Swan ES4118 Super VCD Processor Product Brief DESCRIPTION FEATURES The Swan ES4118 processor is a single-chip solution for Super Video Compact Disk (SVCD) players that integrates MPEG audio and video decoding, as well as system control software. The fully programmable The ES4118 offers the best feature set compared to existing SVCD chips and includes a glueless interface to various peripheral components. The ES4118 is the most cost-effective solution in its class, with levels of integration and quality that establish new benchmarks. The ES4118 processor is capable of decoding MPEG-2 audio simultaneously with MPEG-1 or MPEG-2 video. For embedded applications, the RISC processor core of the ES4118 can be used in place of a microcontroller to provide a rich set of system control features. On-chip, multitap filters provide arbitrary scaling with state-of-the-art SmartScale™ technology that is useful for video standards conversion. SmartStream™ provides video error concealment and video postprocessing, ensuring the highest playability and video quality. The ES4118 connects directly with both 8- and 16-bit ROM and with either 16-bit SDRAM ICs or with EDO DRAM ICs. An 8-bit YUV video interface supports many TV encoders. Generalpurpose auxiliary pins are provided to control various peripheral devices. A standard I2S interface supports popular audio DACs and ADCs. Figure 1 shows a block diagram of a typical standalone system, using the ES4118 with the glueless SDRAM interface. The SVCD data system stream from a CD disc is passed to the ES4118 through the I2S interface. The ES4118 parses the system layer and demultiplexes the audio and video streams. Audio is decoded and passed through the I2S audio serial bus to an external audio DAC and then to the speakers. Video is decoded and output as YUV pixels to an NTSC or PAL video encoder. Onchip system control and housekeeping functions (keypad and remote control) are also provided. • Single-chip SVCD decoder in a 208-pin plastic quad flat package (PQFP) • Supports MPEG-1 system and MPEG-2 program streams • Programmable multimedia processor architecture • Compatible with Audio CD, Video CD 1.1, 2.0, Interactive VCD 3.0, and Super Video CD Video • Trick modes, including Slow, Fast Forward, Fast Reverse, Step, and Goto • 4-bit onscreen display (OSD) with 4-bit blending • 8-bit YUV output Audio • Karaoke function • Supports 256/384iframe sync audio system clock • Bidirectional I2S audio interface Smart Technology • SmartScale™ for NTSC to PAL conversion and vice versa • SmartStream™ for video error concealment Peripheral • • • • • • Independent audio bit clock for transmit and receive port Direct servo/loader interface Supports up to 4 MB of SDRAM and/or 4 MB of EDO DRAM Eight general-purpose auxiliary ports Single 27-MHz clock input Power management BLOCK DIAGRAM Video EPROM Audio CD loader 2 MB SDRAM Swan™ ES4118 NTSC/PAL Encoder Audio Codec Panel Interface TV MIC Speakers Remote Control/ Keypad Figure 1 Typical ES4118 System Block Diagram ESS Technology, Inc. SAM0422-052901 1 ES4118 PRODUCT BRIEF ES4118 PINOUT 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS NC NC NC NC NC NC NC VCC VSS NC NC NC NC NC HD15 HD14 VCC VSS HD13 HD12 HD11 HD10 HD9 HD8 HD7 VCC VSS HD6 HD5 HD4 HD3 HD2 HD1 HD0 VCC VSS HSYNC# VSYNC# PCLKQSCN PCLK2XSCN YUV7 YUV6 YUV5 VSS VCC YUV4 YUV3 YUV2 YUV1 YUV0 DCLK Figure 2 shows the ES4118 device pinout. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Swan ES4118F 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 208-Pin PQFP Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VCC VSS DSCK DQM DCS0# VCC VSS DCS1# DB15 DB14 DB13 DB12 VCC VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VCC DRAS2# DRAS1# DRAS0# DWE# DOE#/DSCK_EN DCAS# VCC VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VCC DMA5 DMA4 DMA3 DMA2 DMA1 DMA0 VCC LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VCC LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VCC TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL1 TSD/SEL_PLL0 VSS VCC SEL_PLL2 NC NC MCLK TBCK NC NC VSS VCC RSD RWS RBCK APLLCAP XIN XOUT VCC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VCC NC VPP AUX0 AUX1 AUX2 VSS VCC AUX3 AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VCC VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VCC LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VCC NC NC LA0 LA1 LA2 LA3 VSS Figure 2 ES4118 Device Pinout 2 SAM0422-052901 ESS Technology, Inc. ES4118 PRODUCT BRIEF ES4118 PIN DESCRIPTION Table 1 lists the ES4118 pin descriptions. Table 1 ES4118 Pin Descriptions List Name VCC LA[21:0] VSS Number I/O 1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 I 7:2, 16:10, 23:19, 207:204 O 8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 I Definition 3.3V power supply. Device address output. Ground. RESET# 24 I Reset input, active low. TDMDX 25 O TDM transmit data. I ROM Select. RSEL RSEL Selection 0 1 16-bit ROM 8-bit ROM. TDMDR 28 I TDMCLK 29 I TDM receive data. TDM clock input. TDMFS 30 I TDM frame sync. TDMTSC# 31 O TDM output enable. TWS 32 O Audio transmit frame sync. TSD 33 O Audio transmit serial data port. I Select PLL0: SEL_PLL2 SEL_PLL0 SEL_PLL2 NC SEL_PLL1 SEL_PLL0 Notes 0 0 1 1 36 I 37, 38, 41, 42, 142:146, 149:155, 158, 202, 203 39 I/O TBCK 40 I/O RSD 45 I Select PLL2. (Refer to the definitions table in pin number 33.) Audio master clock for audio DAC. Audio transmit bit clock. Audio receive serial data. RWS 46 I Audio receive frame sync. RBCK 47 I Audio receive bit clock. APLLCAP 48 I Analog PLL capacitor. XIN 49 I Crystal input. XOUT 50 O Crystal output. 53:58, 61:66 O DRAM address bus. 69 O DRAM column address strobe. DCAS# DOE# DSCK_EN DWE# DRAS[2:0]# DB[15:0] DCS[1:0]# 70 O DRAM output enable. O DRAM clock enable 71 O DRAM write enable. 74:72 O DRAM row address strobe. 77:82, 85:90, 93:96 I/O DRAM data bus. 97, 100 O SDRAM chip select [1:0], active low. DQM 101 O Data input/output mask. DSCK 102 O Clock to SDRAM. 3 SAM0422-052901 2.5 x DCLK 3 x DCLK 3.5 x DCLK 4 x DCLK. No connect. MCLK DMA[11:0] 0 1 0 1 ESS Technology, Inc. ES4118 PRODUCT BRIEF Table 1 ES4118 Pin Descriptions List (Continued) Name Number I/O DCLK 105 I YUV[7:0] Definition Clock input (bypass/test mode). 106:110, 113:115 O 8-bit YUV output. 116 I/O 27 MHz doubled pixel clock. PCLK2XSCN PCLKQSCN 117 I/O 13.5 MHz pixel clock. VSYNC# 118 I/O Vertical sync. HSYNC# 119 I/O Horizontal sync. HD[15:0] 122:128, 131:137, 140:141 I/O VPP AUX[7:0] Host data bus. 159 I 160:162, 165:169 I/O Auxiliary ports. 170 O Device output enable. Chip select [3:0]. LOE# LCS[3:0]# 5V power supply. 173:176 O LD[15:0] 178:182, 185:191, 194:197 I/O LWRLL# 198 O Device write enable. LWRHL# 199 O Device write enable. Device data bus. ORDERING INFORMATION Part Number Description Package ES4118F Super VCD Processor 208-pin PQFP No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. 4 ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,214,125 and others, other patents pending. VideoDrive® is a registered trademark of ESS Technology, Inc. All other trademarks are owned by their respective holders and are used for identification purposes only. © 2001 ESS Technology, Inc. All rights reserved. SAM0422-052901