AKM AK4543

[ASAHI KASEI]
[AK4543]
AK4543
AC’97 Rev 2.1 Multimedia Audio CODEC
General Description
Features
The AK4543 is a 18bit high performance codec compliant with
Audio Codec ’97 Rev 2.1 requirements. The AC Link serial interface
allows the AK4543 to be used with digital controllers as well as
custom logic accelerators to meet full PC98 and PC99 requirements
for a PCI audio solution.
• AC’97 Rev. 2.1 Compliant
• 18bit Resolution A/D and D/A
• Exceeds a PC98/99 Performance Categories:
A/D……………… 90dBA SNR
D/A……………… 90dBA SNR
D/A + Mixer …… 89dBA SNR
A-A……………… 95BA SNR
• Analog Inputs:
4 Stereo Inputs: LINE, CD, VIDEO, AUX
Speakerphone and PC BEEP Inputs
2 Independent MIC Inputs
• Direct PC_Beep Pass Through for lower system costs
• Analog Output:
Stereo LINE Output with volume control
True Line Level with volume control
Mono Output with volume control
• 3D Stereo Enhancement
• Multiple codec Capability
The AK4543 can work as a Primary or Secondary.
• EAPD(External Amplifier Powerdown) Support
• Power Supplies:
Analog 5.0V, Digital 3.3V or 5.0V
• Low Power Consumption
200mW(Analog:5V/Digital:3.3V) at full operation
• 48 Pin LQFP Package
SEL_CMOS
EAPD
SDATA_IN
BIT_CLOCK
RESET#
Codec ID#
The AK4543 can function as a Primary AC’97 or Secondary codec
depending on the codec ID configuration(Multiple codec extension),
making the AK4543 suitable for the docking station application and
multiple codec applications such as 4 speaker output or 6 speaker
output.
Sampling at 48kHz, the AK4543 provides excellent audio
performance, meeting or exceeding all standard requirements. It
offers low power consumption, and flexible power-down modes for
use in laptops, desktop PCs, and aftermarket add-in boards.
Like the earlier pin-compatible AK4540 and AK4542, the AK4543
is available in a compact 48-lead LQFP package.
The AK4543 is a pin compatible upgrade for the AK4540 and
AK4542, some software changes will be required to experience the
extra functions ot the AK4543.
Digital Section
Analog Section
Power Management
18bit
ADC
SYNC
DATA_OUT
The AK4543 provides two pairs of stereo outputs with independent
volume controls along with a mono output, multiple stereo and mono
inputs, are combined to create flexible mixing, gain and mute
functions to provide a complete integrated audio solution for PCs.
AC
Link
Interface
AC'97
Registers
and
Control Signals
Control
Logic
18bit
DAC
Input
Multiplexer
Volume
and
Mute
Control
Voltage
Reference
CD
AUX
VIDEO
MIC1
MIC2
Phone
PC_BEEP
Output
Mixer
Volume
and
Mute
Control
Multiple Codec Support
Clock Generator
LINE_IN
3D Stereo Enhancement
LINE_OUT
TRUE_LINE_LEVEL
MONO_OUT
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
<M0046-E-01>
-11999/01
[ASAHI KASEI]
[AK4543]
LINE_OUT_R
LINE_OUT_L
NC
NC
3Dcap
VRADDA
AFILTR
AFILTL
NC
Vref
AVss1
AVdd1
36
35
34
33
32
31
30
29
28
27
26
25
MONO_OUT
37
24
LINE_IN_R
AVdd2
38
23
LINE_IN_L
LNLVL_OUT_L
39
22
MIC2
NC
40
21
MIC1
LNLVL_OUT_R
41
20
CD_R
AVss2
42
19
CD_GND
TEST2
43
18
CD_L
TEST3
44
17
VIDEO_R
codec ID0#
45
16
VIDEO_L
codec ID1#
46
15
AUX_R
EAPD
47
14
AUX_L
SEL_CMOS
48
13
PHONE
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
8
9
10
11
12
PC_BEEP
XTL_IN
7
RESET#
6
SYNC
5
DVdd2
4
SDATA_IN
3
DVss2
2
DVdd1
<M0046-E-01>
1
-21999/01
[ASAHI KASEI]
[AK4543]
Pin/Function
No.
1
Signal Name
DVdd1
I/O
-
2
I
3
4
XTL_IN
(MCLKI)
XTL_OUT(open)
DVss1
O
-
5
6
SDATA_OUT
BIT_CLK
I
I/O
7
DVss2
-
8
9
SDATA_IN
DVdd2
O
-
10
11
12
13
14
15
16
17
18
19
SYNC
RESET#
PC_BEEP
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
I
I
I
I
I
I
I
I
I
I
20
21
22
23
24
25
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
AVdd1
I
I
I
I
I
-
26
27
AVss1
Vref
O
28
29
30
31
32
33
34
35
36
37
38
NC
AFILTL
AFILTR
VRADDA
3Dcap
NC
NC
LINE_OUT_L
LINE_OUT_R
MONO_OUT
AVdd2
O
O
O
O
O
O
O
-
39
40
41
42
43
44
45
46
47
LNLVL_OUT_L
NC
LNLVL_OUT_R
AVss2
TEST2
TEST3
Codec ID0#
Codec ID1#
EAPD
O
O
I
I
I
I
O
<M0046-E-01>
Description
Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
24.576MHz(512fs) crystal is normally connected.
If a crystal is not connected, an external clock can be used.
24.576MHz(512fs) crystal. If an external clock is used, this pin should be open.
Digital Ground; 0V
This pin should be directly connected to DVss2 on board.
Serial 256-bit AC’97 data stream from digital controller
12.288MHz(256fs) serial data clock
Output when Primary codec(codec ID=00).
Input when Secondary codec(codec ID=01, 10, 11).
Digital Ground; 0V
This pin should be directly connected to DVss1 on board.
Serial 256-bit AC’97 data stream to digital controller
Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
AC’97 Sync Clock, 48kHz(1fs) fixed rate sampling rate
AC’97 Master Hardware Reset
PC Speaker beep pass through
From telephony subsystem speakerphone
Aux Left Channel
Aux Right Channel
Video Audio Left Channel
Video Audio Right Channel
CD Audio Left Channel
CD Audio analog ground; 0V
CD_GND or analog ground should be connected.
CD Audio Right Channel
Desktop Microphone Input
Second Microphone Input
Line In Left Channel
Line In Right Channel
Analog power supply; 5.0V(AVdd1=AVdd2)
0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground).
Analog Ground; 0V
Reference Voltage Output;
0.1µF +4.7µF capacitors should be connected to Avss1(analog ground).
No Connection
Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
Vref for ADC and DAC; 0.1µF capacitor should be connected to analog ground.
3D Enhancement Cap; 27nF capacitor should be connected to analog ground.
No Connection
No Connection
Line Out Left Channel
Line Out Right Channel
To telephony subsystem speakerphone
Analog power supply; 5.0V(AVdd1=AVdd2)
0.1uF capacitor should be connected to AVss2(analog ground).
True Line Level Out Left Channel
No Connection
True Line Level Out Right Channel
Analog Ground; 0V
Test pin (This pin should be open for normal operation)
Test pin (This pin should be open for normal operation)
Codec ID configuration(ID select input for multiple codec extension) See Page20.
Codec ID configuration(ID select input for multiple codec extension) See Page20.
External amplifier powerdown
See Page 20.
-31999/01
[ASAHI KASEI]
[AK4543]
48
SEL_CMOS
I
CMOS/TTL selection for digital input levels
CMOS: Leave open for 3.3V supply.
TTL : Tie to GND for 5V supply.
See Page 28.
Absolute Maximum Rating
AVss1, AVss2, DVss1, DVss2 =0V (Note 1)
Parameter
Symbol
min
Power Supplies
Analog(AVdd1 & AVdd2)
VA
-0.3
Digital(DVdd1 & DVdd2)
VD
-0.3
Input Current (any pins except for supplies)
IIN
Analog Input Voltage
VINA
-0.3
Digital Input Voltage
VIND
-0.3
Ambient Temperature
Ta
-10
Storage Temperature
Ta
-65
Note 1: All voltages with respect to ground .
AGND(AVss1, AVss2) and DGND(DVss1, DVss2) must be the same voltage.
max
Units
6.0
6.0
±10
VA+0.3
VD+0.3
70
150
V
V
mA
V
V
°C
°C
Warning: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Recommended Operating Condition
AGND, DGND=0V (Note 1)
Parameter
Power Supplies
AK4543
Analog
Digital
Note 1 : All voltages with respect to ground.
<M0046-E-01>
Symbol
min
typ
max
Units
VA
VD
4.75
3.135
5.0
3.3 or 5.0
5.25
5.25
V
V
-41999/01
[ASAHI KASEI]
[AK4543]
AK4543 Analog Characteristics
Ta=25°C,AVdd=5.0V±5%, DVdd=3.3V±5% or 5V±5%, fs=48KHz, Signal Frequency =1kHz
All volume setting for ADC/DAC performance measurement is 0dB.
Parameter
min
Typ
Audio-ADC
Resolution
S/N (A weighted)
85
90
S/(N+D)
(-1dB analog input)
70
77
Inter Channel Isolation
70
77
Inter Channel Gain Mismatch
Full Scale Input Voltage
0.88
1.0
Power Supply Rejection
50
Audio DAC: measured at AOUTL/AOUTR via MIXER path
Resolution
S/N (A weighted)
: mixer+DAC measured at AOUT
84
89
S/(N+D)
(-1dB digital input)
75
83
Inter Channel Isolation
70
80
Inter Channel Gain Mismatch
Full Scale Output Voltage
0.83
0.95
Total Out-of-Band Noise (28.8kHz - 100kHz)
-70
Power Supply Rejection
50
MIC Amplifier / MUX
Gain : 20dB is selected
18
20
Master volume (Mono, Stereo, True Line Level Out) : 1.5dB x 32 step
Step Size
-1.5
Attenuation Control Range
-46.5
Load Resistance
10
PC Beep : 3dB x 16 step
Step Size
-3.0
Attenuation Control Range
-45
Analog Mixer : 1.5dB x 32 step
Step Size
-1.5
Gain Control Range
-34.5
Record Gain : 1.5dB x 16 step
Step Size
+1.5
Gain Control Range
0
Mixer
Input Voltage (except for MIC)
1.0
Input Voltage
MIC : Gain = 0dB
1.0
MIC : Gain = 20dB
0.1
S/N(A weighed) : 0dB setting, 1 path is selected at Mixer
CD to AOUT:
85
95
Other analog input to AOUT
95
Input Impedance (Input gain=0dB,Rec_MUTE=off)
PC_BEEP only
(10)
80
Others(PHONE, LINE, CD, AUX, VIDEO)
(10)
40
Input Impedance (MIC1 and MIC2)
(10)
22
Power Supplies
Analog Power Supply Current(AVdd1 & AVdd2)
All ON mode(all PR_bits are 0)
36
Cold Reset status(Reset#=L, Vref is ON)
2.5
All OFF mode(all PR_bits are 1)
0
Digital Power Supply Current(DVdd1 & DVdd2)
All ON mode(all PR_bits are 0) at DVDD=5V
13
All ON mode(all PR_bits are 0) at DVDD=3.3V
6.6
All OFF mode(all PR_bits are 1)
0
<M0046-E-01>
max
Units
18
Bits
dB
dBFS
dB
dB
Vrms
dB
0.5
1.12
18
1.0
1.07
Bits
dB
dBFS
dB
dB
Vrms
dB
dB
22
dB
0
dB
dB
kΩ
0
dB
dB
+12
dB
dB
+22.5
dB
dB
Vrms
Vrms
Vrms
dB
dB
kΩ
kΩ
kΩ
54
5
0.2
mA
mA
mA
20
10
0.2
mA
mA
mA
-51999/01
[ASAHI KASEI]
[AK4543]
Filter Characteristics
Ta=25°C,AVdd=5.0V±5%, DVdd=3.3V±5% or 5V±5% , fs=48KHz(fixed)
Parameter
min
ADC Digital Filter (Decimation LPF)
0
Passband (±0.2dB)
Stopband
28.8
Stopband Attenuation
70
Group Delay
ADC Digital Filter (HPF)
Frequency Response;
-3dB
-0.5dB
-0.1dB
DAC Digital Filter
0
Passband (±0.2dB)
Stopband
28.8
Group Delay
Stopband Rejection
70
DAC Post filter
Passband Frequency Response (0 - 19.2kHz)
typ
Units
19.2
kHz
kHz
dB
ms
0.5
7.5
21
49
Hz
19.2
0.5
±0.1
AK4543 DC Characteristics
Ta=-10∼70°C, VD=5V±5%(SEL_CMOS=L) or 3.3V±5%(SEL_CMOS=H: Open), VA=5V ±5%,
Parameter
Symbol
min
Typ
“H” level input voltage
VIH
0.7xVD
XTAL_IN
RESET#, SYNC, SDATA_OUT, BIT_CLK
At SEL_COMS=L(GND)
2.2
At SEL_COMS=H(Open)
0.7xVD
ID0#, ID1#, SEL_CMOS(Pull up)
0.8xVD
“L” level input voltage
VIL
XTAL_IN
RESET#, SYNC, SDATA_OUT, BIT_CLK
At SEL_COMS=L(GND)
At SEL_COMS=H(Open)
ID0#, ID1#, SEL_CMOS(Pull up)
“H” level output voltage
Iout= -1mA
VOH
VD-0.55
“L” level output voltage
Iout= 1mA
VOL
Input leakage current(exclude pull up pins)
Iin
Pull up resistance
Rup
50
100
<M0046-E-01>
Max
kHz
kHz
ms
dB
dB
50pF external load
Max
Units
V
V
V
V
0.3xVD
V
0.8
0.3xVD
0.2xVD
0.55
±10
200
V
V
V
V
V
µA
kΩ
-61999/01
[ASAHI KASEI]
[AK4543]
Switching Characteristics
Ta=25°C, AVdd=5.0V±5%, DVdd=3.3V±5% or 5V±5%, 50pF external load
Parameter
Symbol
min
Master Clock Frequency
Note)
Fmclk
If Crystal is not used.
45
AC link Interface Timing
BIT_CLK frequency
Fbclk
BIT_CLK clock Period(Tbclk=1/Fbclk)
Tbclk
36.0
BIT_CLK low pulse width
Tclk_low
BIT_CLK high pulse width
Tclk_high
36.0
BIT_CLK rise time
Trise_clk
BIT_CLK fall time
Tfall_clk
SYNC frequency
SYNC low pulse width
Tsync_low
SYNC high pulse width
SYNC rise time
SYNC fall time
Setup time(SYNC, SDATA_OUT)
Hold time(SYNC, SDATA_OUT)
SDATA_IN delay time from BIT_CLK
rising edge
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Cold Rest (SDATA_OUT=L, SYNC=L)
RESET# active low pulse width
RESET# inactive to BIT_CLK delay
Warm Rest Timing
SYNC active low pulse width
SYNC inactive to BIT_CLK delay
Typ
24.576
50
max
55
Units
MHz
%
Tsync_high
-
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
10.0
25.0
-
12.288
81.38
40.7
40.7
48
19.5
(240 cycle)
1.3
(16 cycle)
-
Trise_din
Tfall_din
Trise_dout
Tfall_dout
-
-
6
6
6
6
ns
ns
ns
ns
1.0
162.8
(2 cycle)
-
-
µs
ns
(Tbclk)
Tsync_high
1.0
-
Tsync2clk
162.8
(2 cycle)
1.3
(16 cycle)
µs
(Tbclk)
ns
(Tbclk)
Trst_low
Trst2clk
15
MHz
ns
ns
ns
ns
ns
kHz
µs
(Tbclk)
µs
(Tbclk)
ns
ns
ns
ns
ns
45
45
6
6
6
6
-
AC-link Low Power Mode Timing
End of Slot 2 to BIT_CLK, SDATA_IN
Ts2_pdwn
1.0
µs
Low
Activate Test Mode Timing
Setup to trailing edge of RESET#
Tsetup2rst
15.0
ns
Hold from RESET# rising edge
Thold2rst
100
ns
Rising edge of RESET# to Hi-Z
Toff
50
ns
Falling edge of RESET# to “L”
Tlow
50
ns
Note ) The use of a crystal is recommended. If a master clock is supplied (or if an external oscillator is used),
Master Clock should be supplied to XTAL_IN and XTAL_OUT should be left open.
<M0046-E-01>
-71999/01
[ASAHI KASEI]
[AK4543]
n Power On
Note that a AK4543 must be in cold reset at power on and RESET# must be low until master clock becomes stable,
or a reset must be done once master clock is stable. AVdd or DVdd can be powered from independent supplies.
Vdd
RESET#
SDATA_OUT=”L”
SYNC=”L”
BIT_CLK
Initialize Registers
Trst2clk
start up crystal oscillation
When using the AK4543 in the multiple codec mode, all codec’s connected to the AC-link are waken up at the same
time. A common reset line should be used to insure clock synchronization after power up.
nCold Reset Timing
Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for a cold reset to occur.
The AK4543 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each
analog output is in Hi-Z state except for PC Beep while RESET# pin is low. The PC Beep is directly routed to L
& R line outputs when AK4543 is in Cold Reset. This is done to allow system sounds to be passed to speaker
removing for an internal redundant speaker.
At the rising edge of RESET#, the AK4543 initiates the initialization of analog circuit , which takes 516fs cycles.
After that, the mixer of the AK4543 is ready for normal operation.
Status bit in the slot 0 is “0” (not ready) when the AK4543 is in RESET period ( “L”) or in initialization process.
After initialization cycles, the status bit goes to “1” indicating a ready condition.
Trst_low
Trst2clk
RESET#
VIL
SDATA_OUT=”L”
SYNC=”L”
BIT_CLK
When the AK4543 is used under the multiple codec configuration and when cold reset is issued, all AK4543
connected to the AC-link will execute a cold reset concurrently.
nWarm Reset
The AK4543 initiates a warm reset process by receiving a single pulse on the sync(Pin10). The AK4543 then clears
PR4 bit and PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0 ∼PR3 or
PR6,7 bits in Powerdown Control Register(26h). Note that SYNC signal should synchronize with BIT_CLK after
AK4543 starts to output BIT_CLK clock. And if an external clock is used, an external clock should be supplied
before issuing a sync pulse for warm reset.
Tsync_high
Tsync2clk
SYNC
VIH
BIT_CLK
<M0046-E-01>
-81999/01
[ASAHI KASEI]
[AK4543]
Please refer to Powerdown/Powerup sequence of multiple codec configuration on the warm reset when the AK4543
is used under the multiple codec configuration .(See page 24, 25)
nBIT_CLK Timing
Tclk_low
Tclk_high
BIT_CLK
50%
nSYNC Timing
Tsync_high
Tsync_low
SYNC
VIH
VIL
Tsync_period
nSetup and Hold Timing
Tsetup
Tdelay
VOH
BIT_CLK
VOL
VIH
SDATA_IN
VIL
Thold
VIH
SDATA_OUT
SYNC
VIL
nSignal Rise and Fall Times
(50pF external load : from 10% 90% of DVdd)
Trise_clk
Trise_din
Tfall_clk
SDATA_IN
BIT_CLK
Trise_sync
Tfall_din
Tfall_sync
Trise_dout
SYNC
Tfall_dout
SDATA_OUT
nAC-link Low Power Mode Timing
Slot 1
Slot 2
Ts2_pdwn
BIT_CLK
SDATA_OUT
SDATA_IN
<M0046-E-01>
Write to 0x26
Data PR4=1
Don’t care
Thold
-91999/01
[ASAHI KASEI]
[AK4543]
nActivate Test Mode
VIH
RESET#
SDATA_OUT
VIH
Tsetup2rst
HI-Z
SDATA_IN
BIT_CLK
Toff
nAKM Test Mode
VIH
RESET#
SDATA_OUT=”L”
SYNC
VIH
T setup2rst
Notes:1
1. All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the rising edge of RESET#
causes the AK4543 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that the AK4543 enters in
the ATE test mode regardless SYNC is high or low.
2. Bringing both SYNC high and SDATA_OUT low for the rising edge of RESET# causes AKM test mode.
3. Once test modes have been entered, the only way to return to the normal operating state is to issue “cold reset” which issues RESET#
with both SYNC and SDATA_OUT low.
1
All the following sentences written with small italic font in this document quote the AC’97 component specification.
<M0046-E-01>
- 10 1999/01
[ASAHI KASEI]
[AK4543]
General Description
nAC ‘97 Connection to the Digital AC ’97 controller
2
AC ‘97 communicates with its companion AC ‘97 controller via a digital serial link, “AC-link”. All digital audio streams, and
command/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the
two is shown in the following figure.
AC’97
Controller
AC’97
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
nAC’97 Digital Interface
The AK4543 incorporates a 5 pin digital serial interface that links it to the AC ’97 controller. AC-link is a bi-directional, fixed
rate(48kHz), serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses
employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12
incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4543 is 18 bit resolution. The data
streams currently defined by the AC ‘97 specification include:
l PCM Playback
2 output slots
2 channel composite PCM output stream
l PCM Record data
2 input slots
2 channel composite PCM input stream
l Control
2 output slot
Control register write port
l Status
2 input slots
Control register read port
SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising
edge of BIT_CLK. The receiver of AC-link data, the AK4543 for outgoing data and AC ’97 controller for incoming data, samples each
serial bit on the falling edges of BIT_CLK.
The AK4543 outputs BIT_CLK when it is assigned as Primary codec by the codec ID configuration ID1# and ID0#. The other hand, the
AK4543 receives BIT_CLK when assigned as the Secondary codec from the Primary device.
The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot
within the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time slot within the current audio
frame has been assigned to a data stream, and contains valid data. If a slot is “Tagged” invalid, it is the responsibility of the source
of the data, (The AK4543 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s
active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where
SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is defined as the “Data Phase”.
Note that SDATA_OUT and SDATA_IN data is delayed one BIT_CLK because AC’97 controller causes
S Y N C signal high at a rising edge of BIT_C L K which initiates a frame.
“Output” stream means the direction from AC ’97 controller to the AK4543, and “Input” stream means the direction
from the AK4543 to AC’97 controller
2
All the following sentences written with small italic font in this document quote the AC’97 component specification.
<M0046-E-01>
- 11 1999/01
[ASAHI KASEI]
[AK4543]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
SYNC
Codec ID1:Codec ID0=0:0 or 0:1
SDATA
OUT
TAG
Command Command PCM(dac) PCM(dac)
Address
Data
Left
Right
Codec ID1:Codec ID0=1:0
TAG
Command Command
Address
Data
All
“0”
All
“0”
All
“0”
All
“0”
PCM(dac) PCM(dac)
Left
Right
All
“0”
All
“0”
All
“0”
PCM(dac)
Left
All
”0”
All
“0”
PCM(dac)
Right
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
Codec ID1:Codec ID0=1:1
TAG
SDATA
IN
TAG
Command Command
Address
Data
Status
Address
Status
Data
PCM(adc) PCM(adc)
Left
Right
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
Primary codec (Codec ID1: Codec ID0 = 0 : 0)
SYNC
BIT_CLK
SDATA_OUT
Valid
Frame
Slot3
Slot4
Slot5
Slot6
Slot7
Slot9
Slot10 Slot11 Slot12
Bit13 Bit12
Bit11
Bit10
Bit9”
Bit8
Bit7”
Bit6”
Bit5”
Bit4
Bit3
Bit2
Bit1
Bit0
“1/0” “1/0” “1/0” “1/0” “1/0”
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“0”
Slot1
Bit15 Bit14
Slot2
Slot8
Slot 0
1 BIT_CLK delay
Slot 1
Secondary codec (Codec ID1 : Codec ID0 = 0 : 1 or 1 : 0 or 1 :1 )
SYNC
BIT_CLK
SDATA_OUT
1 BIT_CLK delay
Valid
Frame
Slot3
Slot4
Slot5
Slot6
Slot7
Bit15 Bit14
Bit13 Bit12
Bit11
Bit10
Bit9”
Bit8
“1/0” “0”
“0”
Slot1
Slot2
“1/0” “1/0” “0”
Slot8
Bit7”
Slot9
Slot10 Slot11 Slot12
Bit6”
Bit5”
“1/0” “1/0” “1/0” “1/0” “0”
Slot 0
Bit4
Bit3
Bit2
Bit1
Bit0
“0”
“0”
“0”
“1/0”
“1/0”
Slot 1
The AK4543 checks bit15 (valid frame bit). Note that when the valid frame bit is “1”, at least one bit14-6 (slot 19) or bit1-0 must be valid, bit5-2 will be “0”and should be ignored.
If bit15 is “0”, the AK4543 ignores all following information in the frame.
The AK4543 then checks the validity of each bit in the TAG phase (slot 0).
If each bit is “0”, the AK4543 ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid.
All bits in slot10-12(bit5-3) are “0” and bit2 is also “0”.
The AK4543 monitors bit1 and 0, which are codec ID configuration bits used in multiple codec implementations.
These bits are used to identify which codec the frame data is issued to.
<M0046-E-01>
- 12 1999/01
[ASAHI KASEI]
[AK4543]
When codec ID configuration bits1 and 0 which are set by the codec ID configuration 45/46 strapping pins(codec
ID0# and ID1#) are set to zero(00), the frame is aimed for the Primary codec. And when codec ID configuration bit1
and 0 are set to non-zero values(01, 10, or 11), the frame is meant for Secondary codec.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AK4543 on the following falling edge of BIT_CLK. This sequence ensures that data
transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Data should be sent to the AC’97 codec with MSB first through the Pin labled SDATA_OUT.
The following table shows the relationship of bits14&13 and the Read/Write operation s depending on codec ID
configuration.
Bit 15
Valid Frame
1
1
1
Bit 14: Slot1 Valid Bit
(Command Address)
1
0
1
1
0
Bit 13: Slot 2 Valid Bit
(Command Data)
1
1
0
Read/Write Operation of
Primary AK4543
Read/Write(Normal Operation)
Ignore
Read: Normal Operation
Write: Ignore
0
Ignore
AK4543 Addressing: Slot0 Tag Bits
Read/Wirte Operation of
Secondary AK4543
Ignore
Ignore
Ignore
Read/Write(Normal Operation)
b)Slot1:Command Address Port
Slot1 gives the address of the command data, which is given in the slot 2. The AK4543 has 20 valid registers of
16bit data. See Page17(See AC’97 register map).
BIT_CLK
Bit19 Bit18
SDATA_OUT
Bit17 Bit16
Bit15 Bit14
Bit13 Bit12
“1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0”
Slot 0
Bit11
Bit10
Bit9
Bit9
Bit2
Bit1
Bit0
“0”
“0”
“0”
“0”
“0”
“0”
“0”
Slot 1
Bit19 Bit18
Bit17
Bit16
Slot 2
Command Address Port
Bit 19:
Bit 18:12
Bit 11:0
Read/Write command
1=read, 0=write
Control Register Index (see “AC’97 register map” for the detail)
Reserved (“0”)
Bit18 is equivalent to the most significant bit of the index register address.
The AK4543 ignores from bit11 to bit0. These bits will be reserved for future enhancement and must be stuffed
with 0’s by the AC’97 controller.
c)Slot2:Command Data Port
BIT_CLK
SDATA_OUT
Slot 1
Bit19:4
Bit3:0
Bit19 Bit18
Bit17 Bit16
Bit15 Bit14
Bit13 Bit12
“1/0” “1/0”
“1/0” “1/0” “1/0” “1/0” “1/0” “1/0”
Bit6
Bit5
Bit4
Bit3
“1/0” “1/0” “0”
Slot 2
Bit2
Bit1
Bit0
“0”
“0”
“0”
Bit19 Bit18
Bit17
Bit16
Slot 3
Command Data Port
Control Register Write Data (if bit 19 of slot 1 is “1”, all Bit19:4 should be “0”)
Reserved(“0”)
If bit19 in slot1 is “0”, a write command, the AC’97 controller must output Command Data Port data in slot 2 of the
same frame. If the bit19 in slot1 is “1”, a read, the AK4543 will ignore any Command Data Port data in slot2.
Bit19 is equivalent to D15 bit of mixer register value.
<M0046-E-01>
- 13 1999/01
[ASAHI KASEI]
[AK4543]
d)Slot3 PCM Playback Left Channel (18bits)
In the case of codec ID1:codec ID0=0:0 or 0:1, the AK4543 uses the playback(DAC) data format in slot3 for left
channel.
Playback data format is 18bits MSB first 2’s complement. The AC’97 controller should stuff bit s1-0 with “0”. If
valid bit (slot3) in the slot 0 is invalid (“0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
e)Slot4 PCM Playback Right Channel (18bits)
In the case of codec ID1:codec ID0=0:0 or 0:1, the AK4543 uses the playback(DAC) data format in the slot4 for right
channel. Playback data format is MSB first. Data format is 18bits 2’s complement. The AC’97 controller should
stuff bits1-0 with “0”. If valid bit (slot 4) in the slot 0 is invalid ( “0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
f)Slot5 is Not used in the AK4543
The AK4543 will ignore stuffed in this slot.
g)Slot6 PCM Playback Left Channel (18bits)
In case of codec ID1:codec ID0=1:1, the AK4543 uses the playback(DAC) data in slot 6 for left channel.
Playback data format is 18bits MSB first 2’s complement. The AC’97 controller should stuff bit1-0 with “0”. If valid
bit (slot6) in the slot 0 is invalid ( “0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
h)Slot7 PCM Playback Left Channel (18bits)
In case of codec ID1:codec ID0=1:0, the AK4543 uses the playback(DAC) data in slot7 for left channel.
Playback data format is 18bits MSB first 2’s complement. The AC’97 controller should stuff bit1-0 with “0”. If valid
bit (slot7) in the slot 0 is invalid ( “0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
i)Slot8 PCM Playback Right Channel (18bits)
In case of codec ID1:codec ID0=1:0, the AK4543 uses the playback(DAC) data in slot8 for right channel.
Playback data format is 18bits MSB first 2’s complement. The AC’97 controller should stuff bit1-0 with “0”. If valid
bit (slot8) in the slot 0 is invalid ( “0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
j)Slot9 PCM Playback Right Channel (18bits)
In case of codec ID1:codec ID0=1:1, the AK4543 uses the playback(DAC) data in slot 9 for right channel.
Playback data format is 18bits MSB first 2’s complement. The AC’97 controller should stuff bit1-0 with “0”. If valid
bit (slot9) in the slot 0 is invalid ( “0”), the AK4543 interprets the data as all “0”.
Bit19:2
Playback data
Bit 1:0
“0”
k)Slot10-12 is Not used in the AK4543
The AK4543 will ignore stuffed in these data slots.
<M0046-E-01>
- 14 1999/01
[ASAHI KASEI]
[AK4543]
nAC-link Input Frame(SDATA_IN)
Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control.
a)Slot0
Slot0 is a special frame, and consists of 16bit s. Slot0 is also called the “Tag phase”. The AK4543 supports bits
15-11 and bits1-0. Each bit indicates “1”=valid(normal operation) or ready, “0”=invalid(abnormal operation) or not
ready.
If the first bit in the slot 0 is valid, the AK4543 is ready for normal operation. 3If the “Codec Ready” bit is invalid,
the following bits and remaining slots are all “0”. The AC’97 controller should ignore the following bits in the slot
0 and all other slots.
Bit 14 means that Slot 1(Status Address) output is valid or invalid. And Bit 13 means that Slot 2(Status Data ) is
valid or invalid.
The following table shows the relationship between Bit 14,13 and each Status of the AK4543.
Bit 15
(Codec Ready)
1
Bit 14
(Status Address)
1
Bit 13
(Status Data)
1
Status
There is a Read Command in the previous frame.
Then both Slot 1 and Slot 2 output normal data.
If the access to non-implemented register or odd register is requested, the AK4543
returns “valid 7-bit register address in slot 1 and returns “valid”0000h data in slot
2 on the next AC-link frame.
1
1
0
Prohibited or non-existing
1
0
0
There is no Read Command in the previous frame. Both Slot 1 and Slot 2 output
All”0”.
1
0
1
Prohibited or non-existing
Note 1). The above Read sequence is done as response for previous frames read command. That is, if the previous
frame is a Write Command, AK4543 outputs bit1 4 =”0”, bit13 =”0” and slot 1&2 = All”0”.
Bit12 means the output of Slot 3( PCM(ADC) Left) is valid or invalid. And Bit 11 means the output of Slot
4(PCM(ADC)Left) is valid or invalid. Bits10-0 are filled with “0”.
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4543 transitions SDATA_IN
into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and
subsequently sampled by the AC ’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions,
and subsequent sample points for both incoming and outgoing data streams are time aligned.
SYNC
BIT_CLK
Codec
Ready
SDATA_IN
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot11 Slot12
“1/0” “1/0” “1/0” “1/0” “1/0” “0”
“0”
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
“0”
Bit8
“0”
Bit7
“0” “0”
Bit4 Bit3
Slot 0
b)Slot1
“0”
Bit2
“0” “0”
Bit1 Bit0
Slot 1
Status Address Port
Audio input frame slot1’s stream echoes the control register index, for historical reference, for the data to be returned in slot2.
(Assuming that slots1 valid bit and slot2 valid bit in the slot0 had been tagged “valid” by the AK4543)
BIT_CLK
SDATA_IN
Slot 0
Bit19 Bit18
Bit17 Bit16
“0”
“1/0” “1/0” “1/0” “1/0” “1/0” “1/0”
“1/0”
Bit15 Bit14
Bit13 Bit12
Bit11
Bit10
Bit9
Bit9
Bit2
Bit1
Bit0
“0”
“0”
“0”
“0”
“0”
“0”
“0”
Slot 1
Bit19 Bit18
Bit17
Bit16
Slot 2
Status Address Port
3
When the AC’97 is not ready for normal operation, output bits are not specified in this documents and should be considered as
invalid.
<M0046-E-01>
- 15 1999/01
[ASAHI KASEI]
[AK4543]
This address shows the register index for which data is being returned in the slot2.
This address port is a copy of slot1 of the output frame, and index address input to SDATA_OUT is loop ed back to
the AC’97 controller through SDATA_IN. This allows the controller to insure the AK4543 receives the correct data.
c)Slot2: Status Data Port
Status data addressed by the command address port of Output Stream is output through SDATA_IN pin.
Bit19:4
Control Register Read Data (the contents of indexed address in the slot 1)
Bit3:0
“0”
Note that the address of Status Data Port data is consistent with Status Address Port data of slot 1 in the same
frame. If the read operation is issued in the frame N by the AC’97 controller, Status Data Port data is output
through SDATA_IN in the frame N+1. Note that data is only available in this frame, only one time and that
the following frames are invalid if another read operation is not issued.
d)Slot3: PCM Record Left Channel
Record(ADC) data format is 18bits MSB first 2’s complement. Lower 2bits of the frame are ignored. If ADC block
is powered down, slot-3 valid bit in the slot 0 is invalid ( “0”), and data is as all “0”.
Bit19:2
Bit1:0
Audio ADC left channel output
“0”
e)Slot4: PCM Record Right Channel
Record(ADC) data format is 18bits MSB first 2’s complement. Lower 2bits of the frame are ignored. If ADC block
is powered down, slot-4 valid bit in the slot 0 is invalid ( “0”), and data is as all “0”.
Bit19:2
Audio ADC right channel output
Bit1:0
“0”
f)Slot5: Modem Line Codec
The AK4543 does not incorporate the modem codec, all bits are stuffed with “0” in this slot.
Bit19:0
“0”
g)Slot6: Microphone Record Data
The AK4543 does not incorporate the 3rd ADC for microphone, all bits are stuffed with “0” in this slot.
Bit19:0
“0”
h)Slots7-12
Bits19:0
<M0046-E-01>
Reserved for future enhancement
“0”
- 16 1999/01
[ASAHI KASEI]
[AK4543]
nAC’97 Register Map
Each Register is a 16bit word.
Note: The AK4543 outputs “valid” 0000h if the controller reads an unused or invalid register address .
Reg
Num
00h
02h
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Reset
Master Volume
0
“0”
X
“1”
ML5
“0”
ML4
“1”
ML3
“1”
ML2
“0”
ML1
“0”
X
“1”
X
“1”
“0”
“0”
MR5
MR4
MR3
MR2
04
LINVL Volume
Mute
X
ML5
ML4
ML3
ML2
ML1
X
X
MR5
MR4
MR3
MR2
06h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
20h
22h
26h
28h
7Ch
7Eh
Master Volume Mono
PC_BEEP Volume
Phone Volume
Mic Volume
Line In Volume
CD Volume
Video Volume
Aux Volume
PCM Out Volume
Record Select
Record Gain
General Purpose
3D Control
Powerdown Ctrl/Stat
Extended Audio ID
Vendor ID1
Vendor ID2
Mute
Mute
Mute
Mute
Mute
Mute
Mute
Mute
Mute
X
X
X
X
X
X
X
X
X
X
X
X
X
PR6
ID0
“1”
“1”
X
X
X
X
X
X
X
X
X
X
X
3D
X
PR5
X
“0”
“0”
X
X
X
X
GL4
GL4
GL4
GL4
GL4
X
X
X
X
PR4
X
“0”
“0”
X
X
X
X
GL3
GL3
GL3
GL3
GL3
X
GL3
X
X
PR3
X
“0”
“1”
X
X
X
X
GL2
GL2
GL2
GL2
GL2
SL2
GL2
X
X
PR2
X
“0”
“1”
X
X
X
X
GL1
GL1
GL1
GL1
GL1
SL1
GL1
MIX
X
PR1
“1”
ML
0
ML
0
X
X
X
X
GL0
GL0
GL0
GL0
GL0
SL0
GL0
MS
X
PR0
X
“1”
“1”
“0”
Mute
X
X
X
X
X
X
X
X
X
X
X
LPBK
X
X
X
“0”
“0”
X
X
X
MR5
MR4
MR3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
“0”
“0”
PV3
GN4
GN4
GR4
GR4
GR4
GR4
GR4
X
X
X
X
X
X
“0”
“0”
PV2
GN3
GN3
GR3
GR3
GR3
GR3
GR3
X
GR3
X
X
REF
X
“1”
“0”
X
Mute
POP
X
PR7
ID1
“0”
“0”
AMAP
“0”
“0”
20dB
X
X
X
X
X
X
X
X
X
X
X
“1”
“0”
D4
D3
D2
D1
D0
Default
“0”
“0”
MR1
MR0
2D50h
8000h
MR1
MR0
8000h
MR2
MR1
MR0
PV1
GN2
GN2
GR2
GR2
GR2
GR2
GR2
SR2
GR2
X
X
ANL
X
“0”
“0”
PV0
GN1
GN1
GR1
GR1
GR1
GR1
GR1
SR1
GR1
X
X
GN0
GN0
GR0
GR0
GR0
GR0
GR0
SR0
GR0
X
DP1
DAC
DP0
ADC
X
“1”
“1”
X
“1”
“0”
8000h
0000h
8008h
8008h
8808h
8808h
8808h
8808h
8808h
0000h
8000h
0000h
0000h
na
x200h
414Bh
4D02h
*) Vender ID of AKM is “AKM” :This ID has been approved by Intel.
*) The AK4543 outputs “X” bits as “0”.
*) A write on “Invalid” registers will not affect the operation of the AK4543.
*) ANL, DAC, ADC Bit in register 26h are all “0” following cold reset. When each section is ready for normal
operation, the coresponding bit becomes “1”. The Powerdown register(26h) is not affected by a write to Reset
register(0h). See “Mixer Registers” in AC’97 specification for details. Vref is controlled only by PR3.
nReset Register (Index 00h)
<Write>
When any value is written to this register , all registers in the AK4543 except for register “26h” Powerdown
Ctrl/Stat Register are reset to the default values. The value of this register is not altered.
<Read>
Reading this register returns “2D50h”composed of the ID code of the part, a code for the type of 3D enhancement,
18
bit ADC/DAC resolution, and a code for True Line Level Out.
*Setting D14 – D10 “01011” means AKM 3D enhancement which is registered in Audio Codec ’97 Component
Specification Rev 1.03 and 2.1 .
*Setting D8 “1” indicates 18bit ADC resolution and D6 ”1” does DAC resolution.
*Setting D4 “1” means True Line Level Out is supported with Volume Control(Index 04h).
n Play Master Volume Registers (Index 02h ,06h) and LINVL(True Line Level Out) Volume Register(Index 04h)
The following table shows the relationship between bits and the attenuation value with step size of 1.5dB. The
AK4543 has a range of 0dB to –46.5dB. The AK4543 does not support the optional MX5 bit.
The AK4543 d e t e c ts when MX5 is set and set all 5 LSBs to 1s. Example: When the driver writes a “01xxxxx” the AK4543
interpret that as “0011111”. When this register is read, the returned value is “0011111”.
Mute
0
0
0
0
0
0
0
1
MX5 MX4 MX3 MX2 MX1 MX0
Att.
0
0
0
0
0
0
0dB
0
0
0
0
0
1
-1.5dB
0
0
0
0
1
0
-3.0dB
0
0
0
0
1
1
-4.5dB
------------------------------------------------------------------------0
1
1
1
1
0
-45.0dB
0
1
1
1
1
1
-46.5dB
------------------------------------------------------------------------1
X
X
X
X
X
-46.5dB
------------------------------------------------------------------------X
X
X
X
X
X
Mute
<M0046-E-01>
- 17 1999/01
[ASAHI KASEI]
[AK4543]
n PC Beep Register (Index 0Ah)
The following table shows the relationship between bits and the attenuation value. The attenuation step is -3dB
with a range of 0 to –45dB. PC_BEEP of the AK4543 is mute off at default state.
The PC Beep is routed to L & R Line outputs directly when AK4543 is in a RESET State(Reset# is “L”). This is so that Power on Self
Test(POST) codes can be heard by the user in case of a hardware problem with the PC. After Reset# goes “H”, direct PC beep pass
thru becomes OFF.
Mute
PV3
PV2
PV1
PV0
Att.
0
0
0
0
0
0dB
0
0
0
0
1
-3.0dB
0
0
0
1
0
-6.0dB
-------------------------------------------------------------0
1
1
1
1
-45.0dB
1
X
X
X
X
Mute
n Analog Mixer Input Gain Registers (Index 0Ch-18h)
The following table shows the relationship between bits and the gain/attenuation value. Attenuation step is 1.5dB
with a range of +12dB to –34.5dB.
Mute
Gx4
Gx3
Gx2
Gx1
Gx0
Att.
0
0
0
0
0
0
+12dB
0
0
0
0
0
1
+10.5dB
----------------------------------------------------------------------0
0
1
0
0
0
0dB
0
0
1
0
0
1
-1.5dB
----------------------------------------------------------------------0
1
1
1
1
0
-33.0dB
0
1
1
1
1
1
-34.5dB
1
X
X
X
X
X
Mute
n Record Select Control Register (Index 1Ah)
SR2
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Att.
Mic
CD In (R)
Video In (R)
Aux In (R)
Line In (R)
Stereo Mix (R)
Mono Mix
Phone
SR2
0
0
0
0
1
1
1
1
SL1
0
0
1
1
0
0
1
1
SL0
0
1
0
1
0
1
0
1
Att.
Mic
CD In (L)
Video In (L)
Aux In (L)
Line In (L)
Stereo Mix (L)
Mono Mix
Phone
<M0046-E-01>
- 18 1999/01
[ASAHI KASEI]
[AK4543]
n Record Gain Register (Index 1Ch)
Mute
Gx3
Gx2
Gx1
Gx0
Gain
0
0
0
0
0
0dB
0
0
0
0
1
1.5dB
0
0
0
1
0
3.0dB
-------------------------------------------------------------0
1
1
1
1
22.5dB
1
X
X
X
X
Mute
n General Purpose Register (Index 20h)
The following table indicates how to control several miscellaneous functions of the AK4543.
Bit
POP
D15
3D
D13
MIX
D9
MS
D8
LPBK
D7
Function
PCM(DAC) Bypass 3D
0= Via 3D Path, 1= 3D Bypass
3D Stereo Enhancement
0=Off, 1=On
Mono Output Select
0=Mix, 1=Mic
Mic Select
0=Mic1, 1 =Mic2
ADC/DAC Loopback Mode
1= Loopback
An active bit(“1”) in D15(POP) will pass DAC output to Line_OUT or LNLVL_OUT directly, while a “0” in D15 will
put DAC output into Input Mixers or AKM’s 3D enhancement circuit.
D13(3D) will activate the AKM’s 3D enhancement.
LPBK(ADC/DAC Loopback Mode) bit enables loopback of the ADC output to slot3 &4 of DAC input for
both the Primary codec and Secondary codec on the same AC-Link. Generally done for system testing.
n 3D Control Register (Index 22h)
The following table shows the relationship between the bit and depth of 3D enhancement.
DP1
0
0
1
1
DP0
0
1
0
1
<M0046-E-01>
Depth
0%
50%
70%
100%
Recommended Application
Off
Audio
Audio
Game
- 19 1999/01
[ASAHI KASEI]
[AK4543]
n Powerdown Control/Status Register (Index 26h )
BitsD0 to D3 are read only status bits. Any write to these bits will not affect the operation of the AK4543. These
bits are used as status bits to subsections of the AC ’97 codec. A “1” indicates the subsection of the AK4543 is
“ready” or that is capable of performing in normal operation.
Bit
REF
D3
ANL
D2
DAC
D1
ADC
D0
Function
Vref up to nominal state
0=NOT ready, 1=ready,
Analog mixers, etc ready
0=NOT ready, 1=ready
DAC section ready to accept data
0=NOT ready, 1=ready
ADC section ready to transmit data
0=NOT ready, 1=ready
The power down modes are as follows.
Bit
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
D8
D9
D10
D11
D12
D13
D14
D15
Function
PCM in ADC’s & Input Mux Powerdown
PCM out DACs Powerdown
Analog Mixer Powerdown (Vref still on)
Analog Mixer Powerdown (Vref off)
Digital Interface (AC-link) Powerdown
Internal Clk disable
True Line Level Out Powerdown
EAPD(External Amplifier Powerdown)
When PR3 is set to “1”, the ADC, DAC, Mixer, True Line Level Out, and VREF are powered down even if any PRx
bit are “0”. When PR3 bit is reset to “0”, the AK4543 resumes the previous state by referencing previous PRx bit. In
this case, the AK4543 outputs corresponding slot-x valid bits in the slot 0 as “0” until the AK4543 results in normal
operation(Codec Ready) .
EAPD(External Amplifier Power Down) bit controls an external audio amplifier. EAPD=”0” places a “0”(L) on the
output pin, enabling an external audio amplifier, EAPD= ”1”(H) shuts it down. Powered up default is
EAPD=”0”(external audio amplifier enabled).
n Extended Audio ID(Index 28h)
The Extended Audio ID(28h) is a read only register. 2bits D15&D14 can be read for codec identification. D15 ,14
are automatically set with the codec ID1#(46pin) and ID0#(45pin). ID1# and ID0# can be strapped and adopt
inverted polarity and default to 00= Primary(via internal pull up) when left floating. Depended on codec ID
configuration, the AK4543 is assigned to Primary codec or Secondary codec. Note that codec ID configuration has to
be fixed before Powering up of the device.
ID1#(pin 46)
Physical
Logic
Connection
Value
NC
0
NC
0
GND
1
GND
1
ID0#(pin45)
Physical
Logic
Connection
Value
NC
0
GND
1
NC
0
GND
1
Configuration
(Codec ID)
Primary ID00
Secondary ID01
Secondary ID10
Secondary ID11
The AMAP (bit D9 of this read only register) will always be set to “1” indicating that DAC input slot will follow to
AC’97 recommendation as shown in next table.(CODEC ID is configured via ID1#m ID0# pins)
The audio DAC mapping can be changed based on the codec ID configuration.
Codec ID
00
01
10
11
AC-link Frame Data used for DACs
PCM Left DAC uses PCM Right DAC
data from Slot#
uses data from Slot#
3
4
3
4
7
8
6
9
<M0046-E-01>
Comments
Expected use
Original Definition(Master)
Original Definition(Docking)
Left/Right surround channels
Center/LFE channels
- 20 1999/01
[ASAHI KASEI]
[AK4543]
n Vendor ID Registers (Index 7Ch , 7Eh)
This register is a read only register that is used to determine the specific vendor identification. The ID method is Microsoft Plug and
Play Vendor ID code with upper byte of 7Ch register, the first character of that id, lower byte of 7Ch register, the second character and
upper byte of 7Eh register the third character. These three characters are ASCII encoded. Lower byte of 7E register is for the Vendor
Revision number.
AKM’s vender ID is “AKM”, and revision number is 02. As ASCII code “A” is 41h, “K” is 4Bh, and “M” is 4Dh,
Vendor ID registers are 414Bh and 4D0 2h respectively.
<M0046-E-01>
- 21 1999/01
[ASAHI KASEI]
[AK4543]
AK4543 Block Diagram
3Dcap
PD 26[10]
PD 26[10]
AK4543
PC_BEEP
PC_VOL (0A[4:1])
Mute(0A[15])
PHONE
GAIN (0C[5:0])
Mute(0C[15])
LINE_IN_
GAIN(10[12:8])
Mute(10[15])
LINE_IN_R
GAIN (10[4:0])
Mute(10[15])
PD 26[10]
LNLVD Volume
04[13:8]
Mute
04[15]
LNLVL_OUT_L
LNLVL Volume
04[5:0]
Mute
04[15]
LNLVL_OUT_R
PD 26[14]
Mixer
PD 26[10]
Mixer
RESET#
CD_L
CD_GND
CD_R
GAIN (12[12:8])
Mute(12[15])
GAIN (12[4:0])
Mute(12[15])
VIDEO_L
GAIN (14[12:8])
Mute(14[15])
VIDEO_R
GAIN (14[4:0])
Mute(14[15])
AUX_L
GAIN (16[12:8])
Mute(16[15])
AUX_R
GAIN (16[4:0])
Mute(16[15])
Mixer
<Left>
Mixer
<Right>
∑(L)
20dB
Mux
3D 20[13]
∑(L)
Mute
02[15]
LINE_OUT_R
Mux
3D 20[13]
∑(R)
Mixer
1/2
∑
Mux
Mute
06[15]
Mono Volume
06[5:0]
1/2
MIC2
Mute(18[15])
GAIN (18[12:8])
DAC.L
Mute(18[15])
GAIN (18[4:0])
DAC.R
POP 20[15]
SEL_CMOS
AC’97
20[7]
Mixer
∑
MONO_OUT
Mux 20[9]
Mute(0E[15])
Mux
(20[8])
LINE_OUT_L
Mux
RESET#
Master Volume
02[5:0]
∑
PD 26[10]
GAIN (0E[5:0])
∑
22[1:0]
∑(R)
Mute
02[15]
Master Volume
02[13:8]
Mixer
(0E[6])
MIC1
Mixer
3D
1/2
Digital
20[7] Interface
SYNC
BIT_CLK
PD 26[9]
Registers
SDATA_OUT
Mux
1A[10:8]
Mux
1A[2:0]
GAIN
1C[11:8]
Mute
1C[15]
ADC.L
GAIN
1C[3:0]
Mute
1C[15]
ADC.R
SDATA_IN
RESET#
EAPD
PD 26[11]
Codec ID0#
PD 26[8]
PD 26[8]
Codec ID1#
Voltage Reference
PD 26[13]
PD 26[8]
PD 26[13]
Vref
VRADDA
<M0046-E-01>
AVdd1
AVss1
AVdd2
Avss2
TEST2
TEST3
XTL_IN
PD 26[16]
XTL_OUT
AFILT2
AFILT1
DVss1
DVdd1
DVss2
DVdd2
- 22 1999/01
[ASAHI KASEI]
[AK4543]
nPower Management/Low Power Modes
The AK4543 is capable of operating at multiple reduced power modes for when no activity is required. The state of power down is
controlled by the Powerdown Register (26h). There are 8 separate commands for power down. See the table below for the different
modes. As the AK4543 operates at static mode, the registers will not lose their values even if the master clock is stopped only upon
power.
Powerdown Mode Truth Table
ADC
DAC
Mixer
VREF
ACLINK
PR0=”1”
PD
don’t care
don’t care
don’t care
Don’t care
PR1=”1”
don’t care
PD
don’t care
don’t care
Don’t care
PR2=”1”
don’t care
don’t care
PD
don’t care
Don’t care
(No DAC out)
PR3=”1”
PD
PD
PD
PD
Don’t care
PR4=”1”
PD
PD
don’t care
don’t care
PD
PR5=”1”
PD
PD
don’t care
don’t care
PD
PR6=”1”
don’t care
don’t care
don’t care
don’t care
Don’t care
PR7=”1”
don’t care
don’t care
don’t care
don’t care
Don’t care
*: PD means Powerdown .
*: No DAC out means that there is no PCM out because mixer is disabled.
Internal CLK
don’t care
don’t care
don’t care
LNLVL_OUT
don’t care
don’t care
PD
EAPD
don’t care
don’t care
don’t care
don’t care
don’t care
PD
don’t care
don’t care
PD
don’t care
don’t care
PD
don’t care
don’t care
don’t care
don’t care
don’t care
PD
From normal operation sequential writes to the Powerdown Register are performed to power down subsections of the AK4543 one at
a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC ’97 digital interface (AC-link).
The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC ‘97 controller will send a pulse
on the sync line issuing a warm reset. This will restart the AK4543 digital (resetting PR4 to zero). The AK4543 can also be woken up
with a cold reset. A cold reset will cause a loss of values of the registers as a cold reset will set them to their default states. When a
subsection is powered back on the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready
(i.e. stable) before attempting any operation that requires its normal operation.
And the below figure illustrates one example of procedure to do a complete powerdown/power up of AK4543.
PR0=1
PR1=1
ADCs off
PR0
Normal
PR0=0
&
ADC=1
PR2=1
Analog
off
PR2 or
PR3
DACs off
PR1
PR1=0
&
DAC=1
PR4=1
PR2=0
&
ANL=1
Digital I/F
off
PR4
Shut off
AC-Link
Warm Reset
Cold Reset
Default
Ready = 1
One example of AK4543 Powerdown/Powerup flow
When PR3 bit is set to “1”, the ADC, DAC, Mixer, True Line Level Out, and VREF will be powered down even if any
PRx bits are “0”. When PR3 bit is reset to “0”, the AK4543 resumes with the previous state by referencing PRx bit.
In this case, the AK4543 outputs “0” (invalid) for corresponding slot-x valid bits in the slot 0 until the
corresponding block of the AK4543 is operating with normal operation.
Setting the PR4 bit causes the Powerdown mode of AK4543 and AC-Link of AK4543 shut down. In this case, when
Warm Reset is executed, PR4 bit is cleared and the AC-Link is reactivated. A cold reset is issued , the AK4543 is
restored to operation with the default register settings.
In addition, setting PR5 bit causes the Powerdown mode of AK4543 and the internal clock of AK4543 to be stopped.
When a warm reset is done in this case, PR5 bit is cleared to 0 and internal clock and AC-Link are reactivated.
When Cold reset is executed, AK4543 is set up to the operation with default register setting, no powerdown modes
active.
<M0046-E-01>
- 23 1999/01
[ASAHI KASEI]
[AK4543]
The next figure illustrates a state when all the mixers should work with the static volume settings that are
contained in their associated registers. This is used when the user is playing a CD (or external LINE_IN source)
through the AC ‘97 codec to the speakers but has most of the system in a low power mode. The procedure for this
follows the previous except that the analog mixer is never shut down.
PR0=1
PR1=1
ADCs off
PR0
Normal
PR4=1
Digital
I/F
off
PR4
DACs off
PR1
PR0=0
&
ADC=1
PR1=0
&
DAC=1
Shut off
AC-Link
Warm Reset
AK4543 Powerdown/Powerup flow with analog still alive
nPowerdown/Powerup sequence of multiple codec configuration
There can be up to 4 Codecs on the extended AC-link. Multiple Codec AC-link implementations must run off a
common BIT_CLK. The Primary Codec generates the master AC-link BIT_CLK for both the AC ’97 Digital
Controller and any Secondary Codecs. The AK4543 may be used as a master or slave in any systems using more
than one codec.
Digital Controller
AC ‘97
SYNC
BIT_CLK
SDATA_OUT
RESET#
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SYNC
BIT_CLK
SDATA_OUT
RESET#
SDATA_IN
AC ‘97 or MC ‘97
SYNC
BIT_CLK
SDATA_OUT
RESET#
SDATA_IN
Optional 4th AC ‘97
SYNC
BIT_CLK
SDATA_OUT
RESET#
SDATA_IN
Multiple Codec Example
Under the multiple codec circumstances, there is no restriction on setting PR0(ADC), PR1(DAC),
PR2(Mixer), PR6(LNLVL_OUT) and PR7(EAPD) to “1” or “0”.
As suggested in the AC’97 Specification Rev2.1, the AC-Link Powerdown(PR”4”) and Vref
Powerdown(PR5=”1”) under the Multiple codec configuration are NOT recommended in order to continue
supplying BIT_CLK to the Secondary codecs.
<M0046-E-01>
- 24 1999/01
[ASAHI KASEI]
[AK4543]
The below table shows the relationship for the AC-Link Powerdown/Powerup procedure.
AC-Link Powerdown Procedure
RESET#=L
Subsequent Procedure for
Powerup
Cold Reset
Shutdown(Complete Powerdown)
Cold Reset
Comments
Cold Reset wakes up all of codecs with default register
setting concurrently.
Cold Reset wakes up all of codecs with default register
setting concurrently.
Note:
1) The AC-Link Powerdown of Primary AC’97 will stop supplying the BIT_CLK to the Secondary AC ’97.
2) When the AC-Link Powerdown is issued to the Secondary of AC ’97, the Secondary of AC’97 will go to the ACLink Powerdown and Warm Reset will be followed by Syn signal at the next time frame.
n Testability
Activating the Test Modes
AC ‘97 has two test modes. One is for ATE in circuit test and the other is for vendor specific tests. AC ‘97 enters the ATE
in circuit test mode regardless of SYNC signal (high or low) if SDATA_OUT is sampled high at the trailing edge of RESET#.
If AC ‘97 enters AKM test mode when coming out of RESET if SYNC is high with SDATA_OUT low. These cases will never
occur during standard operating conditions.
Regardless of the test mode, the AC ‘97 controller must issue a “Cold” reset to resume normal operation of the AC ‘97
Codec.
Test Mode Functions
ATE in circuit test mode
When AC ‘97 is placed in the ATE test mode, its digital AC-link outputs (i.e. BIT_CLK and SDATA_IN) are driven to a high
impedance state. This allows ATE in circuit testing of the AC ‘97 controller.
<M0046-E-01>
- 25 1999/01
[ASAHI KASEI]
[AK4543]
System Design
The following figure shows the system connection diagram.
Primary codec: codec ID1:codecID0=0:0
AVDD: 5V
DVDD: 3.3V or 5V
3.3V : 48pin open
5.0V : 48pin DGND
<M0046-E-01>
- 26 1999/01
[ASAHI KASEI]
[AK4543]
Secondary codec codec ID1:codecID0=0:1,1:0 or 1:1
This figure is the case of ID1 =0 and ID0=1.
AVDD: 5V
DVDD: 3.3V or 5V
3.3V : 48pin open
5.0V : 48pin DGND
<M0046-E-01>
- 27 1999/01
[ASAHI KASEI]
[AK4543]
1. Grounding and Power Supply Decoupling
AVdd1 and AVdd2 should be connected and derived from same AVdd. And DVdd1 and DVdd2 also should
be connected and derived from same D V d d. Analog ground and digital ground should be connected together
near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to
the AK4543 as possible, with the small value ceramic capacitor being the nearest.The most important capacitor
placements are on the Vref pin and AVdd pins.
No specific power supply sequencing is required on the AK4543.
2. On-chip Voltage Reference
The on-chip voltage reference is output on the VRADDA, Vref pins are used for decoupling. A electrolytic capacitor
less than 10uF in parallel with a 0.1 uF ceramic capacitor attached to these pins eliminates the effects of high
frequency noise. No load current may be drawn from VRADDA, or Vref pins. All signals, especially clocks, should
be kept away from the VRADDA, and Vref pins in order to avoid unwanted coupling into delta-sigma modulators.
3. Codec ID configuration Pin 45,46
ID1#(pin 46)
Physical
Logic
Connection
Value
NC
0
NC
0
GND
1
GND
1
ID0#(pin45)
Physical
Logic
Connection
Value
NC
0
GND
1
NC
0
GND
1
Configuration
Primary
Secondary ID01
Secondary ID10
Secondary ID11
4.Anlog input
Since many analog levels can be as high as 2Vrms, the circuit shown below can be used to attenuate the analog
input 2Vrms to 1Vrms which is the maximum voltage allowed for all the stereo line-level inputs.
J15
LINE_IN_L
J4
LINE_IN_R
5.SEL_CMOS#(48pin)
When DVDD is 3.3V for support of CMOS level, Pin 48 must be open.
Pin 48 must be DGND as the below figure in the case of DVDD is 5.0V for TTL level
This SEL_COMS# has to be fixed before powering up the AK4543.
6.PC_BEEP
If PC_BEEP isn’t used, this input pin should be NC(open) or connected to Analog-Ground via capacitor. In this
case, the register for PC- Beep(04h,D15) should be set to mute on ”1”. (Note that the default of PC_BEEP is mute
off.)
In addition, when PC_BEEP is connected through capacity to Analog-Ground, PC_BEEP is recommended to be
separated from other non-used input pins.
<M0046-E-01>
- 28 1999/01
[ASAHI KASEI]
[AK4543]
Package
48pin LQFP(Uni t :m
m)
9.0 + 0.2
1.7max
0.10 + 0.07
7.0
1.4TYP
25
36
37
9.0 + 0. 2
0. 5
7. 0
24
13
48
12
1
0.17 + 0.05
0.19 + 0.05
0.01M
0
10
0.5 + 0.2
0.10
<M0046-E-01>
- 29 1999/01
[ASAHI KASEI]
[AK4543]
Marking
AK4543VQ
XXXXXXX
JAPAN
1
1)
2)
3)
4)
5)
<M0046-E-01>
Pin #1 indication
Date Code : XXXXXXX (7 digits)
Marketing Code : AK4543VQ
Country of Origin
Asahi Kasei Logo
- 30 1999/01
[ASAHI KASEI]
[AK4543]
Appendix
1. Summary of the relationship of Slot 0 tag bit between SDATA_OUT and SDATA_IN
Whenever the AC ’97 Digital Controller addresses the Primary AK4543 or the AK4543 responds to a read
command, Slot 0 tag bits should always be set to indicate actual Slot 1 and Slot 2 data validity.
Function
AC ’97 Digital Controller Primary Read
Frame N, SDATA_OUT
AC ’97 Digital Controller Primary
Write
Frame N, SDATA_OUT
AK4543 Status
Frame N+1, SDATA_IN
Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(ValidSlot1Address)
Slot 0, bit 13
(ValidSlot2Data)
Slot 0, Bits 1-0
(Codec ID)
1
1
1
00
1
1
1
00
1
1
0
00
Primary AK4543 Addressing: Slot 0 tag bits
When the AC ’97 Digital Controller addresses a Secondary AK4543, the Slot 0 Tag bits for Address and Data must
be “0”. A non-zero 2-bit Codec ID in the LSBs of Slot 0 indicates a valid Read or Write Address in Slot 1,
and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.
Function
AC ’97 Digital Controller Secondary
Read
Frame N, SDATA_OUT
AC ’97 Digital Controller Secondary
Write
Frame N, SDATA_OUT
AK4543 Status
Frame N+1, SDATA_IN
Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(ValidSlot1Address)
Slot 0, bit 13
(ValidSlot2Data)
Slot 0, Bits 1-0
(Codec ID)
1
0
0
01, 10, or 11
1
1
1
00
1
0
0
01, 10, or 11
Secondary AK4543 Addressing: Slot 0 tag bits
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use
or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
(b)A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless
from any and all claims arising from the use of said product in the absence of such notification.
<M0046-E-01>
- 31 1999/01