SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 D D D D D description The SN54LVC138A 3-line to 8-line decoder/ demultiplexer is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCC operation. SN54LVC138A . . . J OR W PACKAGE SN74LVC138A . . . D, DB, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SN54LVC138A . . . FK PACKAGE (TOP VIEW) B A NC VCC Y0 D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flat (W) Package, and DIPs (J) C G2A NC G2B G1 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 NC Y3 Y4 Y7 GND NC Y6 Y5 D The ’LVC138A devices are designed for highNC – No internal connection performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC138A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVC138A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 FUNCTION TABLE ENABLE INPUTS G1 G2A X X SELECT INPUTS OUTPUTS G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X X H H H H H H H H X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic symbols (alternatives)† A B C G1 1 2 3 6 4 G2A G2B 5 BIN/OCT 0 1 2 1 4 2 3 & 4 EN 5 6 7 15 14 13 12 11 10 9 7 Y0 Y1 Y2 A B C 1 G1 Y5 G2A Y6 G2B 3 6 4 5 Y7 Pin numbers shown are for the D, DB, J, PW, and W packages. POST OFFICE BOX 655303 0 G 7 2 1 2 & 3 4 5 6 7 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 0 2 Y3 Y4 DMUX 0 • DALLAS, TEXAS 75265 15 14 13 12 11 10 9 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 logic diagram (positive logic) 15 A 1 14 Select Inputs B C 13 3 12 10 Enable Inputs 6 9 4 7 G2A G2B Y1 2 11 G1 Y0 Y2 Y3 Data Outputs Y4 Y5 Y6 Y7 5 Pin numbers shown are for the D, DB, J, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 recommended operating conditions (see Note 4) SN54LVC138A VCC VIH Supply voltage High-level input voltage Operating Data retention only VIL VI VO IOH Low-level input voltage MAX MIN MAX 2 3.6 1.65 3.6 1.5 1.5 UNIT V 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V SN74LVC138A MIN V 1.7 2 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0.7 0.8 V 0.8 Input voltage 0 5.5 0 5.5 V Output voltage 0 VCC 0 VCC –4 V High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate VCC = 1.65 V VCC = 2.3 V –8 VCC = 2.7 V VCC = 3 V –12 –12 –24 –24 VCC = 1.65 V VCC = 2.3 V mA 4 8 VCC = 2.7 V VCC = 3 V 12 12 24 0 10 mA 24 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = –4 mA IOH = –8 mA 1.2 V 1.7 2.7 V 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 VI = 5.5 V or GND VI = VCC or GND, 3.6 V ±5 ±5 µA 3.6 V 10 10 µA 500 500 µA IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND ∆ICC VCC–0.2 1.65 V to 3.6 V IOL = 100 µA UNIT VCC–0.2 2.3 V IOH = –24 mA II ICC MIN 1.65 V IOH = –12 12 mA VOL SN74LVC138A TYP† MAX MIN 1.65 V to 3.6 V IOH = –100 100 µA VOH SN54LVC138A TYP† MAX VCC 2.7 V to 3.6 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 3.3 V 5 5 V pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC138A FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 2.7 V MIN A or B or C tpd Y G2A or G2B G1 VCC = 3.3 V ± 0.3 V MAX MIN MAX 7.9 1 6.7 7.4 1 6.5 6.4 1 5.8 UNIT ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) SN74LVC138A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V TYP MIN MAX 15.9 1 15.4 1 14.4 1 A or B or C tpd G2A or G2B VCC = 2.5 V ± 0.2 V Y G1 tsk(o)‡ VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V MAX MIN MAX 9.9 7.9 1 6.7 9.4 7.4 1 6.5 8.4 6.4 1 5.8 1 UNIT ns ns ‡ Skew between any two outputs of the same package switching in the same direction POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance VCC = 1.8 V TYP f = 10 MHz VCC = 2.5 V TYP 25 VCC = 3.3 V TYP 26 27 UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291I – MARCH 1993 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V 0V tPZL 2.7 V 1.5 V 0V tPLH 1.5 V tPLZ Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V VOL + 0.3 V VOL tPHZ tPHL VOH Output 1.5 V 1.5 V tsu Input 1.5 V Input 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) tPZH 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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