(OLWH07 M11B11664A DRAM 64 K x 16 DRAM EDO PAGE MODE FEATURES y y y y y y y y y ORDERING INFORMATION - PACKAGE X16 organization EDO (Extended Data-Output) access mode 2 CAS Byte/Word Read/Write operation 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (TypeII) Single 5V ( ± 10%) power supply TTL-compatible inputs and outputs 256-cycle refresh in 4ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) PRODUCT NO. PACKING TYPE M11B11664A-25J and HIDDEN JEDEC standard pinout Key AC Parameter M11B11664A-30J SOJ M11B11664A-35J tRAC tCAC tRC tPC M11B11664A-40J -25 25 8 43 10 M11B11664A-25T -30 30 9 55 12 M11B11664A-30T -35 35 10 65 14 M11B11664A-35T -40 40 11 75 16 M11B11664A-40T TSOPII GENERAL DESCRIPTION The M11B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Extended Data-Output , 5V( ± 10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VC C I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VC C Elite Memory Technology Inc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TSOP (TypeII) Top View VS S VC C I/O1 5 I/O 0 I/O1 4 I/O 1 I/O1 3 I/O 2 I/O1 2 I/O 3 VS S VC C I/O1 1 I/O1 0 I/O9 I/O8 NC CA SL C ASH I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE OE RA S NC NC A7 A0 A6 A1 A5 A2 A4 A3 VS S VC C 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 V SS 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 NC I/O 15 I/O 14 I/O 13 I/O 12 V SS I/O 11 I/O 10 I/O 9 I/O 8 C AS L C AS H OE NC A7 A6 A5 A4 V SS Publication Date : Dec. 2000 Revision : 1.3 1/15 (OLWH07 M11B11664A FUNCTIONAL BLOCK DIAGRAM WE DATA-IN BUFFER RAS CONTROL LOGIC CASL 16 CASH CLOCK GENERATOR 8 DATA-OUT BUFFER COLUMN ADDRESS BUFFER 8 16 16 SENSE AMPLIFIERS I/O GATING 8 REFRESH CONTROLER A2 OE COLUMN DECODER 256 A0 A1 IO0 : IO15 A3 256 x 16 A4 REFRESH COUNTER A5 ROW DECODER A6 89 A7 8 ROW. ADDRESS BUFFERS(8) 8 256 256 x 256 x 16 MEMORY ARRAY VCC VBB GENERATOR VSS PIN DESCRIPTIONS PIN NO. PIN NAME TYPE 16~19,22~25 A0~A7 Input Address Input Row Address : A0~A7 Column Address : A0~A7 14 RAS Input Row Address Strobe 28 CASH Input Column Address Strobe / Upper Byte Control 29 CASL Input Column Address Strobe / Lower Byte Control 13 WE Input Write Enable 27 OE Input Output Enable 2~5,7~10,31~34,36~39 I/O0 ~ I/O15 Input / Output 1,6,20 VCC Supply Power, 5V 21,35,40 VSS Ground Ground 11,12,15,30 NC - Elite Memory Technology Inc DESCRIPTION Data Input / Output No Connect Publication Date : Dec. 2000 Revision : 1.3 2/15 (OLWH07 M11B11664A ABSOLUTE MAXIMUM RATINGS Voltage on Any pin Relative to Vss … ……-1V to +7V Operating Temperature, TA (ambient) ….0 °C to +70 °C Storage Temperature (plastic) ……….-55 °C to +150 °C Power Dissipation …………………………………1.0W Short Circuit Output Current ……………………50mA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 °C ≤ TA ≤ 70 °C ; VCC = 5V ± 10% unless otherwise noted) PARAMETER CONDITIONS SYMBOL MIN MAX UNITS NOTES Supply Voltage VCC 4.5 5.5 V Supply Voltage VSS 0 0 V Input High Voltage VIH 2.4 VCC +1 V 1 Input Low Voltage VIL -1.0 0.8 V 1 Input Leakage Current 0V ≤ VIH ≤ 7V ILI -10 10 µA Output Leakage Current 0V ≤ VOUT ≤ 7V Output(s) disable ILO -10 10 µA Output High Voltage IOH = -5 mA VOH 2.4 - V Output Low Voltage IOL = 4.2 mA VOL - 0.4 V 1 Note : 1.All Voltages referenced to VSS PARAMETER CONDITIONS SYMBOL Operating Current RAS , CAS cycling , tRC =min ICC1 Standby Current TTL interface , RAS , CAS = VIH , DOUT =High-Z ICC2 CMOS interface, RAS , CAS ≥ VCC-0.2V MAX UNITS NOTES -25 -30 -35 -40 170 150 130 120 mA 4 4 4 4 mA 2 2 2 2 mA 1,2 RAS only refresh Current tRC = min ICC3 170 150 130 120 mA 2 EDO Page Mode Current tPC = min ICC4 170 150 130 120 mA 1,3 Standby Current RAS =VIH, CAS = VIL ICC5 mA 1 CAS Before RAS Refresh Current tRC = min ICC6 5 5 5 5 170 150 130 120 mA Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 3/15 (OLWH07 M11B11664A CAPACITANCE (Ta = 25 °C , VCC = 5V ± 10%) PARAMETER SYMBOL TYP MAX UNIT Input Capacitance (address) CI1 - 5 pF Input Capacitance ( RAS , CASH , CASL , WE , OE ) CI2 - 7 pF CI / O - 10 pF Output capacitance (I/O0~I/O15) AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =5V ± 10%, VSS = 0V) (note 14) Test Conditions Input timing reference levels : 0V, 3V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time SYMBOL -25 MIN -30 MAX MIN -35 MAX MIN -40 MAX MIN MAX UNIT Notes tRC 43 55 65 75 ns tRWC 65 85 95 105 ns EDO-Page-Mode Read or Write Cycle Time tPC 10 12 14 16 ns 22 EDO-Page-Mode Read-Write Cycle Time tPCM 32 37 42 47 ns 22 Access Time From RAS tRAC 25 30 35 40 ns 4 Access Time From CAS tCAC 8 9 10 11 ns 5,20 Access Time From OE tOAC 8 9 10 11 ns 13,20 Access Time From Column Address tAA 12 15 18 20 ns Access Time From CAS Precharge tACP 14 17 20 22 ns RAS Pulse Width tRAS 25 10,000 ns RAS Pulse Width (EDO Page Mode) tRASC 25 100,000 30 100,000 35 100,000 40 100,000 ns RAS Hold Time tRSH 8 9 10 11 ns RAS Precharge Time tRP 15 20 25 30 ns CAS Pulse Width tCAS 4 CAS Hold Time tCSH 21 26 30 CAS Precharge Time tCP 4 4 5 RAS to CAS Delay Time tRCD 10 CAS to RAS Precharge Time tCRP 5 5 5 Row Address Setup Time tASR 0 0 Row Address Hold Time tRAH 5 5 RAS to Column Address Delay Time tRAD 8 Column Address Setup Time tASC 0 0 0 Column Address Hold Time tCAH 5 5 Column Address Hold Time (Reference to RAS ) tAR 22 Column Address to RAS Lead Time tRAL 12 Read Write Cycle Time Elite Memory Technology Inc 10,000 10,000 17 13 30 5 10 8 10,000 10,000 21 15 35 5 10,000 40 25 ns 24 35 ns 19 5 ns 6,23 ns 7,18 5 ns 19 0 0 ns 5 5 ns 10 8 10,000 25 17 6 20 10 8 10,000 29 20 ns 8 0 ns 18 5 5 ns 18 26 30 34 ns 15 18 20 ns Publication Date : Dec. 2000 Revision : 1.3 4/15 (OLWH07 M11B11664A (Continued) -25 PARAMETER SYMBOL -30 -35 -40 UNIT Notes MIN MAX MIN MAX MIN MAX MIN MAX Read Command Setup Time tRCS 0 0 0 0 ns 15,18 Read Command Hold Time Reference to CAS tRCH 0 0 0 0 ns 9,15,19 Read Command Hold Time Reference to RAS tRRH 0 0 0 0 ns 9 CAS to Output in Low-Z tCLZ 3 3 3 3 ns 20 Output Buffer Turn-off Delay From CAS or RAS tOFF1 3 15 ns 10,17,20 Output Buffer Turn-off to OE tOFF2 8 ns 17,26 Write Command Setup Time tWCS 0 0 0 0 ns 11,15,18 Write Command Hold Time tWCH 5 5 5 5 ns 15,25 Write Command Hold Time(Reference to RAS ) tWCR 22 26 30 34 ns 15 Write Command Pulse Width tWP 5 5 5 5 ns 15 Write Command to RAS Lead Time tRWL 7 8 9 10 ns 15 Write Command to CAS Lead Time tCWL 5 6 7 8 ns 15,19 Data-in Setup Time Data-in Hold Time tDS tDH 0 5 0 0 0 ns 12,20 5 5 5 ns 12,20 Data-in Hold Time (Reference to RAS ) tDHR 22 26 30 34 ns RAS to WE Delay Time tRWD 34 46 51 56 ns 11 Column Address to WE Delay Time tAWD 21 31 34 36 ns 11 CAS to WE Delay Time tCWD 17 25 26 27 ns 11,18 Transition Time (rise or fall) tT 1.5 50 ns 2,3 Refresh Period (256 cycles) tREF 4 ms RAS to CAS Precharge Time tRPC 10 10 10 10 ns CAS Setup Time(CBR REFRESH) tCSR 5 10 10 10 ns 1,18 CAS Hold Time(CBR REFRESH) tCHR 7 10 10 10 ns 1,19 OE Hold Time From WE During Read-ModeWrite Cycle tOEH 4 4 4 5 ns 16 OE Low to CAS High Setup Time tOES 4 4 4 5 ns OE High Hold Time From CAS High tOEHC 2 2 2 2 ns OE Precharge Time tOEP 2 2 2 2 ns OE Setup Prior to RAS During Hidden Refresh Cycle tORD 0 0 0 0 ns Last CAS Going Low to First CAS Returning High tCLCH 4 5 5 6 ns Data Output Hold After CAS Returning Low tCOH 3 3 3 3 ns Output Disable Delay From WE tWHZ 3 Read Setup Time Reference to RAS in CBR tRSR 5 5 5 5 ns Read Hold Time Reference to RAS in CBR tRHR 5 5 5 5 ns Elite Memory Technology Inc 15 3 6 50 3 8 1.5 4 7 15 50 7 3 8 2.5 4 3 15 50 2.5 4 3 7 3 7 21 ns Publication Date : Dec. 2000 Revision : 1.3 5/15 (OLWH07 M11B11664A Notes : 1. 2. 3. 4. 5. 6. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD ≥ tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFYWRITE operation is not possible. 14. An initial pause of 200 µ s is required after power-up RAS must be pulsed high. 7. 8. 9. 10. 11. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFYWRITE cycle only. If tWCS ≥ tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD ≥ tRWD(min) , tAWD ≥ tAWD(min) and tCWD ≥ tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go Elite Memory Technology Inc 15. 16. 17. 18. followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. WRITE command is defined as WE going low. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. The I/Os open during READ cycles once t OFF1 or tOFF2 occur. Referenced to the earlier CAS falling edge. 19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle’s last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Each CAS must meet minimum pulse width. 25. Referenced to the latter CAS failing edge. 26. All IOs controlled by OE , regardless CASL and CASH . Publication Date : Dec. 2000 Revision : 1.3 6/15 (OLWH07 M11B11664A TRUTH TABLE FUNCTION ADDRESSES RAS CASL CASH WE OE ROW COL DQS NOTES Standby H HÆX HÆX X X X X Read : Word L L L H L ROW COL Data-Out Read : Lower Byte L L H H L ROW COL Lower Byte, Data-Out Read : Upper Byte L H L H L ROW COL Upper Byte, Data-Out Write : Word (Early Write) L L L L X ROW COL Data-In Write : Lower Byte (Early) L L H L X ROW COL Lower Byte, Data-In , Upper Byte, High-Z Write : Upper Byte (Early) L H L L X ROW COL Lower Byte, High-Z , Upper Byte, Data-In Read-Write L L L ROW COL Data-Out, Data-In 1st Cycle EDO-Page-Mode 2nd Cycle Read Any Cycle L HÆL HÆL H L ROW COL Data-Out 2 L HÆL HÆL H L COL Data-Out 2 L LÆH LÆH H L Data-Out 2 EDO-Page-Mode 1st Cycle Write 2nd Cycle L HÆL HÆL L X COL Data-In 1 L HÆL HÆL L X COL Data-In 1 EDO-Page-Mode 1st Cycle Read-Write 2nd Cycle L HÆL HÆL HÆL LÆH COL Data-Out, Data-In 1, 2 L HÆL HÆL HÆL LÆH COL Data-Out, Data-In 1, 2 LÆHÆL L L H L ROW COL Data-Out L H H X X ROW HÆL L L H X X Hidden Refresh RAS -Only Refresh CBR Refresh HÆL LÆH ROW ROW High-Z 1, 2 2 High-Z X High-Z 3 *Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active). 2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active). 3. Only one CAS must be active ( CASL or CASH ). Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 7/15 (OLWH07 M11B11664A READ CYCLE tRC tR AS RA S tCRP CA SL ,C AS H tRP VIH VIL tCSH tRS H tCAS, tCLCH tRCD tRRH VIH VIL tAR tRAL tCAH t R AD tASR AD DR VIH VIL tRAH tAS C ROW R OW C OLUMN t RC H tRCS WE VIH VIL tAA tRAC NO TE1 tOFF 1 t C AC tCLZ I/ O VO H VO L VAL ID DA TA OPE N tO AC OE OP EN tO FF 2 VIH VIL EARLY WRITE CYCLE tR C tRAS RAS tRP V IH V IL tC SH tRS H tCRP CA SL ,C AS H t RC D tC AS , t C L C H VIH VIL tAR t R AD t R AH t ASR ADDR VIH VIL tRAL tCAH tASC COLUMN ROW tWCS ROW tCWL tRWL tWCR tWCH tWP WE VIH VIL tDS I/O OE V IH V IL tDHR tDH VA LI D DAT A V IH V IL DON'T CARE UNDEFINED Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 8/15 (OLWH07 M11B11664A READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRWC t R AS RAS tCRP CASL ,C AS H tCSH tRS H t C AS , t C L C H tRC D VIH VIL tAR tRAD tRAH tASR AD DR t RP VIH VIL V IH V IL t R AL t C AH tASC ROW COLUMN tRCS WE ROW t RWD tCWD tAWD tCWL tRWL tWP V IH V IL tAA tRAC t C AC I/ O VAL I D DOUT OPE N t O AC OE tDH tDS tCLZ VI/OH VI/OL VA LID DIN tOEH tOFF 2 VIH VIL EDO-PAGE-MODE READ CYCLE t R AS C RA S tP C (NOTE2) tCSH t RC D tCRP CA SL ,C ASH tRP VIH VIL tCAS,tCLCH tCP t C AS , t C L CH tRS H tCAS,tCLCH tCP tCP V IH V IL tAR t R AD t R AL t AS C t AS R t R A H AD DR VIH VIL ROW tCAH COLUMN t AS C t AS C tCAH tCAH COLUMN COLUMN ROW tRC H tRCS WE VIH VIL tAA tACP t C AC tAA tRAC t C AC VOH VOL O PE N VALID DATA tO AC tO ES OE tAA tACP tCAC N O TE 1 tCLZ tCOH tCLZ I/ O tRRH V AL I D D ATA tOF F1 VAL ID DATA tOEHC tO AC OPE N tOFF2 t OF F2 tO ES VIH VIL t O EP DON'T CARE UNDEFINED *NOTE : 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 9/15 (OLWH07 M11B11664A EDO-PAGE-MODE EARLY-WRITE CYCLE t R AS C RAS tRP VIH VIL tCSH tCRP CA SL,C ASH tPC (NOTE1) tCAS,t CLCH tCP tC A S , t C L CH tRC D tRS H t C AS , t C L C H tCP tCP VIH VIL tAR t R AL tCAH t R AD tASR AD DR VIH VIL tRAH tCAH t AS C t A S C t C AH COLUMN ROW WE COL U MN COLUMN tCWL tWCS t AS C tCWL tWCH tWP tWCS tWCH tWP ROW tCWL tWCH tWP tWCS VIH VIL t WCR tDH R tDH tDS I/ O VIH VIL OE VIH VIL tRWL tDS V AL I D D AT A tDH tDH tDS VALI D DATA V AL I D D AT A EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRASC RAS tRP VIH VIL t CS H tCRP CASL ,CAS H t CA S , t C LC H t RC D tPCM tCAS,t CLCH tCP tRSH t CP VIH VIL tAR t RA D tASR ADDR tCP tCAS, t CLCH VIH VIL tRAH ROW t CA H tASC t AS C C OL UM N tASC t C AH tRAL tCAH COLUM N C OL UM N ROW tRWD tRCS tRWL tCWL tCWL tWP tWP t A WD tCWD WE tAA tAA t DH tACP tDS t C AC t CL Z VI /O H VI /O L tAA tDH tDH t AC P tDS tCLZ VALI D VAL ID DOUT DIN VA L I D DOUT tOF F2 tOF F2 t O AC tDS t C AC t C AC tCLZ V A L I D VA L I D DOUT DI N tO AC OE t A WD tCWD tAWD t CWD VIH VIL t R AC I/ O tCWL tWP tO AC VA L I D DIN tOFF 2 tOEH VIH VIL DON'T CARE UNDEFINED Note : 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 10/15 (OLWH07 M11B11664A EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE) tRAS C RA S tRP VIH VIL tCSH CAS tCP tPC tCAS t RC D tCRP tCP tRSH tCAS tCP tCAS tCP VIH VIL tAR tRAL tRAD t ASC tASR tRAH AD DR VIH VIL tCAH tASC CO LU M N(A ) R OW tCAH COLU MN(B) ROW tWCH t WCS VIH VIL tAA tA A t R AC VI/OH VI/OL tW HZ tACP tCAC I/O tCAH COLUMN( N) tRCH tRCS WE tAS C VA L ID DAT A( A ) OPE N tDS tCAC tCO H VA L I D DATA(B ) tDH VALI D DATA IN tO AC OE VIH VIL RAS ONLY REFRESH CYCLE (ADDR = A0~A7 ; OE , WE = DON’T CARE) tRC tRP tRAS RA S VIH VIL CA SL ,C A SH VIH VIL tC RP tRP C tAS R AD DR VIH VIL I/O VOH VOL t RAH R OW ROW OPE N DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 11/15 (OLWH07 M11B11664A CBR REFRESH CYCLE (A0~A7 ; OE = DON’T CARE) tRP RAS I/O tCS R t R AS tR PC tCHR tCSR tCHR VIH VIL VOH VOL OPE N t R S R t RH R t RC H WE tRP VIH VIL tR PC tCP CA SL , C AS H tRAS V IH V IL tR SR tRHR ( NOT E1 ) HIDDEN REFRESH CYCLE WE = HIGH ; OE = LOW ( RE AD ) ( R EF RE S H ) t RAS RAS VIH VIL CA SL ,CAS H VIH VIL tC RP tRSH t RC D t RAS tCHR tAR tRAD tASR ADDR tRP VIH VIL tRAH t ASC ROW tRAL tCAH CO LU MN tAA NOTE2 t RAC tO FF 1 t CAC tCLZ I/O VO H VO L OP EN VAL ID DAT A tO AC tORD OE OPE N tO FF 2 VIH VIL DON'T CARE UNDE FINED Note : 1. tRSR and tRHR are for system design reference only. The WE signal is actually a “don’t care” at RAS time during a CBR REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CBR REFRESH. 2. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 12/15 (OLWH07 PACKING DIMENSIONS 40-LEAD SOJ(400mil) M11B11664A SECTIONI ' E 0$; ( ( E '(7$,/ $ θ $ $ H '(7$,/ $ F $ 5 0,1 θ ; ( SECTIONII Symbol A A1 A2 b b2 c Dimension in mm Min Norm Max 3.250 3.510 3.760 2.080 2.790 REF 0.380 0.460 0.560 0.635 REF 0.180 0.250 0.360 Dimension in inch Symbol Dimension in mm Min Norm Max Min Norm Max 0.128 0.138 0.148 E 10.920 11.176 11.430 0.082 E1 10.030 10.160 10.290 0.110 REF E2 9.40 BSC 0.015 0.018 0.022 R1 0.760 0.890 1.020 0.025 REF b2 0.635 REF 0.007 0.010 0.014 θ1 ° ° e D 1.270 BSC 25.91 26.040 26.290 1.02 Elite Memory Technology Inc 0.050 BSC 1.025 1.035 e y1 1.270 BSC 0.381 Dimension in inch Min Norm Max 0.430 0.440 0.450 0.395 0.400 0.405 0.370 BSC 0.030 0.035 0.040 0.025 REF ° ° 0.050 BSC 0.015 Publication Date : Dec. 2000 Revision : 1.3 13/15 (OLWH07 M11B11664A PACKING DIMENSIONS 40 / 44-LEAD TSOP(II) Symbol DRAM(400mil) Dimension in mm Min Norm A Max Dimension in inch Min Norm 1.20 A1 0.05 A2 0.95 b 0.30 1.00 0.047 0.15 0.002 1.05 0.037 0.45 0.012 0.006 0.039 0.042 0.018 b1 0.30 0.40 0.012 c 0.12 0.21 0.005 0.008 c1 0.10 0.16 0.004 0.006 D 18.28 18.54 0.720 ZD 0.35 Max 18.41 0.805 REF 0.014 0.725 0.016 0.730 0.0317 REF E 11.56 11.76 11.96 0.455 0.463 0.471 E1 10.03 10.16 10.29 0.395 0.400 0.4 L 0.40 0.59 0.69 0.016 0.023 0.027 L1 0.80 REF 0.031 REF e 0.80 BSC 0.0315 BSC θ O° ~ 7° REF O° ~ 7° REF Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 14/15 (OLWH07 M11B11664A ,PSRUWDQW 1RWLFH $OO ULJKWV UHVHUYHG 1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG RU GXSOLFDWHG LQ DQ\ IRU P RU E\ DQ\ PHDQV ZLWKRXW WKH SULRU SHUPLVVLRQ RI (OLWH07 7KH FRQWHQWV SXEOLFDWLRQ UHVHUYHV FRQWDLQHG (OLWH07 WKH ULJKW WR LQ WKLV DVVX PHV FKDQJH GRFXPHQW QR WKH DUH EHOLHYHG UHVSRQVLELO LW\ SURGXFWV RU IRU WR DQ\ EH DFFXUDWH HUURU VSHFLILFDWLRQ LQ LQ WKLV WKLV DW WKH WL PH GRFXPHQW GRFXPHQW RI DQG ZLWKRXW QRWLFH 7KH LQIRUPDWLRQ DSSOLFDWLRQ RI LQIULQJHPHQW SDUWLHV RWKHUZLVH LV RXU RI ZKLFK FRQWDLQHG KHUHLQ SURGXFWV SDWHQWV PD\ 1R SUHVHQWHG IURP XQGHU LWV DQ\ RQO\ UHVSRQVLELOLW\ FRS\ULJKWV UHVXOW JUDQWHG LV RU RWKHU XVH 1R SDWHQWV DV LV D JXLGH DVVXPHG LQWHOOHFWXDO OLFHQVH FRS\ULJKWV E\ H[D PSOHV (OLWH07 SURSHUW\ HLWKHU RU RU ULJKWV H[SUHVV RWKHU IRU IRU RI WKH DQ\ WKLUG LPSOLHG LQWHOOHFWXDO RU SURSHUW\ ULJKWV RI (OLWH07 RU RWKHUV $Q\ VHPLFRQGXFWRU GHYLFHV PD\ KDYH LQKHUHQWO\ D FHUWDLQ UDWH RI IDLOXUH 7R P LQL P L]H ULVNV DVVRFLDWHG ZLWK FXVWR PHU V DSSOLFDWLRQ DGHTXDWH GHVLJQ DQG RSHUDWLQJ VDIHJXDUGV DJDLQVW LQMXU\ GDPDJH RU ORVV IUR P VXFK IDLOXUH VKRXOG EH SURYLGHG E\ WKH FXVWRPHU ZKHQ PDNLQJ DSSOLFDWLRQ GHVLJ QV (OLWH07 V SURGXFWV DUH OL PLWHG GLUHFWO\ WR OLIH DIIHFW VXSSRUW KX PDQ QRW DXWKRUL]HG GHYLFHV OLYHV RU RU IRU XVH LQ FULWLFDO DSSOLFDWLRQV VXFK DV EXW V\VWHP FDXVH ZKHUH SK\VLFDO IDLOXUH LQMXU\ RU RU DEQRUPDO SURSHUW\ RSHUDWLRQ GDPDJH ,I QRW PD\ SURGXFWV GHVFULEHG KHUH DUH WR EH XVHG IRU VXFK NLQGV RI DSSOLFDWLRQ SXUFKDVHU PXVW GR LWV RZQ TXDOLW\ DVVXUDQFH WHVWLQJ DSSURSULDWH WR VXFK DSSOLFDWLRQV Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 15/15