ETC MAS9181BN

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13 October, 1999
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The MAS9181 comprises eight digital to analog
2
converters (DACs) each controlled by a two-wire I C
bus. The DACs are individually programmed using an 8bit word to select an output from one of 256 voltage
steps. The maximum output voltage of all DACs is set
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· Rail to rail output stages
· Octal 8-bit DACs on a single monolithic chip
· Power supply range from +5 V to +12 V
· -20°C to +85°C temperature range
· 16-pin PDIL and SO package
· Power-up reset
by Vmax and the resolution is Vmax/256. At power-on all
2
outputs are set to their lowest value. The I C-bus slave
receiver has 3 programmable address pins (2 for
MAS9181 CS).
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· Trimmer replacement
· AGC/AFT or TVs and VCRs
· Graphic equalizers
· High resolution monitors
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SDA
SCL
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I C Bus
Slave
Receiver
A0
A1
A2
8-BIT DAC
DAC7
8-BIT DAC
DAC6
DAC5
8-BIT DAC
8-BIT DAC
DAC3
8-BIT DAC
8-BIT DAC
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Reference
Voltage
Generator
DAC4
8-BIT DAC
DAC2
DAC1
8-BIT DAC
DAC0
VDD GND
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PDIP 16
DA9181.006
13 October, 1999
SO16
MAS9181BN
VDD 1
16 DAC7
Vmax 2
15 DAC6
SDA 3
14 DAC5
SCL 4
13 DAC4
A0 5
12 DAC3
A1 6
11 DAC2
A2 7
10 DAC1
GND 8
9 DAC0
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MAS9181CS
VDD
Vmax
SDA
SCL
NC
A0
A1
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
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DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
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VDD
1
1
P
Positive supply voltage
Vmax
2
2
I
Control input for DAC maximum output voltage
SDA
3
3
I/O
SCL
4
4
I
I C bus serial data clock
A0
5
6
I
Programmable address bits for I C bus slave receiver
A1
6
7
I
Programmable address bits for I C bus slave receiver
A2
7
NC
I
Programmable address bits for I C bus slave receiver
GND
8
8
G
Ground
DAC0
9
9
O
Analog voltage output
DAC1
10
10
O
Analog voltage output
DAC2
11
11
O
Analog voltage output
DAC3
12
12
O
Analog voltage output
DAC4
13
13
O
Analog voltage output
DAC5
14
14
O
Analog voltage output
DAC6
15
15
O
Analog voltage output
DAC7
16
16
O
Analog voltage output
2
I C bus serial data input/output
2
2
2
2
*1 MAS9181BN (PDIP16)
*2 MAS9181CS (SO16)
2
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13 October, 1999
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(conditions)
Supply Voltage
VDD
-0.5
18
Supply current
IDD
-10
40
V(3),V(4)
-0.5
5.9
Input voltage
Vin
-0.5
VDD+0.5
Output voltage
Vo
-0.5
VDD+0.5
2
I C-bus line voltage
V
V
Ç
V
Maximum current on any
pin
Imax
10
mA
total power dissipation
Ptot
500
mW
Operating ambient
temperature range
Storage temperature range
Tamb
-20
+85
o
Tstg
-65
+150
o
C
C
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Supply Voltage
VDD
Supply current
IDD
Total power dissipation
Ptot
C
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12
13.2
V
No loads, Vmax=VDD=12V, All
data=00OCT
3.0
5.0
mA
No loads, Vmax=VDD=12V, All
data=00OCT
40
60
mW
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(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
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Input voltage range
VI
Input low voltage
VIL
Input high voltage
VIH
Input leakage current
IIL
Power-up reset
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-0.5
5.5
V
1.0
V
3.0
Vin = 0V or VDD
V
-1
+1
A
3.5
V
3
DA9181.006
13 October, 1999
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(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
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Input voltage range
VI
Input low voltage
VIL
Input high voltage
VIH
Input current low
IIL
Input current high
IIH
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0
VDD
V
1.0
V
3.0
V
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-15
A
1
A
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
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Pin 2 current
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I2
7
10
A
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(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
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ÊË Ì ËÉ
DAC output (pin 9 to 16)
Output voltage range
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ÔÕ Ì Õ ÐÓ Ö
Vo
Io = +/- 100 A
0.1
VDD-0.1
V
Io = +/- 500 A
0.2
VDD-0.2
V
1
mA
2
nF
Output impedance
Zo
data = 7F
DAC output drive range
Io
Upper side saturation voltage= 0.2v
Low side saturation voltage = 0.2v
Output capacitive load
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30
-1
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ç
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
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Output voltage low
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÷
VOL
I3 = 3.0 mA
øö ôúùïûüø"é ýÿþôö í
0.4
V
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
Differential nonlinearity
DNL
Io = 0 (without load)
Vmax = VDD-1.0
-1
1
LSB
Integral nonlinearity
INL
Io = 0 (without load)
Vmax = VDD-1.0
-1.5
1.5
LSB
ZCE
data = 00
30
mV
5
mV/V
200
V/ C
Zero code error
1
1
Power supply rejection
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PSRR
1
Zero code temperature coefficient
TCo
-200
o
Note 1: Guaranteed by design but not production tested
4
DA9181.006
13 October, 1999
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2
2
The MAS9181 I C-bus interface is a receiver- only slave. Data is accepted from the I C - bus in the following
format.
S
0 1 0 0 A2 A1 A0 0
A
I3 I2 I1 I0 SD SC SB
SA
Address byte
A
D7 D6 D5 D4 D3 D2 D1
D0
Instruction byte
A
First data byte
S
Start condition
A2, A1, A0
programmable address bits
P
Stop condition
I3, I2, I1, I0
instruction bits
A
Acknowledgement
SD, SC, SB, SA
sub-address bits
D7, D6, D5, D4, D3, D2, D2, D1, D0
data bits
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J
Bit Transfer on the I C-bus
SDA
SCL
Data line
stable
(data valid)
Change
of data
allowed
Complete Data Transfer
SDA
1-7
SCL
8
9
1-7
8
9
8
1-7
9
P
S
Start
condition
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
condition
5
P
DA9181.006
13 October, 1999
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Valid addresses are 40, 42, 44, 46, 48, 4A, 4C, 4E(hex),
depending on the programming of bits A2, A1 and A0.
With these addresses, up to eight MAS9181 ICs can be
2
operated independently from one I C-bus. No other
addresses are acknowledged by the MAS9181. The
address inputs A0, A1 and A2 are programmed by
connection to GND for An = 0 or to VDD for An = 1. If
the inputs are left floating, An = 1 will result. For
MAS9181CS, A2 is always 1.
Valid instructions from 00 to 0F and F0 to FF (hex);
MAS9181 will not respond to other instruction value, but
will still generate an acknowledgement. Instructions 00
to0F cause auto-incrementing of the sub-address (bits
SD to SA) when more than one data byte is sent within
one transmission. With auto-incrementing, the first data
byte is written into the DAC addessed by bits SD to SA
and then the sub-address is automatically incremented
by one position for the next databyte in the series. Auto-
incrementing does not occur with instructions F0 to FF.
The DAC addressed by the sub-address will always
receive the data if more than one data byte is sent.
Valid sub-addresses (bits SD to SA) are 0 to 7 (hex)
relating numerically to DAC0 to DAC7. When the autoincrementing function is used, the sub-address will
sequence through all possible values (0 to F, 0 to F,
etc.). While the sub-address is between 8 and F no
DAC outputs change.
Input SCL (pin 4) and input/output SDA (pin 3) conform
2
to I C-bus specifications. Pins 3 and 4 are protected
against voltage pulses by internal zener diodes
connected to the ground plane and therefore the normal
bus line voltage shall not exceed 5.5V.
Input Vmax (pin 2) provides a means of comprising the
output voltage swing of the DACs. The maximum DAC
output voltage is restricted to approximately Vmax while
the 8-bit resolution is maintained, therefore giving a
finer voltage resolution of smaller output swings.
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DA9181.006
13 October, 1999
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+12v
VDD
DAC7
DAC6
100nF
GND
+5v
DAC5
Micro
Controller
5k
6
5k
Clock
5
4
3
15
14
DAC4
13
DAC3
12
DAC2
7
16
A2
DAC1
A1
DAC0
11
10
9
A0
SCL
+12v
SDA
100nF
Data
MAS9181
7
DA9181.006
13 October, 1999
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16 LEAD PDIP OUTLINE (300 MIL BODY)
6.10
7.11
7.62
BSC
0.254
0.36
0.56
1.15
1.77
5.33
MAX
5.5
5-7°
2.93
4.95
1.52
18.93
21.33
SEATING
PLANE
2.54
BSC
0.63 TYPICAL
1 PIN
16 LEAD SO OUTLINE (300 MIL BODY)
1.27
5° TYP. TYP.
5°TYP
2.36
2.64
0.25 RAD.
MIN.
5° TYP.
.
0.8 6 T Y P
SEATING
PLANE
7.39
7.59
10.11
10.49
10.01
10.64
5° TYP.
0-0.13
RAD.
0.10
0.30
5° TYP.
0.36
0.48
0.94
1.12
0.33 x 45°
PIN 1
ALL MEASUREMENTS IN mm
8
DA9181.006
13 October, 1999
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MAS9181BN
OCTAL 8-BIT TRIMMER-IC
16 Pin PDIP 0.3"
MAS9181CS
OCTAL 8-BIT TRIMMER-IC
16 Pin SO 0.3"
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2 Address Pins
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Micro Analog Systems Oy
Kamreerintie 2, P.O.Box 51
FIN-02771 ESPOO, FINLAND
http://www.mas-oy.com
Tel. (09) 80 521
Tel. Int. +358 9 80 521
Telefax +358 9 805 3213
E-mail: [email protected]
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this
data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are
free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes
no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
9