DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com DUAL H-BRIDGE MOTOR DRIVER Check for Samples: DRV8833 FEATURES 1 • 2 • • • Dual-H-Bridge Current-Control Motor Driver – Capable of Driving Two DC Motors or One Stepper Motor – Low MOSFET On-Resistance: HS + LS 360 mΩ Output Current 1.5-A RMS, 2-A Peak per H-Bridge (at VM = 5 V, 25°C) Outputs Can Be Paralleled for 3-A RMS, 4-A Peak Wide Power Supply Voltage Range: 2.7 V – 10.8 V • • PWM Winding Current Regulation/Limiting Thermally Enhanced Surface Mount Package APPLICATIONS • • • • • • Battery-Powered Toys POS Printers Video Security Cameras Office Automation Machines Gaming Machines Robotics DESCRIPTION The DRV8833 provides a dual bridge motor driver solution for toys, printers, and other mechatronic applications. The device has two H-bridge drivers, and can drive two DC brush motors, a bipolar stepper motor, solenoids, or other inductive loads. The output driver block of each H-bridge consists of N-channel power MOSFET’s configured as an H-bridge to drive the motor windings. Each H-bridge includes circuitry to regulate or limit the winding current. With proper PCB design, each H-bridge of the DRV8833 is capable of driving up to 1.5-A RMS (or DC) continuously, at 25°C with a VM supply of 5 V. It can support peak currents of up to 2 A per bridge. Current capability is reduced slightly at lower VM voltages. Internal shutdown functions with a fault output pin are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. A low-power sleep mode is also provided. The DRV8833 is packaged in a 16-pin HTSSOP or QFN package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). ORDERING INFORMATION (1) ORDERABLE PART NUMBER PACKAGE (2) PowerPAD™ (HTSSOP) - PWP PowerPAD™ (QFN) - RTY (1) (2) Reel of 2000 DRV8833PWPR Tube of 90 DRV8833PWP Reel of 3000 DRV8833RTYR Reel of 250 DRV8833RTYT TOP-SIDE MARKING DRV8833 DRV8833 For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com DEVICE INFORMATION Functional Block Diagram 2.2uF VINT VM VM VM 10uF Internal Ref & Regs Charge Pump VCP 0.01uF VM Drives 2x DC motor or 1x Stepper AOUT1 Gate Drive & OCP AIN1 AIN2 DCM VM Step Motor AOUT2 BIN1 BIN2 AISEN ISEN Logic VM nSLEEP BOUT1 nFAULT Gate Drive & OCP OverTemp DCM VM BOUT2 BISEN ISEN GND 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com Table 1. TERMINAL FUNCTIONS PIN (RTY) I/O (1) 13 PPAD 11 PPAD - Device ground Both the GND pin and device PowerPAD must be connected to ground VM 12 10 - Device power supply Connect to motor supply. A 10-µF (minimum) ceramic bypass capacitor to GND is recommended. VINT 14 12 - Internal supply bypass Bypass to GND with 2.2-μF, 6.3-V capacitor VCP 11 9 IO High-side gate drive voltage Connect a 0.01-μF, 16-V (minimum) X7R ceramic capacitor to VM AIN1 16 14 I Bridge A input 1 Logic input controls state of AOUT1. Internal pulldown. AIN2 15 13 I Bridge A input 2 Logic input controls state of AOUT2. Internal pulldown. BIN1 9 7 I Bridge B input 1 Logic input controls state of BOUT1. Internal pulldown. BIN2 10 8 I Bridge B input 2 Logic input controls state of BOUT2. Internal pulldown. nSLEEP 1 15 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. Internal pulldown. 8 6 OD Fault output Logic low when in fault condition (overtemp, overcurrent) AISEN 3 1 IO Bridge A ground / Isense Connect to current sense resistor for bridge A, or GND if current control not needed BISEN 6 4 IO Bridge B ground / Isense Connect to current sense resistor for bridge B, or GND if current control not needed AOUT1 2 16 O Bridge A output 1 AOUT2 4 2 O Bridge A output 2 BOUT1 7 5 O Bridge B output 1 BOUT2 5 3 O Bridge B output 2 NAME PIN (PWP) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND CONTROL STATUS nFAULT OUTPUT (1) Connect to motor winding A Connect to motor winding B Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 3 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com PWP PACKAGE (TOP VIEW) nSLEEP AOUT1 AISEN AOUT2 BOUT2 BISEN BOUT1 nFAULT 1 16 2 15 3 14 4 13 GND (PPAD) 5 12 6 11 7 10 8 9 AIN1 AIN2 VINT GND VM VCP BIN2 BIN1 13 14 12 1 GND (PPAD) 2 3 11 10 9 8 7 VINT GND VM VCP BOUT1 nFAULT BIN1 BIN2 6 4 5 AISEN AOUT2 BOUT2 BISEN 15 16 AOUT1 nSLEEP AIN1 AIN2 RTY PACKAGE (TOP VIEW) 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) VM Power supply voltage range Digital input pin voltage range xISEN pin voltage Peak motor drive output current VALUE UNIT –0.3 to 11.8 V –0.5 to 7 V –0.3 to 0.5 V Internally limited A TJ Operating junction temperature range –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION THERMAL METRIC PWP RTY 16 PINS 16 PINS θJA Junction-to-ambient thermal resistance (1) 40.5 37.2 θJCtop Junction-to-case (top) thermal resistance (2) 32.9 34.3 (3) θJB Junction-to-board thermal resistance 28.8 15.3 ψJT Junction-to-top characterization parameter (4) 0.6 0.3 ψJB Junction-to-board characterization parameter (5) 11.5 15.4 θJCbot Junction-to-case (bottom) thermal resistance (6) 4.8 3.5 (1) (2) (3) (4) (5) (6) UNITS °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS TA = 25°C (unless otherwise noted) MIN VM Motor power supply voltage range (1) VDIGIN Digital input pin voltage range IOUT Continuous RMS or DC output current per bridge (2) (1) (2) MAX UNIT 2.7 NOM 10.8 V -0.3 5.75 V 1.5 A Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V. VM = 5 V, power dissipation and thermal limits must be observed. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 5 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY IVM VM operating supply current VM = 5 V, xIN1 = 0 V, xIN2 = 0 V 1.7 3 mA IVMQ VM sleep mode supply current VM = 5 V 1.6 2.5 μA VUVLO VM undervoltage lockout voltage VM falling 2.6 V VHYS VM undervoltage lockout hysteresis 90 mV LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage VHYS Input hysteresis RPD Input pull-down resistance IIL Input low current IIH Input high current tDEG Input deglitch time nSLEEP 0.5 All other pins 0.7 nSLEEP All other pins 2.5 V 2 0.4 nSLEEP 500 All except nSLEEP 150 VIN = 0 V kΩ 1 VIN = 3.3 V, nSLEEP VIN = 3.3 V, all except nSLEEP V 6.6 13 16.5 33 450 μA μA ns nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 μA H-BRIDGE FETS VM = 5 V, I O = 500 mA, TJ = 25°C HS FET on resistance 200 VM = 5 V, IO = 500 mA, TJ = 85°C 325 VM = 2.7 V, I O = 500 mA, TJ = 25°C 250 VM = 2.7 V, IO = 500 mA, TJ = 85°C RDS(ON) 350 VM = 5 V, I O = 500 mA, TJ = 25°C LS FET on resistance 160 VM = 5 V, IO = 500 mA, TJ = 85°C 275 VM = 2.7 V, I O = 500 mA, TJ = 25°C 200 VM = 2.7 V, IO = 500 mA, TJ = 85°C IOFF Off-state leakage current VM = 5 V, TJ = 25°C, VOUT = 0 V mΩ 300 –1 1 μA MOTOR DRIVER fPWM Current control PWM frequency Internal PWM frequency 50 kHz tR Rise time VM = 5 V, 16 Ω to GND, 10% to 90% VM 180 ns tF Fall time VM = 5 V, 16 Ω to GND, 10% to 90% VM 160 ns tPROP Propagation delay INx to OUTx VM = 5 V 1.1 µs tDEAD Dead time (1) VM = 5 V 450 ns PROTECTION CIRCUITS IOCP Overcurrent protection trip level 3.3 A tDEG OCP Deglitch time 2.25 µs tOCP Overcurrent protection period 1.35 ms tTSD Thermal shutdown temperature (1) 6 2 Die temperature 150 160 180 °C Internal dead time. External implementation is not necessary. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 240 mV CURRENT CONTROL VTRIP xISEN trip voltage tBLANK Current sense blanking time 160 µs 3.75 SLEEP MODE tWAKE Startup time nSLEEP inactive high to H-bridge on 1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 ms 7 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION PWM Motor Drivers DRV8833 contains two identical H-bridge motor drivers with current-control PWM circuitry. A block diagram of the circuitry is shown below: VM OCP VM VCP, VINT xOUT1 xIN1 Predrive DCM xOUT 2 xIN2 PWM OCP xISEN + Optional REF (200mV) Figure 1. Motor Control Circuitry Bridge Control and Decay Modes The AIN1 and AIN2 input pins control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1 and BIN2 input pins control the state of the BOUT1 and BOUT2 outputs. Table 2 shows the logic. Table 2. H-Bridge Logic xIN1 xIN2 xOUT1 xOUT2 FUNCTION 0 0 Z Z Coast/fast decay 0 1 L H Reverse 1 0 H L Forward 1 1 L L Brake/slow decay The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted. To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow decay, one xIN pin is held high. Table 3. PWM Control of Motor Speed 8 xIN1 xIN2 FUNCTION PWM 0 Forward PWM, fast decay 1 PWM Forward PWM, slow decay 0 PWM Reverse PWM, fast decay PWM 1 Reverse PWM, slow decay Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com Figure 2 shows the current paths in different drive and decay modes. VM VM 1 Forward drive 1 xOUT2 xOUT1 1 Reverse drive 1 2 Fast decay 3 Slow decay 2 Fast decay xOUT1 xOUT2 2 2 3 3 FORWARD 3 Slow decay REVERSE Figure 2. Decay Modes Current Control The current through the motor windings may be limited, or controlled, by a fixed-frequency PWM current regulation, or current chopping. For DC motors, current control is used to limit the start-up and stall current of the motor. For stepper motors, current control is often used at all times. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Note that immediately after the current is enabled, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins with a reference voltage. The reference voltage is fixed at 200 mV. The chopping current is calculated in Equation 1. mV ¾ ICHOP = 200 RISENSE (1) Example: If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA. Once the chopping current threshold is reached, the H-bridge switches to slow decay mode. Winding current is re-circulated by enabling both of the low-side FETs in the bridge. This state is held until the beginning of the next fixed-frequency PWM cycle. Note that if current control is not needed, the xISEN pins should be connected directly to ground. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 9 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com nSLEEP Operation Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (up to 1 ms) needs to pass before the motor driver becomes fully operational. To make the board design simple, the nSLEEP can be pulled up to the supply (VM). It is recommended to use a pullup resistor when this is done. This resistor limits the current to the input in case VM is higher than 6.5 V. Internally, the nSLEEP pin has a 500-kΩ resistor to GND. It also has a clamping zener diode that clamps the voltage at the pin at 6.5 V. Currents greater than 250 µA can cause damage to the input structure. Hence the recommended pullup resistor would be between 20 kΩ and 75 kΩ. Protection Circuits The DRV8833 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (tOCP) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally. Overcurrent conditions are detected independently on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, so functions even without presence of the xISEN resistors. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. nFAULT is driven low in the event of an undervoltage condition. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com APPLICATIONS INFORMATION Parallel Mode The two H-bridges in the DRV8833 can be connected in parallel for double the current of a single H-bridge. The internal dead time in the DRV8833 prevents any risk of cross-conduction (shoot-through) between the two bridges due to timing differences between the two bridges. The drawing below shows the connections. Figure 3. Parallel Mode Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 11 DRV8833 SLVSAR1B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com THERMAL INFORMATION Maximum Output Current In actual operation, the maximum output current achievable with a motor driver is a function of die temperature. This in turn is greatly affected by ambient temperature and PCB design. Basically, the maximum motor current will be the amount of current that results in a power dissipation level that, along with the thermal resistance of the package and PCB, keeps the die at a low enough temperature to stay out of thermal shutdown. The dissipation ratings given in the datasheet can be used as a guide to calculate the approximate maximum power dissipation that can be expected to be possible without entering thermal shutdown for several different PCB constructions. However, for accurate data, the actual PCB design must be analyzed via measurement or thermal simulation. Thermal Protection The DRV8833 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops by 45°C. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8833 is dominated by the DC power dissipated in the output FET resistance, or RDS(ON). There is additional power dissipated due to PWM switching losses, which are dependent on PWM frequency, rise and fall times, and VM supply voltages. These switching losses are typically on the order of 10% to 30% of the DC power dissipation. The DC power dissipation of one H-bridge can be roughly estimated by Equation 2. 2 2 PTOT = (HS - RDS(ON) · IOUT(RMS) ) + (LS - RDS(ON) · IOUT(RMS) ) (2) where PTOT is the total power dissipation, HS - RDS(ON) is the resistance of the high side FET, LS - RDS(ON) is the resistance of the low side FET, and IOUT(RMS) is the RMS output current being applied to the motor. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8833 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8833PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8833PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8833RTYR ACTIVE QFN RTY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8833RTYT ACTIVE QFN RTY 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) DRV8833PWPR HTSSOP PWP 16 2000 330.0 12.4 DRV8833RTYR QFN RTY 16 3000 330.0 DRV8833RTYT QFN RTY 16 250 180.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 4.25 4.25 1.15 8.0 12.0 Q2 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8833PWPR HTSSOP PWP 16 2000 346.0 346.0 29.0 DRV8833RTYR QFN RTY 16 3000 346.0 346.0 29.0 DRV8833RTYT QFN RTY 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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