BRIEF MX88L60 DUAL-MODE PC CAMERA CONTROLLER FEATURES • PC Interface - High speed USB interface with embedded transceiver - UART interface with external transceiver, for best backward compatibility • Portable Mode Additional Features - Embedded 8051 micro-controller - Support external ROM code storage at Flash memory or EPROM - Embedded real-time-clock (RTC) for time stamp * Adjusted by PC software * On-System programming capability at portable mode - Support monochrome TN LCD for information display. The logos include: * Date * Time * Number of pictures left: 2 or 3 digits * Flash light status: ON/OFF/AUTO * Self Timer: On, Off, and Flash when push the snap shot button * Battery status: High, low, and empty * Continuous shots: On and Off * Quality (compression rate): Best, Better, Good (total 8 classes actually) * Image size: Full, 1/2 - Support self timer function - Support melody IC for singling control when * Initialization * Self timer * Snap shot * Low battery * Failure shot - Support flashlight charge control • Miscellaneous - 48 MHz system clock operation - Dedicated sensor clock input(optional) - Built in 27 general-purpose I/O pins - 160 pin LQFP • Power - 3.3V with power saving control • Image Sensor Interface - 8-bit to 10-bit resolution for digital image raw data input - Support imager with resolution up to SVGA (800x592)with windowing mode or random-access control - Support universal serial interface for various CCD and CMOS sensors * CCD sensor: Sony , Sharp , and Panasonic * CMOS sensor: Hyundai, HP, VLSI Vision (VVL), Photobit, Biomorphic, TASC, etc. • Image Processing Unit - Complete image processing functions: * RGB Bayer CFA color interpolation * Black reference * Defect concealment * Flare and black level correction * Brightness and contrast control * Edge enhancement * Color correction * Gamma correction * RGB to YUV color space conversion * Color saturation control * False color suppression * Image sub-sampling - Programmable 5(H) x 5(V) zones with programmable size for image statistical calculation to facilitate automatic exposure control and automatic white balance - Support focus-assisting signaling control (with Melody IC interface) • Video Compression Unit - High quality and high performance proprietary compression algorithm for live video capture and transferring * 30 fps for CIF (352x288) * 10~15 fps for VGA (640x480) • Memory Control Interface - Support both EDO DRAM (256Kx16) x1 or SDRAM (1Mx16) x1 or x2 - Support NAND-type Flash memory (8Mb,16Mb,32Mb,64Mb) x1 or x2 - Support serial Flash memory (MX25L4004, 4Mb) x1, x2,x3 or x4 - Support Compact Flash card and Smart Media card. - Support NDR-type Flash memory (16Mb,32Mb,64Mb) - Support EEPROM for sensor information - Support Flash memory format function, controlled by PC software P/N: PM0743 1 REV. 2.5B, AUG. 18, 2000 MX88L60 GENERAL DESCRIPTION supports, it is an ideal solution for a tethered digital video camera, which can capture real-time live video for entertainment or videoconference applications. For still image capture, the MX88L60 can also function as a controller for low-cost digital still camera (DSC) or toy camera. With Flash memory interface support and powersaving control, it can make the system work on battery power for portable purpose. The MX88L60 is a general-purpose controller for dualmode (tethered and portable) PC cameras and toy cameras. The MX88L60 contains all the necessary hardware supports, like image sensor control and interface, image capture and processing, proprietary video compression, memory control, USB and UART interface, embedded micro-controller and general-purpose I/Os. With the intensive hardware and associated software 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PSEN_B PALE RST_B EA CLK48O CLK48I VDD GPIO 25 GPIO 24 GPIO 23 GPIO 22 GPIO 21 CLKSNO CLKSN GPIO 20 GPIO 19 GPIO 18 GPIO 17 GND GPIO 16 GPIO 15 GPIO 14 GPIO 13 GPIO 12 GND VDD SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 ADCK VDD PBLK XCLPOB PIN CONFIGURATION 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 MX88L60 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 XCLPDM XRS GND XSHD XSHP XSG2 XSG1 XV3/HRO XV2/FRO XV1/HRI XV0FRI XSUB H2 H1 RG FQ7 FQ6 FQ5 FQ4 FQ0 VDD FQ1 FQ2 FQ3 GND VDD GND FCEB_B FCEA_B FRE_B FRB_B FCLE FALE FWE_B FWP_B DA4 DA5 DA6 DA7 DA8 VDD GND CLK32KI CLK32KO GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VDD GND DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DWE_B DCAS_B DRAS_B SDCSA_B SDCSB_B SDCKE VDD SD_CLK GND DOE_B DBANK DA10 DA0 DA1 DA2 DA3 DA9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 GND P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 GND VDD P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 GND VDD D+ DGND REV. 2.5B, AUG. 18, 2000 P/N: PM0743 2 MX88L60 Pin Numbers in Numerical Sequence Name VDD GND CLKRTCI CLKRTCO GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VDD GND DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DWE_B DCAS_B DRAS_B SDCSA_B SDCSB_B SDCKE VDD SDCLKO GND DOE_B Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DBANK DA10 DA0 DA1 DA2 34 35 36 37 38 Type Definition 3.3V I O RTC crystal oscillator input, 32KHz RTC crystal output I/O I/O I/O I/O I/O I/O I/O I/O DRAM data bit 0, pull high/low, mapping to register DRAM_TYPE[0] DRAM data bit 1, pull high/low, mapping to register DRAM_TYPE[1] DRAM data bit 2, pull high/low, mapping to register DCK[0] DRAM data bit 3, pull high/low, mapping to register DCK[1] DRAM data bit 4, , pull high/low, mapping to register DCK[2] DRAM data bit 5, pull high/low, mapping to register DCK[3] DRAM data bit 6, pull high/low, mapping to register TEST[0] DRAM data bit 7, pull high/low, mapping to register TEST[1] 3.3V I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O DRAM data bit 15, pull high/low, mapping to register TEST[9] DRAM data bit 14, pull high/low, mapping to register TEST[8] DRAM data bit 13, pull high/low, mapping to register TEST[7] DRAM data bit 12, pull high/low, mapping to register TEST[6] DRAM data bit 11, pull high/low, mapping to register TEST[5] DRAM data bit 10, pull high/low, mapping to register TEST[4] DRAM data bit 9, pull high/low, mapping to register TEST[3] DRAM data bit 8, pull high/low, mapping to register TEST[2] DRAM write enable DRAM Column address strobe DRAM Row address strobe SDRAM #0 chip select SDRAM #1 chip select SDRAM clock enable 3.3V SDRAM clock output O O O O O O O SDRAM, ldqm, udqm, EDORAM output enable SDRAM bank select SDRAM address bit 10 DRAM address bit 0 DRAM address bit 1 DRAM address bit 2 REV. 2.5B, AUG. 18, 2000 P/N: PM0743 3 MX88L60 Name DA3 DA9 DA8 DA7 DA6 DA5 DA4 FWP_B FWE_B Pin # 39 40 41 42 43 44 45 46 47 Type O O O O O O O O O FALE 48 O FCLE 49 O FRB_B 50 I FRE_B 51 O FCEA_B FCEB_B GND VDD GND FQ3 FQ2 FQ1 VDD FQ0 FQ4 FQ5 FQ6 FQ7 RG H1 H2 XSUB XV0/ FRI XV1/ HRI 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 O O I/O I/O I/O I/O I/O O O O O I/O 71 I/O Definition DRAM address bit 3 SDRAM address bit 9 DRAM address bit 8 DRAM address bit 7 DRAM address bit 6 DRAM address bit 5 DRAM address bit 4 Flash memory write protect NAND type flash memory write enable Serial flash data output NAND type flash memory address latch enable Serial flash memory #3 chip select NAND type flash memory command latch enable Serial flash memory #2 chip select NAND type flash memory read/busy input Serial flash data input NAND type flash memory read enable Serial flash clock output Flash memory #0 chip select Flash memory #1 chip select 3.3V I/O I/O I/O NAND type flash memory data bit 3, pull high/low, mapping to register GP_CFG[0] NAND type flash memory data bit 2, pull high/low, mapping to register FLASH_TYPE[2] NAND type flash memory data bit 1, pull high/low, mapping to register FLASH_TYPE[1] 3.3V NAND type flash memory data bit 0, pull high/low, mapping to register FLASH_TYPE[0] NAND type flash memory data bit 4, pull high/low, mapping to register GP_CFG[1] NAND type flash memory data bit 5, pull high/low, mapping to register GP_CFG[2] NAND type flash memory data bit 6, pull high/low, mapping to register GP_CFG[3] NAND type flash memory data bit 7, pull high/low, mapping to register GP_CFG[4] Reset gate pulse output for CCD image sensor Horizontal transfer pulse output 1 for CCD image sensor Horizontal transfer pulse output 2 for CCD image sensor Pulse output for electronic shutter Vertical transfer-pulse 0 for CCD image sensor; also can be programmed to vertical sync signal input. Vertical transfer-pulse 1 for CCD image sensor; also can be programmed to horizontal sync signal input. REV. 2.5B, AUG. 18, 2000 P/N: PM0743 4 MX88L60 Name XV2/ FRO XV3/ HRO XSG1 XSG2 XSHP XSHD GND XRS XCLPDM XCLPOB PBLK Pin # 72 Type O 73 O 74 75 76 77 78 79 80 81 82 O O O O VDD ADCK SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 VDD GND GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GND GPIO 17 GPIO 18 GPIO 19 GPIO 20 CLKSNI CLKSNO 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 O O O O O I I I I I I I I I I Definition Vertical transfer pulse 2 for CCD image sensor; also can be programmed to vertical sync signal output Vertical transfer pulse 3 for CCD image sensor; also can be programmed to horizontal sync signal output Readout pulse 1 for CCD image sensor Readout pulse 2 for CCD image sensor Pre-charge level sample-and-hold pulse Data level sample-and-hold pulse Sample-and-hold pulse output for analog/digital conversion IC Dummy bit block clamp pulse output Optical black bit block clamp pulse output Pre-blanking pulse that corresponds to the cease period of horizontal transfer pulse for CCD image sensor. 3.3V Clock output for analog/digital conversion IC or CMOS image sensor. Sensor input data bit 0 (LSB) Sensor input data bit 1 Sensor input data bit 2 Sensor input data bit 3 Sensor input data bit 4 Sensor input data bit 5 Sensor input data bit 6 Sensor input data bit 7 Sensor input data bit 8 Sensor input data bit 9(MSB) 3.3V I/O I/O I/O I/O I/O GPIO GPIO GPIO GPIO GPIO bit bit bit bit bit 12 13 14 15 16 I/O I/O I/O I/O I O GPIO bit 17 GPIO bit 18 GPIO bit 19 GPIO bit 20, 8051 clock off output Sensor clock crystal oscillator input Sensor clock crystal output REV. 2.5B, AUG. 18, 2000 P/N: PM0743 5 MX88L60 Name GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 VDD CLK48I CLK48O EA RST_B PALE PSEN_B P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 GND P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 GND VDD P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Type I/O I/O I/O I/O I/O I O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O Definition GPIO bit 21, flash light strobe output GPIO bit 22 GPIO bit 23 GPIO bit 24 GPIO bit 25 3.3V System clock crystal oscillator input, 48MHz System clock crystal output External ROM enable Hardware reset Address latch enable Program strobe enable 8051 port 0 bit 0, external address/data bus bit 0 8051 port 0 bit 1, external address/data bus bit 1 8051 port 0 bit 2, external address/data bus bit 2 8051 port 0 bit 3, external address/data bus bit 3 8051 port 0 bit 4, external address/data bus bit 4 8051 port 0 bit 5, external address/data bus bit 5 8051 port 0 bit 6, external address/data bus bit 6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8051 Port 0 bit 7, external address/data bus bit 7 8051 port 1 bit 0, GPIO bit 0, 8051 port 1 bit 1, GPIO bit 1, 8051 port 1 bit 2, GPIO bit 2, 8051 port 1 bit 3, GPIO bit 3 8051 port 1 bit 4, GPIO bit 4 8051 port 1 bit 5, GPIO bit 5 8051 port 1 bit 6, GPIO bit 6, SCL 8051 Port 1 bit 7, GPIO bit 7, SDA 8051 port 2 bit 0, external address bus bit 8 8051 port 2 bit 1, external address bus bit 9 8051 port 2 bit 2, external address bus bit 10 I/O I/O I/O I/O I/O I/O I/O 3.3V 8051 port 2 bit 3, external address bus bit 11 8051 port 2 bit 4, external address bus bit 12 8051 port 2 bit 5, external address bus bit 13 8051 port 2 bit 6, external address bus bit 14 8051 Port 2 bit 7, external address bus bit 15 8051 port 3 bit 0, GPIO bit 8, RXD 8051 port 3 bit 1, GPIO bit 9, TXD REV. 2.5B, AUG. 18, 2000 P/N: PM0743 6 MX88L60 Name P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 GND UVDD D+ DUGND Pin # 150 151 152 153 154 155 156 157 158 159 160 Type I/O I/O I/O I/O I/O I/O Definition 8051 port 3 bit 2, interrupt 0, 8051 port 3 bit 3, interrupt 1, 8051 port 3 bit 4, GPIO bit 10 8051 port 3 bit 5, GPIO bit 11 8051 port 3 bit 6, external SRAM write strobe, GPIO26 8051 Port 3 bit 7, external SRAM read strobe, GPIO27 I/O I/O 3.3V Data+, USB data bus Data-, USB data bus Pin Numbers/Definition by Function Power Supply Name VDD VDD VDD VDD VDD VDD VDD VDD VDD UVDD GND GND GND GND GND GND GND GND GND GND GND GND UGND Pin # 1 14 30 55 60 83 95 114 142 61 2 5 15 32 54 56 78 96 102 128 141 156 62 Type Definition 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V REV. 2.5B, AUG. 18, 2000 P/N: PM0743 7 MX88L60 Sensor Interface Name RG H1 H2 XSUB XV0/ FRI XV1/ HRI XV2/ FRO XV3/ HRO XSG1 XSG2 XSHP XSHD XRS XCLPDM XCLPOB PBLK Pin # 66 67 68 69 70 Type O O O O I/O 71 I/O 72 O 73 O 74 75 76 77 79 80 81 82 O O O O O O O O ADCK 84 O SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 85 86 87 88 89 90 91 92 93 94 I I I I I I I I I I Definition Reset gate pulse output for CCD image sensor Horizontal transfer pulse output 1 for CCD image sensor Horizontal transfer pulse output 2 for CCD image sensor Pulse output for electronic shutter Vertical transfer-pulse 0 for CCD image sensor; also can be programmed to vertical sync signal input. Vertical transfer-pulse 1 for CCD image sensor; also can be programmed to horizontal sync signal input. Vertical transfer pulse 2 for CCD image sensor; also can be programmed to vertical sync signal input Vertical transfer pulse 3 for CCD image sensor; also can be programmed to horizontal sync signal input Readout pulse 1 for CCD image sensor Readout pulse 2 for CCD image sensor Pre-charge level sample-and-hold pulse Data level sample-and-hold pulse Sample-and-hold pulse output for analog/digital conversion IC Dummy bit block clamp pulse output Optical black bit block clamp pulse output Pre-blanking pulse that corresponds to the cease period of horizontal transfer pulse for CCD image sensor. Clock output for analog/digital conversion IC or CMOS image sensor. Phase adjustment in 90O units. Sensor input data bit 0 (LSB) Sensor input data bit 1 Sensor input data bit 2 Sensor input data bit 3 Sensor input data bit 4 Sensor input data bit 5 Sensor input data bit 6 Sensor input data bit 7 Sensor input data bit 8 Sensor input data bit 9(MSB) REV. 2.5B, AUG. 18, 2000 P/N: PM0743 8 MX88L60 DRAM Interface Name DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DWE_B DCAS_B DRAS_B SDCSA_B SDCSB_B SDCKE SDCLKO DOE_B DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DBANK Pin # 6 7 8 9 10 11 12 13 23 22 21 20 19 18 17 16 24 25 26 27 28 29 31 33 36 37 38 39 45 44 43 42 41 40 35 34 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O Definition DRAM data bit 0, pull high/low, mapping to register DRAM_TYPE[0] DRAM data bit 1, pull high/low, mapping to register DRAM_TYPE[1] DRAM data bit 2, pull high/low, mapping to register DCK[0] DRAM data bit 3, pull high/low, mapping to register DCK[1] DRAM data bit 4, pull high/low, mapping to register DCK[2] DRAM data bit 5, pull high/low, mapping to register DCK[3], DRAM data bit 6, pull high/low, mapping to register TEST[0] DRAM data bit 7, pull high/low, mapping to register TEST[1] DRAM data bit 8, pull high/low, mapping to register TEST[2] DRAM data bit 9, pull high/low, mapping to register TEST[3] DRAM data bit 10, pull high/low, mapping to register TEST[4] DRAM data bit 11, pull high/low, mapping to register TEST[5] DRAM data bit 12, pull high/low, mapping to register TEST[6] DRAM data bit 13, pull high/low, mapping to register TEST[7] DRAM data bit 14, pull high/low, mapping to register TEST[8] DRAM data bit 15, pull high/low, mapping to register TEST[9] DRAM write enable DRAM Column address strobe DRAM Row address strobe SDRAM #0 chip select SDRAM #1 chip select SDRAM clock enable SDRAM clock output SDRAM, ldqm, udqm,EDORAM output enable DRAM address bit 0 DRAM address bit 1 DRAM address bit 2 DRAM address bit 3 DRAM address bit 4 DRAM address bit 5 DRAM address bit 6 DRAM address bit 7 DRAM address bit 8 SDRAM address bit 9 SDRAM address bit 10 SDRAM bank select REV. 2.5B, AUG. 18, 2000 P/N: PM0743 9 MX88L60 Flash Memory Interface Name FCLE FALE FWE_B FWP_B FRB_B FRE_B FCEA_B FCEB_B FQ0 Pin # 49 48 47 46 50 51 52 53 61 Type O O O O I O O O I/O Definition NAND type flash memory command latch enable Serial flash memory #2 chip select NAND type flash memory address latch enable Serial flash memory #3 chip select NAND type flash memory write enable Serial flash memory data output Flash memory write protect NAND type flash memory read/busy input Serial flash memory data input NAND type flash memory read enable Serial flash memory clock output Flash memory #0 chip select Flash memory #1 chip select NAND type flash memory data bit 0, pull high/low, mapping to register FLASH_TYPE[0] FQ1 FQ2 FQ3 FQ4 FQ5 FQ6 FQ7 59 58 57 62 63 64 65 I/O I/O I/O I/O I/O I/O I/O NAND type flash memory data bit 1, pull high/low, mapping to register FLASH_TYPE[1] NAND type flash memory data bit 2, pull high/low, mapping to register FLASH_TYPE[2] NAND type flash memory data bit 3, pull high/low, mapping to register GP_CFG[0] NAND type flash memory data bit 4, pull high/low, mapping to register GP_CFG[1] NAND type flash memory data bit 5, pull high/low, mapping to register GP_CFG[2] NAND type flash memory data bit 6, pull high/low, mapping to register GP_CFG[3] NAND type flash memory data bit 7, pull high/low, mapping to register GP_CFG[4] USB Interface Name D+ D- Pin # 158 159 Type Definition I/O Data+, USB data bus I/O Data-, USB data bus Micro-Controller Interface Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 Pin # 121 122 123 124 125 126 127 129 130 131 132 133 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Definition 8051 port 0 bit 0, external address/data bus bit 0 8051 port 0 bit 1, external address/data bus bit 1 8051 port 0 bit 2, external address/data bus bit 2 8051 port 0 bit 3, external address/data bus bit 3 8051 port 0 bit 4, external address/data bus bit 4 8051 port 0 bit 5, external address/data bus bit 5 8051 port 0 bit 6, external address/data bus bit 6 8051 Port 0 bit 7, external address/data bus bit 7 8051 port 1 bit 0, GPIO bit 0, 8051 port 1 bit 1, GPIO bit 1, 8051 port 1 bit 2, GPIO bit 2, 8051 port 1 bit 3, GPIO bit 3 REV. 2.5B, AUG. 18, 2000 P/N: PM0743 10 MX88L60 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 EA PALE PSEN_B 134 135 136 137 138 139 140 143 144 145 146 147 148 149 150 151 152 153 154 155 117 119 120 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O 8051 port 1 bit 4, GPIO bit 4 8051 port 1 bit 5, GPIO bit 5 8051 port 1 bit 6, GPIO bit 6, SCL 8051 Port 1 bit 7, GPIO bit 7, SDA 8051 port 2 bit 0, external address bus bit 8 8051 port 2 bit 1, external address bus bit 9 8051 port 2 bit 2, external address bus bit 10 8051 port 2 bit 3, external address bus bit 11 8051 port 2 bit 4, external address bus bit 12 8051 port 2 bit 5, external address bus bit 13 8051 port 2 bit 6, external address bus bit 14 8051 Port 2 bit 7, external address bus bit 15 8051 port 3 bit 0, GPIO bit 8, RXD 8051 port 3 bit 1, GPIO bit 9, TXD 8051 port 3 bit 2, interrupt 0, 8051 port 3 bit 3, interrupt 1, 8051 port 3 bit 4, GPIO bit 10 8051 port 3 bit 5, GPIO bit 11 8051 port 3 bit 6, external SRAM write strobe, GPIO26 8051 Port 3 bit 7, external SRAM read strobe, GPIO27 External ROM enable Address latch enable Program strobe enable Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Definition GPIO bit 12, sel_sram_b GPIO bit 13, usb_dpluso GPIO bit 14, usb_dminuso GPIO bit 15, usb_data_en_b GPIO bit 16, usb_suspendo GPIO bit 17, usb_dplusi GPIO bit 18, usb_dmiusi GPIO bit 19, usb_datai GPIO bit 20, 8032 clock off output GPIO bit 21, flash light strobe output GPIO bit 22 GPIO bit 23 GPIO bit 24 Miscellaneous Name GPIO12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 Pin # 97 98 99 100 101 103 104 105 106 109 110 111 112 REV. 2.5B, AUG. 18, 2000 P/N: PM0743 11 MX88L60 Absolute Maximum Ratings RATING DC Supply Voltage(VCC) DC Input/Output Voltage(Vin/Vout) Ambient Temperature(TA) Storage Temperature(TSTG) ESD rating(Rzap=1.5K,Czap=100pF) Power Dissipation(PD) Power Dissipation(Normal) VALUE 3.0V to 3.6V -0.5V to VCC+0.5V 0 to 70Celsius -40 to 125Celsius 2000V 0.7mW 0.4W DC Characteristics SYMBOL VIL VIH VOL VOH ICC IIL IIH Rpullup IDD Cin Cout Description Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Power Supply Current Input Low Current Input High Current Pull Up Resistance Static IDD Current Input Capacitance Output Capacitance MIN 2.0 0.8VCC -1 20 3 MAX 0.8 0.4 130 1 1 60 Test Conditions I=4ma I=4ma VCC=3.3V 640x480x10Hz VCC=3.5V, Vin=0V Vin=VCC 10 45 Unit Volt Volt Volt Volt ma ua ua K ohm ma pf pf AC Characteristics RESET Timing AC Characteristics RST_B TRST SYMBOL TRST Description Reset Pulse Width MIN 250 MAX Test Conditions Unit ns REV. 2.5B, AUG. 18, 2000 P/N: PM0743 12 MX88L60 Clock AC Characteristics TCYC THIGH TLOW SYMBOL PARAMETER MIN TYP MAX Unit CLK48I 48 Mhz CLK32KI 32.768 Khz SD_CLK 48 Mhz CLK48I 10.4 ns CLK32KI 15.2 ms SD_CLK 10.4 ns CLK48I 10.4 ns CLK32KI 15.2 ms SD_CLK 10.4 ns 1/TCYC THIGH TLOW REV. 2.5B, AUG. 18, 2000 P/N: PM0743 13 MX88L60 SDRAM Interface Timings SD_CLK TCKS TCKH SDCKE TAS TAH TDS TDH DA DQ TCMH TCMS SDCS*_B TCMH DRAS_B TCMS TCMH DCAS_B DWE_B TCMS DOE_B Parameter SYMBOL MIN TYP MAX _ Unit ns Address setup time Address hold time TAS 3 _ TAH 1.5 _ _ ns Data-in setup time TDS 3 _ _ ns Data-in hold time CKE setup time CKE hold time TDH 1.5 _ _ ns TCKS 3 _ _ ns TCKH 1.5 _ _ ns TCMS 3 _ _ ns TCMH 1.5 _ _ ns Command setup time Command hold time Note : SDRAM Interface Timing is adjustable in the step of about 2ns REV. 2.5B, AUG. 18, 2000 P/N: PM0743 14 MX88L60 NANDFLASH Interface Timings * Command Latch Cycle FCLE tCLS tCLH tCS tCH FCE*_B tWP FWE_B tALS tALH FALE tDH tDS Command FQ 0 ~ 7 * Address Latch Cycle tCLS FCLE tCS tWC tWC FCE*_B tWP tWP tWP FWE_B tWH tWH tALS tALH FALE tDS FQ 0 ~ 7 tDH A 0~A 7 tDS tDH A 8~A 15 tDS tDH A 16~A 20 REV. 2.5B, AUG. 18, 2000 P/N: PM0743 15 MX88L60 * Input Data Latch Cycle tCLH FCLE tCH FCE*_B tALS tWC tWP » FALE tWP tWP FWE_B tDS FQ 0 ~ 7 tWH tDH DIN 0 tDS tDH tDS tDH DIN 255 DIN 1 * Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) tRC FCE*_B tCHZ* » tREH FRE_B Dout FQ 0 ~ 7 Dout » tRHZ* Dout tRR FRB_B REV. 2.5B, AUG. 18, 2000 P/N: PM0743 16 MX88L60 * Status Read Cycle tCLS FCLE tCLS tCLH tCS FCE*_B tCH tWP FWE_B tCHZ* tWHR FRE_B tDS FQ 0 ~ 7 tDH tRHZ* Status Output 70H REV. 2.5B, AUG. 18, 2000 P/N: PM0743 17 MX88L60 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min Max Unit CLE Set-up Time tCLS 1 CLK * CLE Hold Time tCLH 2 CLK CE Setup Time tCS 2 CLK CE Hold Time tCH 8 CLK WE Pulse Width tWP 2 CLK ALE Setup Time tALS 1 CLK ALE Hold Time tALH 2 CLK Data Setup Time tDS 2 CLK Data Hold Time tDH 2 CLK Write Cycle Time tWC 4 CLK WE High Hold Time tWH 2 CLK AC Characteristics for Operation Parameter Symbol Min Max Unit Ready to RE Low tRR 6 CLK Read Cycle Time tRC 4 CLK RE High to Output Hi-Z tRHZ 0 CE High to Output Hi-Z tCHZ 0 RE High Hold Time tREH 1 CLK WE High to RE Low tWHR 3 CLK * 1 CLK = one CLK48I cycle time REV. 2.5B, AUG. 18, 2000 P/N: PM0743 18 MX88L60 SENSOR Interface Timings tADCK ADCK tpd1 tSD SD[9:0] tpd2 HRO Symbol tADCK tSD tpd1 tpd2 Definition ADCK cycle time sensor data cycle time sensor data input delay HRO rising delay Min. 20.8 1 0 0 Typ. - Max. 6 6 - Unit ns TADCK TADCK ns * 1 TADCK = one ADCK cycle time REV. 2.5B, AUG. 18, 2000 P/N: PM0743 19 MX88L60 CCD sensor interface timings tCK CLK48I tpd3 twh1 tH1 H1/H2 tpd4 twh2 RG tpd5 twh3 XRS tpd6 twl1 XSHP tpd7 twl2 XSHD CLoad : 35pF, 25OC Symbol Definition tH1 H1/H2 cycle time tpd3 H1/H2 rising delay, activated by the rising edge of CLK48I tpd4 RG rising delay, activated by the rising edge of CLK48I tpd5 XRS rising delay, activated by the rising edge of CLK48I tpd6 XSHP falling delay, activated by the rising edge of CLK48I tpd7 XSHD falling delay, activated by the rising edge of CLK48I twh1 H1/H2 high level width twh2 Pulse width of RG twh3 Pulse width of XRS twl1 Pulse width of XSHP twl2 Pulse width of XSHD Min. 4 1.2 3.0 3.0 3.0 2.6 Typ. 2 1 1 1 1 Max. - - Unit SCLK* ns** ns** ns** ns** ns** SCLK SCLK SCLK SCLK SCLK * 1 SCLK = one cycle of CLK48I or SD.CLK ** adjustable by registry settings REV. 2.5B, AUG. 18, 2000 P/N: PM0743 20 MX88L60 0.9Vdd 0.9Vdd H1 0.1Vdd 0.1Vdd trH1 tfH1 0.9Vdd 0.9Vdd RG 0.1Vdd 0.1Vdd trRG tfRG CLoad : 30pF, 25OC Symbol trH1 tfH1 trRG tfRG Definition H1 rise time H1 fall time RG rise time RG fall time Min. Typ. 2.1 1.8 2.1 1.8 Max. Unit ns ns ns ns REV. 2.5B, AUG. 18, 2000 P/N: PM0743 21 MX88L60 PACKAGE INFORMATION ©ô§»¹q¤lªÑ¥÷¦³¤½¥q DWG. NO. 6110-0239 TOLERANCE Macronix International Co., Ltd. OUTLINE DIMENSIONS FOR TITLE 160 LQFP 20X20X1.4mm(2.0mm FOOTPRINT)PACKAGE DRAWN APPROVED SCALE C.L.Chiang JW Lin UNIT REVISION 1 − REV. 2.5B, AUG. 18, 2000 P/N: PM0743 22 MX88L60 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.