ETC NT6861U

NT6861
8-Bit Microcontroller for Monitor
Features
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40 pin DIP & 42 pin SDIP package
Operating Voltage Range: 4.5V to 5.5V
CMOS technology for low power consumption
Crystal oscillator or ceramic resonator* available
6502 8-bit CMOS CPU core
8MHz operation of frequency
4/8/12/16/24K bytes ROM are available
256 bytes of RAM (which stores EDID for DDC1/2B)
One 8-bit pre-loadable base timer
14 channels of 8 bit PWM outputs:
6 channel with 5V open drain and 8 channel with 12V
open drain
n 2 channel A/D converters with 6-bit resolution
24 bi-directional I/O port pins and 1 I/P pin
Hsync/Vsync signal processor
Hardware sync signals polarity & freq. evaluator
Built-In I2C bus interface
Supporting VESA DDC1/2B function
Six-interrupt sources
- INTV (Vsync INT)
- INTE (External INT with rising edge trigger)
- INTMR (Timer INT )
- INTA (Slave Address Matched INT)
- INTD (Shift Register INT)
- INTS (SCL GO-LOW INT)
n Hardware watch-dog timer function
General Description
NT6861 is a monitor component µC for auto-sync and
digital controlled applications. It contains a 6502
8-bit CPU core, 256 bytes of RAM used as working RAM
and stack area, 24K bytes of ROM maximum for
programming, 14-channel 8-bit PWM D/A converters, 2channel A/D converters for key detection saving I/O pins,
one 8 bit pre-loadable base timer, internal Hsync and
Vsync signals processor providing mode detection,
watch-dog timer preventing system from abnormal
operation, and an I2C bus interface.
Users can store EDID data in the 128 bytes of RAM for
DDC1/2B, so that users can save the cost of dedicated
EEPROM for EDID. Half frequency output function can
save external one-shot circuit. All of these designs create
savings in component costs.
* The frequency deviation of ceramic resonator has
+/- 6% maximum.
1
V2.0
NT6861
Pin Configuration
[OE] DAC2
DAC1
DAC0
[A11] P13/HALFHI
[A10] P12/HALFHO
[A9] P11/AD1
[A8] P10/AD0
P16/INTE
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
14
15
16
17
18
19
20
*[
NT6861
P15
[CE] P14
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
[OE] DAC2
DAC1
DAC0
[VPP] RESET
V DD
NC
GND
OSCO
VSYNCI/INTV/ [A14]
HSYNCI
DAC3 [PGM]
DAC4 [MODE0]
DAC5 [MODE1]
DAC6 [MODE2]
DAC7
P07/HSYNCO [A7]
OSCI
P15
[CE] P14
[A11] P13/HALFHI
[A10] P12/HALFHO
[A9] P11/AD1
[A8] P10/AD0
P16/INTE
P06/VSYNCO [A6]
P05/DAC13 [A5]
P04/DAC12 [A4]
P03/DAC11 [A3]
P02/DAC10 [A2]
P01/DAC9 [A1]
P00/DAC8 [A0]
P31/SCL [A13]
P30/SDA [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]
[DB7] P27
[DB6]P26
[DB5] P25
[DB4] P24
[DB3] P23
]: OTP Mode
1
2
3
4
5
6
7
8
42
41
40
39
NT6861U
[VPP] RESET
V DD
GND
OSCO
OSCI
1
2
3
4
5
6
7
8
9
10
11
12
13
9
10
11
12
13
14
15
16
17
18
19
20
21
*[
38
37
36
VSYNCI/INTV
HSYNCI
DAC3 [PGM]
DAC4 [MODE0]
DAC5 [MODE1]
NC
DAC6 [MODE2]
35
34
33
32
31
30
29
28
27
26
DAC7 [A14]
P07/HSYNCO [A7]
P06/VSYNCO [A6]
P05/DAC13 [A5]
P04/DAC12 [A4]
P03/DAC11 [A3]
P02/DAC10 [A2]
P01/DAC9 [A1]
P00/DAC8 [A0]
P31/SCL [A13]
25
24
23
22
P30/SDA [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]
]: OTP Mode
Block Diagram
VDD
GND
Timing Generator
Program ROM
4/8/12/16/24K Bytes
IIC BUS
SCL
SDA
OSCI
OSCO
CPU core
6502
SRAM + STACK
256 Bytes
PWM DACs
DAC0 - DAC7
DAC8 - DAC13
A/D Converter
AD0 - AD1
INTE
VSYNCI/INTV
HSYNCI
Interrupt
Controller
8 Bit Base Timer
P00 - P07
I/O Ports
VSYNCO
HSYNCO
HALFHI
H/V Sync Signals
Processor
P10 - P15
P16
Watch Dog Timer
P20 - P27
P30 - P31
HALFHO
2
NT6861
Pin Descriptions
Pin No.
Designation
*
Reset Init.
I/O
Description
40 Pin
42 Pin
1
1
DAC2
O
Open drain 12V, D/A converter output 2
2
2
DAC1
O
Open drain 12V, D/A converter output 1
3
3
DAC0
O
Open drain 12V, D/A converter output 0
4
4
RESET
I
Schmitt trigger input pin, low active reset*
5
5
VD D
P
Power
6
7
GND
P
Ground
7
8
OSCO
O
Crystal OSC output
8
9
OSCI
I
Crystal OSC input
9
10
P15
I/O
Bi-directional I/O pin
10
11
P14
I/O
Bi- directional I/O pin
11
12
P13/HALFHI
P13
I/O
Bi- directional I/O pin, shared with half hsync input
12
13
P12/HALFHO
P12
I/O
Bi- directional I/O pin, shared with half hsync output
13
14
P11/AD1
P11
I/O
Bi- directional I/O pin, shared with A/D converter channel
1 input
14
15
P10/AD0
P10
I/O
Bi- directional I/O pin, shared with A/D converter channel 0
input
15
16
P16/INTE
P16
I
Schmitt trigger input pin with internal pull high, shared with
external Rising-edge trigger interrupt
16 - 23
17 - 24
P27 - P20
I/O
Bi- directional I/O pin, push-pull structure with high current
drive/sink capability
This RESET pin must be pulled high by external pulled-up resistor (5KΩ suggestion), or it will stay low
voltage to reset system all the time.
3
NT6861
Pin Descriptions (continued)
Pin NO.
Designation
Reset Init.
I/O
Description
25
P30/SDA
P30
I/O
Open drain 5V Bi-direction I/O pin P30, shared with SDA pin of
I2C bus schmitt trigger buffer
25
26
P31/SCL
P31
I/O
Open drain 5V Bi-direction I/O pin P31, shared with SCL pin of
I2C
bus schmitt trigger buffer
26
27
P00/DAC8
P00
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 8
27
28
P01/DAC9
P01
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 9
28
29
P02/DAC10
P02
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 10
29
30
P03/DAC11
P03
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 11
30
31
P04/DAC12
P04
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 12
31
32
P05/DAC13
P05
I/O
Bi- directional I/O pin, shared with open drain 5V D/A converter
output 13
32
33
P06/VSYNCO
P06
I/O
Bi- directional I/O pin, shared with vsync out
33
34
P07/HSYNCO
P07
I/O
Bi-directional I/O pin, shared with hsync out
34
35
DAC7
O
Open drain 12V, D/A converter output
35
36
DAC6
O
Open drain 12V, D/A converter output
36
38
DAC5
O
Open drain 12V, D/A converter output
37
39
DAC4
O
Open drain 12V, D/A converter output
38
40
DAC3
O
Open drain 12V, D/A converter output
39
41
HSYNCI
I
Debouncing & Schmitt trigger input pin for video horizontal
sync signal, internal pull high, shared with composite sync
input
40
42
VSYNCI/INTV
I
Debouncing & Schmitt trigger input pin for video vertical sync
signal, intermally pull high, shared with external interrupt
source
-
6
NC
-
37
NC
40 Pin
42 Pin
24
VSYNCI
4
NT6861
Functional Descriptions
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing
capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input
options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.
7
0
Accumulator A
7
0
Index Register Y
7
0
Index Register X
15
8
Program Counter PCH
PCL
7
0
7
0
Stack Pointer SP
7
N
0
V
B
D
I
Z
C
Status Register P
Carry
1 = TRUE
Zero
1 = Result ZERO
1 = DISABLE
IRQ Disable
Decimal Mode
BRK Command
1 = TRUE
1 = BRK
Overflow
1 = TRUE
Negative
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
NT6861
2. Instruction set list
Instruction Code
Meaning
Operation
ADC
Add with carry
A + M + C → A, C
AND
Logical AND
A• M → A
ASL
Shift left one bit
C ← M7 • • • M0 ← 0
BCC
Branch if carry clears
Branch on C = 0
BCS
Branch if carry sets
Branch on C = 1
BEQ
Branch if equal to zero
Branch on Z = 1
BIT
Bit test
A • M, M7 → N, M6 → V
BMI
Branch if minus
Branch on N = 1
BNE
Branch if not equal to zero
Branch on Z = 0
BPL
Branch if plus
Branch on N = 0
BRK
Break
Forced Interrupt PC+2 ↓ PC ↓
BVC
Branch if overflow clears
Branch on V = 0
BVS
Branch if overflow sets
Branch on V = 1
CLC
Clear carry
0→C
CLD
Clear decimal mode
0→D
CLI
Clear interrupt disable bit
0→I
CLV
Clear overflow
0→V
CMP
Compare accumulator to memory
A− M
CPX
Compare with index register X
X − M
CPY
Compare with index register Y
Y− M
DEC
Decrement memory by one
M− 1 → M
DEX
Decrement index X by one
X− 1 → X
DEY
Decrement index Y by one
Y − 1→ Y
EOR
Logical exclusive-OR
A⊕M→ A
INC
Increment memory by one
M + 1→ M
INX
Increment index X by one
X + 1→ X
INY
Increment index Y by one
Y + 1→ Y
6
NT6861
Instruction set list (continued)
Instruction Code
Meaning
Operation
JMP
Jump to new location
(PC+1) → PCL, (PC+2) → PCH
JSR
Jump to subroutine
PC + 2 ↓, (P+1) → PCL, (PC+2) → PCH
LDA
Load accumulator with memory
M→ A
LDX
Load Index register X with memory
M→ X
LDY
Load Index register Y with memory
M→ Y
LSR
Shift right one bit
0 → M7 • • • M0 → C
NOP
No operation
No operation (2 cycles)
ORA
Logical OR
A+M →A
PHA
Push accumulator on stack
A↓
PHP
Push status register on stack
P↓
PLA
Pull accumulator from stack
A↑
PLP
Pull status register from stack
P↑
ROL
Rotate left through carry
C ← M7 • • • M0 ← C
ROR
Rotate right through carry
C → M7 • • • M0 → C
RTI
Return from interrupt
P ↑, PC ↑
RTS
Return from subroutine
PC ↑, PC+1 → PC
SBC
Subtract with borrow
A − M − C → A, C
SEC
Set carry
1→C
SED
Set decimal mode
1→D
SEI
Set interrupt disable status
1→I
STA
Store accumulator in memory
A →M
STX
Store index register X in memory
X →M
STY
Store index register Y in memory
Y →M
TAX
Transfer accumulator to index X
A→ X
TAY
Transfer accumulator to index Y
A→ Y
TSX
Transfer stack pointer to index X
S→ X
TXA
Transfer index X to accumulator
X→ A
TXS
Transfer index X to stack Pointer
X→ S
TYA
Transfer index Y to accumulator
Y→ A
* Refer to 6502 programming data book for more details.
7
NT6861
3. RAM: 256 X 8 bits
256 X 8-bit SRAM is used for data memory and stack. The RAM addressing range is from $0080 to $017F. From $0100 to
$017F is used as the EDID data buffer when activating DDC1/2B mode transmission. The contents of RAM are undetermined
at power-up and are not affected by system reset. Software programmers can allocate stack area in the RAM by setting stack
pointer register S. Because the 6502 default stack pointer is $01FF, programmers must set register S to FFH when starting the
program, so the stack area will map $01FF - $0180 to $00FF - $0080.
as;
LDX
TXS
#$FF
$0000
$0025
System Registers
Unused
$0080
RAM
stack pointer
$00FF
$0100
EDID
$017F
$0180
Unused
$BFFF
$A000
(4/8/12/16/24K Bytes)
ROM
$FFFC
RST-L
$FFFD
RST-H
IRQ-L
RESET vector
IRQ-H
IRQ vector
$FFFE
$FFFF
8
NT6861
4. System Registers
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0000
PT0
FFH
P07
P06
P05
P04
P03
P02
P01
P00
RW
$0001
PT1
7FH
-
P16
P15
P14
P13
P12
P11
P10
RW
$0002
PT2DIR
FFH
P27OE
P26OE
P25OE
P24OE
P23OE
P22OE
P21OE
P20OE
W
$0003
PT2
FFH
P27
P26
P25
P24
P23
P22
P21
P20
RW
$0004
PT3
03H
-
-
-
-
-
-
P31
P30
RW
$0005
MD CON
07H
-
-
-
-
-
-
S/ C
MD1/ 2
R
INSEN
HSEL
S/ C
MD1/ 2
W
HCNTOV
VCNTOV
HSYNCI
VSYNCI
HPOLI
VPOLI
HPOLO
VPOLO
R
W
$0006
HV CON
2FH
$0007
HCNT L
00H
HCL7
HCL6
HCL5
HCL4
HCL3
HCL2
HCL1
HCL0
R
$0008
HCNT H
00H
-
-
-
-
HCH3
HCH2
HCH1
HCH0
R
$0009
VCNT L
00H
VCL7
VCL6
VCL5
VCL4
VCL3
VCL2
VCL1
VCL0
R
$000A
VCNT H
00H
-
-
-
-
VCH3
VCH2
VCH1
VCH0
R
$000B
SYNCON
FFH
NOHALF
ENHALF
-
FRUN
FRFREQ
HALFPOL
ENH
ENV
W
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$000D
AD0 REG
C0
H
CEND
AD05
AD04
AD03
AD02
AD01
AD00
R
W
CSTA
$000E
AD1 REG
00H
-
-
AD15
AD14
AD13
AD12
AD11
AD10
R
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
9
NT6861
System Registers (continued)
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0012
CLR WDT
-
0
1
0
1
0
1
0
1
W
$0013
II ADR
FFH
AR7
AR6
AR5
AR4
AR3
AR2
AR1
-
W
$0014
II DAT
00H
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RW
$0015
II STS
08H
-
-
START
START
STOP
STOP
RXAK
-
ENDDC
TRX
R
W
$0016
BT
00H
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
$0017
BT CON
03H
-
-
-
-
-
-
TBS
ENBT
W
$0018
DACH0
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0019
DACH1
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001A
DACH2
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001B
DACH3
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001C
DACH4
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001D
DACH5
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001E
DACH6
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001F
DACH7
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0020
DACH8
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0021
DACH9
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0022
DACH10
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0023
DACH11
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0024
DACH12
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0025
DACH13
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
Note: The line above a writable signal name indicate an active low signal
The dash line in these control register indicate an undefined bit
The address of control register from $0026 to $007F are not used.
10
NT6861
5. Timing Generator
This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal quartz,
ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock,
(4 MHz for CPU), Although internal circuits have a feedback resistor and compacitor included, components may be externally
added to ensure proper operation. The typical clock frequency is 8MHz. This frequency will affect the operation of on-chip
peripherals whose operating frequency is based on the system clock .
OSCI
External Clock
OSCI
8MHz
OSCO
Unconnected
OSCO
(2)
(1)
NT6861
NT6861
Figure 2. Oscillator Connections
6. A/D Converter
The analog to digital converter is a single 6-bit successive approximation converter. Analog voltage is supplied from external
sources to the A/D input pins and the results of the conversion are stored in the 6-bit data latch registers
($000D & $000E). The A/D converter is controlled by the control bits in the A/D control register ENDAC. Refer to the A/D
channel format table A/D input pins activation. A conversion is started by setting a '0' to the CONVERSION START bit ( CSTA )
in the A/D control register ($000D). This automatically sets the CONVERSION END bit ( CEND ) to '1'. When a conversion has
been finished, CEND bit automatically clears to '0'. The A/D conversion data in the AD LATCH registers ($000D & $000E) is
valid digital data.
The analog voltage to be measured should be stabled during the conversion operation. The variation should exceed
1/2 LSB for accuracy in measurement. Please refer Figure 3 for checking the linearity of A/D.
A/D Channel Format Table
ENAD1
ENAD0
P11 line
P10 line
0
0
AD1
AD0
0
1
AD1
P10
1
0
P11
AD0
1
1
P11
P10
11
NT6861
A/D Channel Control Register
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$000D
AD0 REG
C0H
CEND
AD05
AD04
AD03
AD02
AD01
AD00
R
W
AD15
AD14
AD13
AD12
AD11
AD10
R
CSTA
$000E
AD1 REG
00H
-
-
Input Voltage
Digital Value
Input Voltage
Digital Value
Input Voltage
Digital Value
1.5
19 ($13)
2.22
28 ($1C)
2.91
37 ($25)
1.58
20 ($14)
2.29
29 ($1D)
2.98
38 ($26)
1.65
21($15)
2.37
30 ($1E)
3.06
39 ($27)
1.73
22 ($16)
2.45
31 ($1F)
3.15
40 ($28)
1.81
23 ($17)
2.53
32 ($20)
3.24
41 ($29)
1.90
24 ($18)
2.61
33 ($21)
3.32
42 ($2A)
1.97
25 ($19)
2.68
34 ($22)
3.40
43 ($2B)
2.06
26 ($1A)
2.76
35 ($23)
3.47
44 ($2C)
2.14
27 ($1B)
2.84
36 ($24)
3.55
45 ($2D)
70
These digitals have±
1 LSB deviation
60
Digital Value
Linear Range
50
40
30
20
10
0
V DD
0
0.2
0.3
0.4
0.6
0.7
0.8
Input Voltage
Figure 3. A/D Converter Linearity Diagram
12
1
NT6861
7. PWM DACs (Pulse Width Modulation D/A Converters)
There are 14 PWM D/A converters with 8-bit resolution in NT6861. Eight of these D/A (DAC0 - DAC7) converters are opendrain output structures with 12V applied (maximum), and the other six D/A converters (DAC8 - DAC13) are
open-drain output structures with 5V applied (maximum). The PWM frequency is 31.25 KHz on 8 MHz system clock. Use of a
different oscillator frequency will result in different PWM frequency. As DAC8 - DAC13 are shared with I/O port pins, user can
write '0' to corresponding enable bit in the ENDAC control register to activate each of DACH8 - 13. There are 14-channel
readable DACH registers corresponding to 14 D/A converters. Each PWM output pulse width is programmable by setting the 8
bit digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND
level) and each bit addition will add 125ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output). Refer to
Figure 4 for the detailed timing diagram of PWM D/A output.
8MHz Fosc
PWM value:
00
255
0
1
2
m
m+1
m+2
255
0
1
01
02
m
255 (FF)
Figure 4. The DAC Output Timing Diagram and Wave Table
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
DAC Output Duty Cycle
0
0
0
0
0
0
0
0
GND
0
0
0
0
0
0
0
1
1/256 Vref.
0
0
0
0
0
0
1
0
2/256 Vref.
0
0
0
0
0
0
1
1
3/256 Vref.
0
0
0
0
0
1
0
0
4/256 Vref.
-
-
-
-
-
-
-
-
X /256 Vref.
1
1
1
1
1
1
1
0
254/256 Vref.
1
1
1
1
1
1
1
1
255/256 Vref.
The DAC value correspondent to PWM Output
* Vref. is 12V or 5V
13
NT6861
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$0018
DACH0
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0019
DACH1
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001A
DACH2
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001B
DACH3
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001C
DACH4
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001D
DACH5
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001E
DACH6
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$001F
DACH7
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0020
DACH8
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0021
DACH9
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0022
DACH10
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0023
DACH11
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0024
DACH12
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0025
DACH13
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
DAC control register ($000C) and DAC value register ($0018 - $0025)
Control Bit Description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$0018
DACH0
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
ENDK8 : Enable DAC channel 8; When clearing this bit to '0', the I/O port, P00, will change to DAC channel 8.
When setting this bit to '1', the I/O port will restore to P00.
ENDK9 - ENDK13 : The manipulation is the same as ENDK8 bit, and control DAC channel 9 - 13.
DACH0 (DKVL0 - DKVL7): Setting DAC output waveform of DAC channel 8. Please check Figure 3 for the timing diagram
and wave table.
DACH1 - DACH13: The manipulation is the same as DACH0 register, and control DAC channel 1 - 13.
14
NT6861
waveform and DAC8 - DAC13 is disabled
8. Watch-dog timer is cleared and enabled
8. RESET
NT6861 can be reset by the external reset pin or by the
internal watch-dog timer. This resets or starts the
microcontroller from a power-down condition. During the
time that this reset pin is held low (*reset line must be held
low for at least two CPU clock cycles), writing to or from the
µC is inhibited. When positive edge is detected on the
reset input, the µC will immediately begin reset sequence.
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the µC will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.
To improve noise immunity a Schmitt Trigger buffer is
provided at the RESET .
This RESET pin must be pulled high by external pulled-up
resistor (5KΩ suggestion), or it will stay low voltage to reset
system all the time (Refer to Figure 5 ).
9. Watch-dog timer (WDT)
NT6861 implements a watch-dog timer reset to avoid
system shut-down or malfunction. The clock of the WDT is
from on-chip RC oscillator not requiring any external
components. The WDT runs regardless if the clock of the
OSCI/OSCO pins of the device has been stopped. The
WDT time interval is about 0.5 second. The WDT must be
cleared within every 0.5 second when software is in normal
sequence, otherwise the WDT will overflow and cause
reset. The WDT is cleared and enabled after system is
reset. It cannot be disabled by software. Users can clear
the WDT by writing 55H to CLRWDT register.
Reset status is as follows:
1. PORT0 PORT1. PORT2. PORT3 pins will act as
I/O ports with HIGH output.
2. Sync processor counters reset and VCNT | HCNT
latches cleared
3. All sync outputs are disabled
4. Base timer is disabled and cleared
5. A/D Converter is disabled and stopped
6. DDC1/2B function is disabled
7. PWM DAC0 - DAC7 output 50% duty
as;
LDA
STA
#$55
$0012
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0012
CLR WDT
-
0
1
0
1
0
1
0
1
Vcc
5K
Ohm
Reset_
Figure 5. External Reset Suggested Circuit
15
NT6861
External
Low Voltage
Reset Circuit
W
NT6861
10. Interrupt Controller
The µC will complete the current instruction being
executed before recognizing the interrupt request. At this
time, the interrupt mask bit in the status register will be
examined. If the interrupt mask bit is not set, µC will begin
interrupt sequence. The program counter and processor
status register are stored in the stack. µC will then set the
interrupt mask flag HIGH so that no further interrupts
occur. At the end of this cycle, the program counter will be
loaded from addresses $FFFE & $FFFF, transferring
program control to the memory vector located at these
addresses.
Three memory mapped registers are used to control the
interrupt operation. The IRQX is set by the rising edge of
external pins (INTV & INTE), base timer overflow (INTR),
SCL line go-low (INTS), and serial bus interrupt (INTA &
INTD). The serial bus interrupt is generated by the I2C
circuit as described in under I2C bus interface sections.
The interrupt enable (IEX) bit will effects the interrupt
process if the IRQX has already been set. Once IEX bit is
set, its corresponding interrupt will generate an interrupt
source for 6502 CPU. The IRQX will be set no matter the
IEX bit enable or not. The interrupt request is generated
when IRQX and IEX are both '1'. The IRQX remains in
HIGH state unless the CLRIRQ register is cleared (write '1'
to correspondent bit in CLRIRQ register). The interrupt
enable register (IEX) and interrupt request register (IRQX)
are memory mapped registers which can only be accessed
or tested by program. These registers are cleared to '0' at
initialization after the chip is reset .
When interrupt occurs, CPU jumps to $FFFE & $FFFF to
execute interrupt service routine and finds which one of the
interrupt sources is active by checking the IRQX. Upon
entering the interrupt service routine, the IRQX that caused
the interrupt service must be cleared in the interrupt
service routine program. CPU clears IRQX by writing '1' to
the corresponding bit in CLRIRQ register. If more than one
interrupt is pending and waiting to be served, each is
executed by priority. Priority is defined by the programmer.
Six interrupt sources are available in this system:
- INTV INT (Vsync INT): Rising edge of every Vsync
pulse
- INTE INT (External INT): Rising edge of external
interrupt pulse
- INTMR INT (Timer INT): As the Base Timer counter
overflow and counting from $FF to $00
- INTA INT (Address Matched INT): External device
calling NT6861 in DDC2 mode communication
- INTD INT (Shift Register INT): Shift register is
empty or receiving a new byte data in DDC1 & DDC2
mode communication
- INTS INT (SCL Go-Low INT): External device
proceed a DDC2 communication
Control bit description:
ADDR.
REGISTER
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
IRQINTS is the interrupt flag for SCL- At DDC2B TRANSMISSION mode, it is set when SCL line changes from '1' to '0'.
IEINTS enable 6502 interrupt for INTS. - When this bit is set to '1' and IRQINTS flag is set, 6502 will accept interrupt source
and jump to interrupt service routine assigned by interrupt vector.
CLRINTS clears INTS interrupt flag. - Before returning from interrupt service routine, this flag must be cleared.
The manipulation of other interrupt source is the same as INTS.
CLRHOV & CLRVOV: Clear the overflow flag of H/V counter and reset H/V counter to zero.
16
NT6861
ups. In this state they can be used as input, then the input
signal can be read. This port outputs high after reset .
P00 - P05 are shared with DAC8 - DAC13 respectively. If
user sets ENDK8 - ENDK13 LOW in ENDAC register,
P00 - P05 will act as DAC8 - DAC13 respectively
(Figure 7). After the chip is reset, ENDK - ENDK13 will
enter HIGH state and P00 - P05s will act as I/O ports.
11. I/O PORTs
NT6861 has 25 pins dedicated to input and output. These
pins are grouped into 4 ports .
11.1. Port0: P00 - P07
Port0 is an 8-bit bi-directional CMOS I/O port with PMOS
as internal pull-up (Figure 6). Each pin of Port0 may be bit
programmed as an input or output port without the
software controlling the data direction register. When Port0
works as output, the data to be output is latched to the port
data register and output to the pin. Port0 pins that have '1's
written to them are pulled high by the internal PMOS pull-
P06, P07 are shared with VSYNCO & HSYNCO
respectively. If user sets ENH , ENV to low in SYNCON
register, P06, P07 will act as VSYNCO & HSYNCO
respectively (Figure 8). After the chip is reset, ENH , ENV ,
will enter high state and P06, BP07 will act as I/O pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0000
PT0
FFH
P07
P06
P05
P04
P03
P02
P01
P00
RW
$000B
SYNCON
FFH
NOHALF
ENHALF
-
FRUN
FRFREQ
HALFPO
L
ENH
ENV
W
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
PWM
Output
Vcc
PWM
Data In
Figure 7. PWM Output Structure
I/O
Vcc
Data Out
O/P
Data In
Data Out
Figure 6. I/O Structure
Figure 8. Output Structure
17
NT6861
11.2. Port1: P10 - P16
Port10-Port15 are 6-bit bi-directional CMOS I/O ports with
PMOS as the internal pull-up (Figure 6). Port16 is an input
pin only. Each bi-directional I/O pin may be bit
programmed as an input or output port without software
controlling the data direction register. When Port1 works
as output, the data to be output is latched to the port data
register and output to the pin. Port1 pins that have '1's
written to them are pulled high after reset.
P12, P13 are shared with half signals input and output pins
by accessing SYNCON control register. If user clears the
ENHALF bit to low, P13 will switch to HALFHI pin (input
pin) and P12 will switch to HALFHO pin
(output pin, Figure 8). Refer to half frequency function in
the H/V sync processor paragraph concerning HALFHI &
HALFHO pin. After the chip is reset, the ENHALF bits will
enter HIGH state and P12, P13 will act as I/O pins.
P10, P11 are shared with AD0 & AD1 input pins
P16 has a Schmitt Trigger input buffer (Figure 9) and is
shared with the external interrupt pin if set the IEINTE bit in
IEX control register. Refer to 'Interrupt Controller' section
above for function details.
respectively. If user clears the ENADX bit in the ENDAC
control register to low, A/D converters will activate
simultaneously. After the chip is reset, ENADX bits enter
HIGH state and P10, P11 act as I/O pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0001
PT1
7FH
-
P16
P15
P14
P13
P12
P11
P10
RW
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$000D
AD0 REG
C0H
CEND
AD05
AD04
AD03
AD02
AD01
AD00
R
W
CSTA
$000E
AD1 REG
00H
-
-
AD15
AD14
AD13
AD12
AD11
AD10
R
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
Vcc
Vcc
Data Out
.
I/P
Data OE
Data Input
Figure 9. Schmitt Input Structure
Data In
Figure 10. I/O Structure
18
I/O
NT6861
11.3. Port2: P20 - P27
Port2, an 8-bit bi-directional I/O port (Figure 10), which may be programmed as an input or output pin by the software control.
When setting the PT2DIR control bit to '0', its corresponding pin will act as output pin. Clearing PT2DIR bit to '1', acts as an
input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output, the data to be
output is latched to the port data register and output to the pin with push-pull structure. If programmed as an output pin, user
can read out its correspondent control bit about what user has written before. If programmed as an input pin, user can read out
what the I/O pin status outside. This port acts as an input port after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0002
PT2DIR
FFH
P27OE
P26OE
P25OE
P24OE
P23OE
P22OE
P21OE
P20OE
W
$0003
PT2
FFH
P27
P26
P25
P24
P23
P22
P21
P20
RW
11.4. Port3: P30 - P31
Port3 is an 2 bit bi-directional open-drain I/O port (Figure 11). Each pin of Port3 may be bit programmed as an input or output
pin with open drain structure. When Port3 works as an output, the data to be output is latched to the port data register and
output to the pin. For Port3 pins that have '1's written to them, user must connect PORT3 with external pulled-up resistor and
then PORT3 can be used as input (the input signal can be read). This port outputs high after reset .
P30, BP3 include Schmitt Trigger buffer for noise immunity and can be configured as the I2C pins SDA & SCL respectively. If
set ENDDC to LOW in IISTS control register, P30, P31 will act as SDA, SCL respectively. After the chip is reset, ENDDC will
be in HIGH and PORT3 will act as I/O pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0004
PT3
03H
-
-
-
-
-
-
P31
P30
$0015
II STS
0FH
-
-
START
START
STOP
STOP
ENDDC
TRX
RXAK
I/O
Data Out
Data In
Figure 11. Open Drain I/O Structure
19
RW
R
W
NT6861
12. H/V sync signals processor
The functions of the sync processor include polarity
detection, Hsync & Vsync signals counting, programmable
sync signals output, free running signal generator and
composite sync separation. The processor properly
handles either composite or separate sync signal inputs as
well as no sync signal input. The input at HSYNCI can be
either a pure horizontal sync signal or a composite sync
signal. For the sync waveform refer to Figures 12 and 13.
The sync processor block diagram is shown in
Figure 17. Both VSYNCI & HSYNCI pins have a Schmitt
Trigger and filtering process to improve noise immunity.
Any pulse that is shorter than 125ns will be regarded as a
glitch and will be ignored.
VCNTOV bit (in HVCON register) to HIGH (see Figure 14).
Once the VCNTOV sets to HIGH, it keeps in HIGH state
unless cleared by CLRVOV bit (in CLRFLG register) to
HIGH. When user clears the CLRVOV bit, the VCNT
counter will be reset to zero and begin to count again.
Hsync counter: HCNTL/H, the other 12-bit read only
register pairs contain the numbers of Hsync pulse between
two Vsync pulses (see Figure 15), and the data can be
read to determine if the frequency is valid and to determine
the VIDEO mode. If the HSEL bit sets to HIGH, the
internal counter counts the Hsync pulses between two
Vsync pulses. If the HSEL bit clears to LOW, the internal
counter will be reset and begin counting the Hsync pulses
in each 8.192ms interval (see Figure 16). The counted
value will be latched by the HCNTL/H register pairs which
are updated by every Vsync pulse or 8.192ms interval. If
the counter overflows, the HCNTOV bit (in HVCON
register) will be set to HIGH. Once the HCNTOV sets to
HIGH, it remains in the overflow HIGH state unless cleared
by CLRHOV (in CLRFLG register) to HIGH. When user
clears the CLRHOV bit, the HCNT counter will be reset to
zero.
12.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 12-bit read only register,
contains information of the Vsync frequency. An internal
counter counts the numbers of 8µs pulse between two
Vsync pulses. When the next Vsync signal is recognized,
the counter is stopped and the VCNT register latches the
counter value. The counted data can be converted to the
time duration between two successive Vsync pulses by
8µs. If no Vsync comes, the counter will overflow and set
(a) Positive polarity
(b) Negative polarity
Figure 12. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13. Composite H Sync. Waveform
20
NT6861
Latch VCNT register
Reset V sync. counter
Start pulse counting
Latch VCNT register
Reset V sync. counter
Start pulse counting
●
●
●
●
●
VSYNCI
Sampling Clock
●
8µ s
Figure 14. Vsync counter Operation
Latch HCNT register
Reset H sync. counter
Start pulse counting
Latch HCNT register
Reset H sync. counter
Start pulse counting
●
●
●
HSYNCI
●
●
VSYNCI
●
Figure 15. Hsync Counter Operation Using Vsync Pulse
Latch HCNT register
Reset H sync. counter
Start pulse counting
Latch HCNT register
Reset H sync. counter
Start pulse counting
●
●
●
●
HSYNCI
●
HSEL = Low
8.192 ms
●
Figure 16. Hsync Counter Operation Using 8.192ms Time Interval
21
NT6861
VCNTL
VCNTH
Control
Logic
V sync.
Latch
S/C
VSYNC
INPUT
Schmitt
Trigger
Digital
Filter
1
Enable
8 µs
V sync.
counter
V
Enable
Reset
HSEL
0
8.192 ms
0
Enable
1
HSYNC
INPUT
Schmitt
Trigger
Digital
Filter
Sync
Separator
H sync.
Latch
H&V
Sync.
Polarity
Detector
H
H sync.
counter
HPOLO
Reset
Enable
HCNTL
HCNTH
HPOLI
H Sync.
Output
Control
H
HSYNCO
FREE_RUN
Control
S/C
VPOLI
V
0
V
V Sync.
Output
Control
1
VPOLO
Figure 17. Sync. Processor Block Diagram
22
VSYNCO
NT6861
12.2. Sync Processor Control Register:
Composite sync: User has to determine whether the
incoming signal is separate sync or composite sync and
set S/ C & HSEL bit properly. If composite sync signal is
input, after set S/ C to '0', the sync separator block will be
activated ( please refer figure 18). During Vsync pulse the
Hsync will be inserted Hsync pulse by hardware circuit and
the pulse width of inserted pulse is 2µs fixed. According to
the last Hsync pulse outside the Vsync pulse duration, the
hardware will arrange the interval of these hardware
interpolated pulse. So the insertion of these Hsync pulse
will be continued inside the Vsync pulse duration no matter
what the Hsync pulse originally exist or not. These inserted
Hsync pulse have 0.5µs phase deviation maximum. The
Vsync pulse can be extracted by hardware from composite
signal, and the output of Vsync signal delay time will be
limited bellow 20ns. For inserting Hsync pulse safely, the
extracted Vsync pulse will be widen about 9µs. Because
evenly putting the Hsync pulse, the last inserted Hsync
pulse will have different frequency from original ones.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output which are shared with
P06 & P07 respectively. If set ENV & ENH to '0' in
SYNCON register, P06 & P07 will act as VSYNCO &
HSYNCO pin. When input sync is separate signal, the
V/HSYNCO will output the same signal as input sync
signal without delay. But if input sync is composite signal,
the VSYNCO signal will have a delay time of about 4µs to
8µs. The HSYNCO has no delay output and still has Vsync
pulse among Hsync pulse (i.e. the signal on HSYNCI pin
directly output to HSYNCO pin.)
Free run signal output: The user can set FRUN to '0' bit in
SYNCON register, then VSYNCO will output 61Hz Vsync
signal and HSYNCO will output 62.5KHz Hsync signal
default (Refer to Figure 20). When FRFREQ bit clears to
'0', the HSYNCO pin will output 41.7 KHz Hsync signal.
The free run signal has negative or positive polarity
depending on the HPOLO & VPOLO bit setting in the
HV_CON control register, '1' is positive and '0' is negative
System will not implement this insertion function, user
must clear INSEN bit in the MD_CON control register to
activate this function.
polarity. After chip reset, ENV , ENH , FRFREQ & FRUN
will enter HIGH state and P06 & P07 will act as I/O pins.
After reset, the HSEL , S/ C & INSEN bits default value is
HIGH and clear the VCNT | HCNT counter latches to zero.
Half frequency input and output: In this pin assignment,
when ENHALF sets to '0' in SYNCON register, the
HALFHO pin will act as an output pin and output half of
input signal in the HALFHI pin with 50% duty
Polarity: The detection of Hsync or Vsync polarity is
achieved by hardware circuits sample the sync signal's
voltage level periodically. The user can read HPOLI &
VPOLI bit in HVCON register, from which bit = '1'
representing positive polarity and '0', negative polarity. The
user can read HSYNCI and VSYNCI bit in HVCON register
to detect H & V sync input signal. The user can control the
polarity of H & V sync output signal by writing the
appropriate data to the HPOLO and VPOLO bits in the
HVCON register, '1' represents positive polarity and '0',
negative polarity.
(Refer to Figure 21). If NOHALF sets to '0', HALFHO will
output the same signal in the HALFHI pin and user can
control its polarity output of HALFHO by setting HALFPOL
bit, '1' for positive and '0' for negative polarity. After chip
reset, ENHALF , NOHALF & HALFPOL will be in the
HIGH state and P13 & P17 will act as I/O pins.
23
NT6861
●
(1) HSYNCI
●
●
●
●
Composite H sync. waveform (H EOR V)
●
(2) HSYNCI
Composite H sync. waveform (H OR V)
No matter Hsync pulse existing or not,
the output signal of Hsync will be inserted.
2µs
HSYNCO
●
●
●
Original
Hsync Pulse
Original
Hsync Pulse
Inserted Hsync Pulse
VSYNCO
Widen 9 µs
Figure 18. Composite H & V Sync. Processing
24
NT6861
Sync. Mode
Processing
Set S/C = '0'
Clear VCNTOV & HCNTOV
Open INTV & clear INTV flag
System Default:
S/C = '1' & HSEL = '1'
Open INTV & clear INTV flag
Freq.
Calculating
Set S/C = '1' & HSEL = '0'
Clear VCNTOV & HCNTOV Delay 10ms
No
INTV ?
Delay 60ms
Yes
Yes
HCNTH = '00'
?
Delay 31 ms
No
Yes
Suspend Mode
Yes
VCNTOV = '1'
?
Off Mode
1. Extract VCNTL/H 12 bit data
2. HSEL = '1'
12 bit data X 8µ s
= Vsync. time duration
3. Its reciprocal
is Vsync. freq.
4. HSEL = '0'
12 bit data X 8.192ms
= Vsync. freq.
VCNTOV = '1'
?
No
STAND-BY Mode
No
Yes
HCNTH = '00'
?
HCNTH ='00'
?
NORMAL Mode
Seperate Sync.
No
Yes
Worng Mode
1. Extract HCNTL/H 12 bit data
2. 12 bit data * Vsync. freq.
= Hsync. freq.
3. Its reciprocal
is Hsync. time duration.
No
Read VCNT|HCNT
Counter Register
Read VCNT|HCNT
Counter Register
Return
Freq.
Calculating
NORMAL Mode
Composite Sync.
Return
Figure 19. H & V Sync. Software Control Flowchart (for reference only)
25
NT6861
61Hz
(1) 62.5KHz
Pulse width 64 µ s
(a) Free run output Vsync. signal
(2) 41.7KHz
Pulse width 1µ s
(b) Option 2 of free run output Hsync. signal
Figure 20. Free Running Sync. Waveform
HALFHI
HALFHO: Half freq. output signal (50% duty)
HALFHO output signal when NOHALF bit clears to LOW
(the same signal as in the HALFHI pin)
Figure 21. Half Freq. Sync. Waveform
26
NT6861
12.3. Power Saving mode detect:
The VIDEO mode is listed below. Power saving is from mode 2 to mode 4. All modes can be detected by setting the control
register properly. Refer to Figure 15 control flow chart for software reference.
Mode
(1) Normal
(2) Stand by
(3) Suspend
(4) Off
H-Sync
Active
Inactive
Active
Inactive
V-Sync
Active
Active
Inactive
Inactive
Control bit description:
Addr.
$0005
$0006
Register
MD CON
HV CON
INIT
07H
2FH
Bit7
-
Bit6
-
Bit5
-
Bit4
-
Bit3
-
Bit2
-
Bit1
Bit0
S/ C
MD1/ 2
INSEN
HSEL
S/ C
MD1/ 2
HCNTOV
VCNTOV
HSYNCI
VSYNCI
HPOLI
VPOLI
VPOLO
HCL0
R
W
R
R
W
$0007
HCNT L
00H
HCL7
HCL6
HCL5
HCL4
HCL3
HCL2
HPOLO
HCL1
$0008
HCNT H
00H
-
-
-
-
HCH3
HCH2
HCH1
HCH0
R
$0009
$000
A
$000
B
VCNT L
VCNT H
00H
00H
VCL7
-
VCL6
-
VCL5
-
VCL4
-
VCL3
VCH3
VCL2
VCH2
VCL1
VCH1
VCL0
VCH0
R
R
SYNCON
FFH
NOHALF
ENHALF
-
FRUN
FRFREQ
HALFPOL
ENH
ENV
W
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0011
MDCON control register:
HSYNCI & VSYNCI: User can instantaneously detect
input of H & V Sync pulse at any
time.
HPOLI & VPOLI: The polarity of input H & V Sync pulse
- '1' for positive polarity and '0' for
negative polarity.
HPOLO & VPOLO: To control the output polarity of H & V
Sync pulse - '1' for positive polarity
and '0' for negative polarity.
S/ C : The SYNC MODE control. If the input of V & H
Sync are separate signals, set this bit to
'1' (system default). If the input is composite
signal, clear this bit. Under the COMPOSITE mode,
NT6861 will extract the V Sync form H Sync
signal.
HSEL : When clearing this bit, system will reset
HCNTL|H counter to zero. The number of Hsync
pulse at the 8.192ms interval is obtained.
INSEN : User can clear this bit for inserting Hsync pulse
when processing the composite signal. System
will disable this function after reset.
HCNTL|H & VCNTL|H control registers:
The 12 bits counter for H & V Sync pulse.
SYNCON control register:
ENH & ENV : Enable the output of H & V Sync. The P06
& P07 will switch to VSYNCO & HSYNCO
output.
HVCON control register:
HCNTOV: The overflow bit of H Sync. After setting HSEL
bit '1' without any input Vsync pulses and
there are more than 4096 Hsync pulses
coming ,this bit will be set. It will keep '1' and
user can clears it by setting CLRHOV bit to '1'
at the CLRFLG control register. After cleared,
the H Sync counter will reset to '0' and start
counting for every Hsync pulse.
VCNTOV: The overflow bit of V Sync. The operation is
the same as HCNTOV. After cleared, the
Vsync counter will reset to '0' and start
counting for every 8µs.
FRUN : Open free run signal at the VSYNCO & HSYNCO
output.
FRFREQ : Select the free run frequency of H Sync
output.
ENHALF : P12 & P13 will switch to HALFHO & HALFHI
pin. The HALFHO will output the half signal at
the HALFHI pin with 50% duty.
NOHALF : User must clear ENHALF first. The HALFHO
will output the same signal at the HALFHI pin.
27
NT6861
positive polarity and '0' for negative polarity.
HALFPOL: User must clear ENHALF first and control the
polarity at the HALFHO output pin - '1' for
28
NT6861
13. BASE TIMER (BT)
The Base Timer is an 8-bit counter whose clock source must be chosen with 1µs or 1ms by setting or clearing the TBS bit
('0' for 1µs and '1' for 1ms). The BT can be enabled/disabled by the ENBT bit in the BTCON register. When user clearing this
control bit to '0', the BT will start counting, otherwise setting this bit to '1' will stop the counting. After chip is reset, the TBS and
ENBT bits are set to '1' (the BT is disabled). BT, can be preset by writing BT7 - BT0 to the BT register (write only) at any time
and the BT will start count-up from preset value. When the value reaches FFH, it generates a timer interrupt if the timer
interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and begin counting at 00H.
The timer interval can be within 256 ms maximum if set TBS to '1'. The timer interval can be within 256µs maximum if set TBS
to '0'.
1µs
0
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
TMR INT
1
1ms
TBS
Control bit description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0016
BT
00H
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
$0017
BT CON
03H
-
-
-
-
-
-
TBS
ENBT
W
BT control register :
BT0 - BT7: Preloaded value of the base timer. The timer will count-up from this value.
BTCON control register:
ENBT : When clearing this bit, the base timer will be activated.
TBS: Select the input clock source of base timer - '1' for 1ms and '0' for 1µs.
29
NT6861
14. I2C bus interface: DDC1 & DDC2B Slave Mode
I2C bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication between
devices. Its structure minimizes the cost of connecting various peripheral devices. In short, the wired-AND connection of all I 2C
interface to I2C bus is the most important structure. Two modes of operation have been implemented in NT6861: UNIDIRECTIONAL mode (DDC1 mode) and BI-DIRECTIONAL mode (DDC2B mode). If the MD1/2 bit is set to '1', the device will
operate in the DDC1 mode, and if the MD 1/2 bit is cleared to '0', the device will operate in the DDC2B mode. All of these I 2C
functions will be activated only when ENDDC bit clears to '0' (in IISTS register). When I2C bus
function is activated, the P30 & P31 will switch to SCL & SDA pin. System works on the DDC1 mode transmission default. The
SCL pin will remain high and SDA will transfer one bit of data at every rising edge of Vsync pulse.
SDA
Shift Register (IIDAT)
clock source
0
SCL
1
VSYNC
MD1/2
14.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 data transfer, the
Vsync input pin is used as an input clock for data
transmission and SDA output pin, as serial data line. This
function comprises of two data buffers: one is a preloaded
data buffer for user placing one bit of data in advance, and
one is shift register for system shifting out one bit of data to
the SDA pin. These two data buffer cooperate properly.
Refer to Figure 18. After system reset, the I2C bus interface
is in DDC1 mode.
out MSB bit and generate an INTD interrupt to remind user
to replace next byte data into IIDAT register. After eight
rising clocks, there are eight bits shifted out in proper order
and the shift register becomes empty again. At the ninth
rising clock, it will shift the ninth bit (null bit '1') out to SDA.
And on the next rising edge of Vsync clock, system will
generate a INTD interrupt again. NT6861 will also load
new data in the IIDAT register to internal shift register and
shift out one bit immediately. User must input new data to
IIDAT register properly before the shift register is empty
(the next INTD interrupt).
Data transfer: In advance, put one byte transmitted data
into IIDAT register and activate I2C bus by setting ENDDC
bit to '0' and open INTD interrupt source by setting IEINTD
to '1'. On the first 9 rising edge of Vsync, system will shift
out any invalid bit in shift register to SDA pin to empty shift
register. When shift register is empty and on next rising
edge of Vsync, it will load data in the IIDAT register to
internal shift register. At the same time, NT6861 will shift
Vsync clock: In the separate sync signal, the Vsync pulse
is used as a data transfer clock. Its frequency allows
25KHz maximum. If no Vsync input signal is found,
NT6861 can not transmit any data to SDA pin regardless
what the Vsync has extracted from composite Hsync
signal.
30
NT6861
Control bit description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
$0005
MD CON
07H
-
-
-
-
-
-
IEINTS
IEINTD
IEINTA
$000F
Bit2
Bit1
Bit0
-
-
S/ C
MD1/ 2
R
INSEN
HSEL
S/ C
MD1/ 2
W
IEINTR
IEINTE
IEINTV
W
IEX
00H
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0014
II DAT
00H
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RW
$0015
II STS
08H
-
-
START
START
STOP
STOP
RXAK
ENDDC
TRX
TXAK
R
W
MDCON control register:
MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default.
When transmission mode is changed form DDC1 to DDC2B, system automatically clears this bit.
IEX control register:
At DDC1 mode, only open INTD interrupt, as well as open INTS interrupt to detect if has changed to DDC2B mode.
II_DAT control register: Data buffer for transmission.
II_STS control register:
ENDDC : When clearing this bit, system will activate DDC transmission. P30 & P31 will switch to SDA & SCL pin.
ENDDC
(in IISTS register)
Vsync Pulse
●
1
2
3
●
●
9
4
●
INTV
●
1
2
3
4
5
6
7
8
9
1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
2
●
Load data in the IIDAT register to shift register
INTD
User can load next byte data to IIDAT register
SDA
Invalid data
●
●
8
●
7
6
5
●
●
●
1
Null
Bit
8
7
6
5
4
3
Second Byte Data
Shift
register
8
MSB
7
6
5
4
3
2
1
LSB
First Byte Data
Figure 22. DDC1 Mode Timing Diagram
31
2
1
Null
Bit
8
7
NT6861
14.2 DDC2B Slave Mode bus interface
The DDC2B I2C Bus Interface features are as follows:
- SLAVE mode (NT6861 addressed by a master
which drive SCL signal)
- Fully compatible with I2C bus standard
- Interrupt and generation of acknowledge handled by
user for communication
- Interrupt driven byte by byte data transfer
- Calling address identification interrupt
- Detection of START and STOP signals
occurs, NT6861 will remind user by generating a INTS
interrupt and switch to DDC2B mode automatically. When
user sets MD1/2 to '1' at this time, the NT6861 will still
proceed with a DDC1 communication. The DDC2B bus
consists of two wires, SCL and SDA; SCL is for the data
transmission clock and SDA is for the data line. Data
transfers follow the format shown in Figure 19. The
standard communication of I2C bus protocol includes four
parts: a START signal, slave ADDRESS, transferred data
(proceed byte by byte) and a STOP signal. In the wiredAND connection, any slow devices can hold the SCL line
LOW to force the fast device into a wait state until the slow
device is ready for the next bit or byte transfer in a type of
handshake procedure.
Enable I2C and INTS: The NT6861 included the use in
applications requiring storage and serial transmission of
configuration and control information. User can place
address data into IIADR register and set IEINTS to '1' (in
IEX register) in advance. In the DDC1 mode (after clearing
ENDDC to '0') and when the low level on the SCL pin
STOP
CONDITION
START
CONDITION
SDA
●
8
MSB
●
●
8
9
ADDRESS
R/W
ACK
SCL
IIDAT Reg.
bit stream
●
1-7
7
6
5
4
●
1
●
●
LSB
●
●
●
1-7
8
9
DATA
ACK
8
ACK
7
6
5
●
●
1-7
4
MSB
8
9
DATA
3
2
ACK
1
LSB
Figure 23. DDC2B Data Transfer
32
ACK
8
MSB
7
●
●
●
NT6861
Start condition: When SCL & SDA lines are in HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is in high state). When there is a
START condition, NT6861 will set the 'START' bit to '1'
and user can poll this status bit to control DDC2B
transmission at any time. This bit will keep '1' until user
clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send
start conditions without sending a STOP signal to
terminate this communication. This is used by the external
device to communicate with another slave or with the same
slave in different mode (READ or WRITE mode) without
releasing the bus.
Data validity and transfer: The data on the SDA line mu be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. If a receiver (external device or NT6861)
cannot receive another complete byte of data until it has
performed some other function, for example servicing an
internal interrupt, it can hold the clock line SCL LOW to
force the transmitter into a wait state. Data transfer then
continues when the receiver is ready for another byte of
data and release clock line SCL. Each byte data is followed
by an acknowledge bit.
Address matched and INTA: After the START condition, a
slave address is sent by external device. When I2C bus
interface changes to DDC2B mode, NT6861 will first act
as a receiver to receive this one byte data. This address
data is 7 bits long followed by the eighth bit that indicates
Acknowledge: The acknowledgment will be generated at
ninth clock by whom receive data. In the WRITE mode,
NT6861 system must respond to this acknowledgment.
After receiving one byte data from external device, NT6861
will automatically send an acknowledgment by pulling SDA
line to 'LOW'. In the READ MODE, external device must
respond to this acknowledgment and at every byte data
sent, user can read RXAK bit in IISTS register to check if
external sent a ACK or not.
the data transfer direction (R/W ). When NT6861 system
receives address data from external device, it will store if in
IIDAT register. System support 'A0' address by default
and another one set of DDC2 address for user. When user
enable DDC2 function, the system will compare address
data getting from external device with the default address
'A0' and data in the $0013 II_ADR control register written
by user. Either of these address matched, the system will
generate an INTA interrupt flag and this DDC2
communication will be continued. If user sets IEINTA bit to
'1' in advanced and address data matched, the NT6861
system will generate a INTA interrupt. Under the address
matching condition, the NT6861 will send an
acknowledgment to external device. If address data not
matched, the NT6861 will not generate INTA interrupt and
not care the data change on SDA line in the future.
The INTD interrupt: After NT6861 receive the START
condition, it will generate an INTD interrupt at the falling
edge of the ninth clock. User can control the flow of
DDC2B transmission at this INTD interrupt.
The INTD on the WRITE mode: NT6861 read data from
external device. At INTD interrupt, the SCL will be hold
LOW by NT6861. When getting one byte data from II_DAT
register, user can write '00' into II_DAT register and the
SCL will be released. External device can continue
sending next byte data to NT6861. Refer to Figure 24.
The INTD on the READ mode: External device read data
from NT6861. At INTD interrupt, the SCL will be hold LOW
by NT6861. User can check RXACK bit in the IISTS
register whether external device has sent an ACK or not
after one byte data transfer. If external device has sent an
ACK, the RXACK will be '0' (assume the acknowledgment
is LOW signal). When user puts one new byte data into
II_DAT register, the SCL will be released for generation of
SCL transmission clock. The next byte data will be shifted
out
properly.
Refer
to
Figure 25.
Data Transmission direction: At INTA interrupt servicing
routine, user must check the LSB of address data in IIDAT
register. According to I2C bus protocol, this bit indicates the
DDC2B data transfer direction in later transmission - a '1'
indicates a request for 'READ MODE' action (external read
data from system); a '0' indicates a 'WRITE MODE' action
(external write data to system). For READ mode and
WRITE mode timing diagram refer to Figure 24 and 25.
The data transfer can be proceeded byte by byte in a
direction specified by the R/ W bit after a successful slave
address is received. User must set TRX bit in the IISTS
register for NT6861 transmission mode - '1' for READ
mode and '0' for WRITE mode.
33
NT6861
STOP condition: When SCL & SDA lines have been
released (remain in 'HIGH' state), DDC2B data transfer is
always terminated by a STOP condition generated by
external device. A STOP signal is defined as a low to high
transition of SDA while SCL is in HIGH state. When there is
a STOP condition, NT6861 will set the 'STOP' bit to '1' and
user can poll this status bit to control DDC2B transmission
at any time. This bit keeps '1' until user clears it. Notice the
SCL and SDA lines must conform to I2C bus specifications.
(Refer to Figure 26). Refer to the standard I2C bus
specification for details.
Changing to DDC1 mode: After an external device
terminates DDC2 transmission, set MDI/ 2 to 1 for
changing to DCC1 mode. When the SCL line has been
released (pulled-up), user can force NT6861 to DDC1
mode communication at any time. This function is
supporting the 'error' recovery protocol in the VESA DDC
standard Ver 2.0.
Control bit description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005
MD CON
07H
-
-
-
-
-
-
S/ C
MD1/ 2
R
INSEN
HSEL
S/ C
MD1/ 2
W
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0013
II ADR
FFH
AR7
AR6
AR5
AR4
AR3
AR2
AR1
-
W
$0014
II DAT
00H
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RW
$0015
II STS
08H
-
-
START
START
STOP
STOP
RXAK
-
ENDDC
TRX
R
W
MDCON control register:
II_ADR control register: User can define the address of
DDC2B device. If an external
device sends the same address
data as this control register
(calling
NT6861),
NT6861
will generate an INTA interrupt.
MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for
DDC2B mode. System will be DDC1 mode by
default.
When transmission mode is changed form
DDC1 to DDC2B, system will automatically clear
this bit.
II_STS control register:
IEX control register:
ENDDC : When clearing this bit, the system will activate
DDC transmission. P30 and P31 will switch to
SDA and SCL pin.
TRX: In the READ mode of DDC2B transmission, user
must set this bit '1'.
RXAK: In the WRITE mode of DDC2B transmission, after
one byte has been sent out to the SDA line,
there will be an INTD interrupt. At INTD interrupt
service routine, user can check this bit to see if
external device has responded to NT6861.
In DDC2 mode, user use INTS, INTA & INTD interrupt and
II_STS control register to control DDC2B transmission.
II_DAT control register: Data buffer for transmission
34
NT6861
S
NT6861 Address
R/W
A
DATA
A
DATA
A
P
Data transferred
from external device
0
From external device to NT6861
A = acknowledge
S = START
P = STOP
From NT6861 to external device
(a) WRITE_Mode Data Format
wait
wait
wait
wait
SCL
R/W
START
SDA
(external device)
1
0
1
0
0
0
0
STOP
0
DATA
DATA
INTS
INTA
INTD
SDA
(NT6861)
A
A
(b) WRITE_Mode timing Diagram
Figure 24. DDC2B Write_Mode Spec.
35
A
NT6861
S
NT6861 Address
R/W
A
DATA
A
DATA
A
P
Data transferred
from external device
1
From external device to NT6861
A = acknowledge
A = no acknowledge
S = START
P = STOP
From NT6861 to external device
(a) Read_Mode Data Format
wait
wait
wait
wait
SCL
R/W
START
SDA
(external device)
1
0
1
0
0
0
0
STOP
1
A
A
INTS
INTA
INTD
SDA
(NT6861)
A
DATA
(b) READ_Mode timing Diagram
Figure 25. DDC2B Read_Mode Spec.
36
DATA
NT6861
Interrupt Service Routine
Polling
Main Program
Need
Polling
INTS ?
No
Need
Polling
INTD ?
Need
Polling
INTA ?
No
DDC2
yes
Change To
DDC2 Mode
MD 1/2 = 0
(Auto Switch)
No
yes
yes
DDC1
Transfer ?
Put Addr.
Into
IIADR Reg.
From EDID
Buffer Index
Put One Byte
Data Into
IIDAT Reg.
Setting IISTS:
TRX = 0
(Recv. Mode)
No
INTA ?
INTD ?
yes
Wait Interrupt
or
Doing something
Need
Polling
INTV ?
Need
Polling
INTR ?
No
yes
No
INTS ?
Set ENDDC = 0
No
yes
yes
yes
Open
INTV & INTS
No
No
INTV ?
yes
No
DDC2B
Write_Mode
Operation
?
yes
Reset EDID Buffer Index
From IIDAT Reg.
LSB
To Decide
Write/Read Mode
No
DDC2B
Read_Mode
Operation
Read One Byte
Data From
IIDAT Reg.
To Set EDID
Buffer Index
From EDID
Buffer Index
Put One Byte
Data Into
IIDAT Reg.
Write '00'
To IIDAT
For releasing SCL
DDC1
DDC2B
Write_Mode
Operation
?
yes
Setting IISTS:
TRX = 0
(Recv. Mode)
No
INTR ?
yes
yes
Change To
DDC1 Mode
MD_CON = 1
Reset EDID
Buffer Index
Put One Byte
Data Into
IIDAT Reg.
No
Setting IISTS:
TRX = 1
(Trans. Mode)
Other INT.
Service
Open
INTS & INTD
NO
DDC2 Idle
For 2 Sec. ?
No
Open
INTA & INTR
Open
INTS & INTD
DDC2 Operate
Over ?
Write '00'
To IIDAT
For releasing SCL
yes
Reset EDID
Buffer Index
Open
INTA & INTD
Open
INTA & INTD
Open
INTA & INTV
Return
Figure 26. DDC1/2B Software Flow Chart
37
Put First Byte
Data Into
IIDAT Reg.
For releaseing SCL
& For Transfer data
yes
Return To
DDC1 Mode
Open INTV
NT6861
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposed to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Supply Voltage VDD - VSS . . . . . . . . . . . . . .-0.3V to 7V
Input Voltage . . . . . . . . . . . . . . . GND -0.2V to VCC +0.2V
Operating Temperature . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . -50°C to +125°C
DC Electrical Characteristics (VDD = 5V, TA = 25°C, oscillator freq. = 8MHz, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
20
mA
Conditions
IDD
Operating Current
VIH1
Input High Voltage
2
V
P00 - P07, P10-P16, P20-P27, P30, P31,
RESET , VSYNCI, HSYNCI, HALFHI, INTE
VIH2
Input High Voltage
3
V
SCL, SDA pins
VIL1
Input Low Voltage
0.8
V
P00 - P07, P10 - P16, P20 - P27, P30, P31,
RESET , VSYNCI, HSYNCI, HALFHI, INTE
VIL2
Input Low Voltage
1.5
V
SCL, SDA pins
IIH
Input High Current
-350
µA
VOH1
Output High Voltage
VOH2
Output High Voltage (DAC8 - DAC13)
VOH3
-200
2.4
No loading
P00 - P07, P10 - P16 ,P20 -P27, VSYNCI,
HSYNCI, HALFHI, RESET (VIH = 2.4V)
V
P00 - P07, P10 - P15 (IOH = -100µA)
VSYNCO, HSYNCO (I OH = -4mA)
HALFHO (I OH = -4mA)
P20-P27 (IOH = -10mA)
5
V
external applied voltage
Output High Voltage (DAC0 - DAC7)
12
V
external applied voltage
VOL
Output Low Voltage
0.4
V
P00 - P07, P10 - P15, DAC0 - 13 (I OL = 4mA)
SCL/P30, SDA/P31 (IOL = 5mA)
VSYNCO, HSYNCO (I OL = 4mA)
HALFHO (I OL = 4mA)
P20 - P27 (IOL = 10mA)
ROL
Pull Down Resistor ( RESET )
25K
50K
75K
Ω
ROH1
Pull Up Resistor (INTE)
11K
22K
33K
Ω
ROH2
Pull Up Resistor (PORT0 & PORT1)
11K
22K
33K
Ω
ROH3
Pull Up Resistor (HSYNCI & VSYNCI)
11K
22K
33K
Ω
38
NT6861
AC Electrical Characteristics(VDD = 5V, T A = 25°C, oscillator freq. = 8MHz, unless otherwise specified)
Symbol
Parameter
Fsys
System Clock
tC N V T
A/D Conversion time
Voffset
A/D Converter Offset Error
Vlinear
A/D Input Dynamic Range of Linearity
conversion
Min.
Typ.
Max.
8
0.3
Unit
Condition
MHz
375
µs
39
mV
0.7
VD D
2
µs
Composite sync
(Refer Figure 18)
ns
Composite mode &
insertion function activated
tinst
The inserted Hsync pulse width
tdev
The time deviation at the end edge of
inserted Hsync pulse
tR E S E T
Reset Pulse Width Low
2
Fvsync
Vsync Input Frequency
32
25K
Hz
tVPW
Vsync Input Pulse Width
8
300
µs
Fhsync
Hsync Input Frequency
30
120
KHz
tHPW1
Hsync Input Pulse Width High
0.5
7
µs
tHPW2
Hsync Input Pulse Width Low
8
250
Vin = 2V for A/D converter
tCYCLE
tCYCLE = 2/Fsys
tVSYNC = 1/Fvsync
tHSYNC = 1/Fhsync
µs
Composite sync
tERROR1
Counting Deviation of Base Timer
1
µs
1µs clock source
tERROR2
Counting Deviation of Base Timer
1
ms
1ms clock source
39
NT6861
DDC1 Mode
Symbol
tVPW
Fvsync
tDD
tMODE
Parameter
Min.
Typ.
Max.
Unit
Vsync high time
0.5
300
us
Vsync Input Frequency
32
25K
Hz
200
500
ns
500
ns
Data valid
Time for transition to DDC2B
mode
Condition
tVSYNC = 1/Fvsync
SCL
tMODE
tDD
SDA
Bit 0
Null Bit
Bit 7
VSYNC
tVPW
Composite
Hsync Input
● ● ●
t HPW2
tHPW1
Extracted
Vsync Output
(no loading)
40
Bit 6
NT6861
DDC2B Mode
Symbol
fSCL
tBUF
tHD; STA
Parameter
Min.
Typ.
SCL Clock Frequency
Bus Free Between a STOP and START Condition
Hold Time for START Condition
Max.
Unit
100
KHz
4.7
µs
4
µs
tLOW
LOW Period of the SCL Clock
4.7
µs
tHIGH
HIGH Period of the SCL Clock
4
µs
tSU; STA
Set-up Time for a Repeated START Condition
4.7
µs
tHD; DAT
Data Hold Time
300
ns
tSU; DAT
Data Set-up Time
300
ns
tR
Rise Time of Both SDA and SCL Signals
1
µs
tF
Fall Time of Both SDA and SCL Signals
300
ns
tSU; STO
SDA
Set-up Time for STOP Condition
µs
4
tBUF
tLOW
tR
tF
tHD ; ST A
SCL
tHD; STA
tHD; DAT
tSU; ST A
tSU; DAT
tSU; ST O
tHIGH
STOP
START
START
41
STOP
NT6861
Ordering Information
Part No.
Package
NT6861
40L DIP
NT6861U
42L S-DIP
42
NT6861
Package Information
DIP 40L Outline Dimensions
unit: inches/mm
D
21
E1
40
1
20
E
A1
A2
Base Plane
L
A
C
S
Seating Plane
B
B1
α
e1
Symbol
Dimensions in inches
Dimensions in mm
A
0.210 Max.
5.33 Max.
A1
0.010 Min.
0.25 Min.
A2
0.155±0.010
3.94±0.25
B
0.018 +0.004
-0.002
0.46 +0.10
-0.05
B1
0.050 +0.004
-0.002
1.27 +0.10
-0.05
C
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
2.055 Typ. (2.075 Max.)
52.20 Typ. (52.71 Max.)
E
0.600±0.010
15.24±0.25
E1
0.550 Typ. (0.562 Max.)
13.97 Typ. (14.27 Max.)
e1
0.100±0.010
2.54±0.25
L
0.130±0.010
3.30±0.25
α
0° ~ 15°
0° ~ 15°
eA
0.655±0.035
16.64±0.89
S
0.093 Max.
2.36 Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
43
eA
NT6861
Package Information
S-DIP 42L Outline Dimensions
unit: inches/mm
D
42
22
E
pin 1 index
1
21
ME
A1
A2
Base Plane
Seating Plane
L
A
C
Z
e1
b1
b
MH
e
Symbol
Dimensions in inches
Dimensions in mm
A
0.200 Max.
5.08 Max.
A1
0.020 Min.
0.51 Min.
A2
0.157 Max.
4.0 Max.
b
0.051 Max.
0.031 Min.
1.3 Max.
0.8 Min.
b1
0.021 Max.
0.016 Min.
0.53 Max.
0.40 Min.
c
0.013 Max.
0.010 Min.
0.32 Max.
0.23 Min.
D(1)
1.531 Max.
1.512 Min.
38.9 Max.
38.4 Min.
E(1)
0.551 Max.
14.0 Max.
0.539 Min.
13.7 Min.
1.778
e
0.070
e1
0.600
15.24
L
0.126 Max.
3.2 Max.
0.114 Min.
2.9 Min.
ME
0.622 Max.
0.600 Min.
15.80 Max.
15.24 Min.
MH
0.675 Max.
17.15 Max.
0.626 Min.
15.90 Min.
w
0.007
0.18
Z(1)
0.068 Max.
1.73 Max.
Notes:
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
44