OZ965 High-Efficiency Inverter Controller FEATURES • • • • • • • • • • dimming function with an analog voltage or low frequency Pulse Width Modulation (PWM) control. Single-stage power conversion, requiring only a +5 V voltage source Reduces the number of components and board size by 30% compared with conventional design Supports both floating and grounded secondary designs 90% efficiency vs. typical 75% efficiency of conventional designs Internal open-lamp and short-circuit protections Wide dimming range Supports multiple CCFLs Simple and reliable 2-winding transformer design Eliminates leakage current when used in a floating secondary design Constant-frequency design eliminates interference with LCDs Operating Principle: The CCFL tube, transformer secondary, and capacitor form a resonant circuit. The OZ965 utilizes the low energy loss resonate mode principle to deliver a very high efficiency inverter. The OZ965 drives the transformer primary with a variable pulse width voltage directly from the +5v supply. The resultant primary drive current is alternately reversing with zero-voltage-switching. Because of the transformer leakage inductance and the secondary resonant circuit, the secondary voltage and current are approximately sinusoidal. This sinusoid results in very little harmonic emi/rfi emissions. The OZ965 operates at a single, constant frequency in a PWM mode. Typical operating frequency ranges between 30 KHz to 200 KHz, dependent upon the CCFL and transformer characteristics. Intelligent open-lamp protection provides design flexibility so various transformer models/manufacturers may be used. ORDERING INFORMATION OZ965G - 16-pin plastic SOP OZ965R - 16-pin plastic TSSOP OZ965IG - 16-pin plastic SOP OZ965IR - 16-pin plastic TSSOP GENERAL DESCRIPTION Its high driving capability allows the OZ965 to drive high power MOSFETs. The OZ965 is a single chip, high-efficiency, Cold Cathode Fluorescent Lamp (CCFL) backlight inverter controller whose primary function is to convert +5 volt DC power to approximately 600 VAC. Additionally, the OZ965 performs the lamp The single stage design results in a low cost, reliable transformer without expensive, less reliable secondary fold-back treatment. The transformer does not require a more expensive center tapped primary. Figure 1. Typical Application Circuit The OZ965 is available in 16-pin SOP and TSSOP packages. It is specified over the commercial temperature range of 0°C to +70°C, and the industrial temperature range of -40°C to +85°C. J1 1 2 3 4 5 6 C2 22u 100k R1 C1 0.1u R2 22 R3 150k C3 10u R4 20k C4 0.1u R5 15k C5 OZ965 C8 0.1u VDD RT CT OPS ENA NDR PDR SST 16 15 14 13 12 11 10 9 U2 2 1 470p C6 8 7 68p 3kv 5 HV RTN 6 T1 Q1 4 3 J2 1 2 7 17:2200 C7 10u 6 5 Q2 C10 2.2u Si4532 3 C9 0.01u REF HCLMP LCLMP SCP ADJ FB CMP GND 2 R6 59.0k U1 1 2 3 4 5 6 7 8 2 C11 0.1u CR3 BAV99L R13 510k R15 4.3k 1 5V 5V ENA DIM GND GND R16 100k C12 0.1u 06/20/00 Copyright 2000 by O2Micro R17 1.02k OZ965-SF-3.0 All Rights Reserved Page 1 U.S. Patent #5,619,402 OZ965 “Soft start” gradually increases the energy delivered to the secondary. FUNCTIONAL BLOCK DIAGRAM When the OZ965 is enabled at pin ENA, the capacitor on pin SST determines the duration of the “soft-start” period, gradually increasing the NDR pulse width to the regulated brightness. The “soft-start” period provides sufficient time for the lamp to ignite. Refer to the functional block diagram in Figure 2, below, and the Pin Description Table on page 3. Power is transferred to the transformer primary by the N-MOSFET, driven by the MOSFET gate driver out of pin NDR. The P-MOSFET resets the primary field, driven by pin PDR. The usual design results in approximately 50% duty cycle at full lamp intensity. Terminating the NDR signal earlier than the full brightness lamp pulse width performs lamp dimming, using the analog dimming. The voltages on pins HCLMP and LCLMP set a threshold voltage for the ramp comparator setting the maximum duty cycle for NDR. For system reliability there are several circuit protections provided. To ensure a controlled output, the secondary current is monitored on pin FB and is compared to a reference voltage on pin ADJ. The NDR signal is shortened or lengthened dependent upon this feedback. Protection is provided by the resultant signal, CMP, monitoring for a lamp removal condition. Short circuit protection is provided at pin SCP. The OPS signal selects either HCLMP or LCLMP providing current protection against an “Open Lamp” condition at start-up. The OPS signal also allows adjustment to different transformer models. A pulse generator circuit creates the clock signal with the frequency determined by an external, constant current setting resistor (RT) and timing capacitor (CT). To reduce power dissipation, the switch (MOSFET) drive signals are “break-before-make” with a short, fixed off time between activation of NDR or PDR. The “soft-start” circuit ensures a reliable and long lamp life starting condition. Vdd 16 REF 1 IBIAS & REFERENCE 2.50V POFF HCLMP Vset + Vmax=2.6V-Vset - RT + Vmax RAMP COMP. V>Vmax -- -> Vmax Vmin<V<Vmax ->V V<Vmin -- ->Vmin V LCLMP 15 - RAMP COMP. PULSE 2 3 Vmin (fix value) + COMP PULSE GEN CT + COMP SCP - 14 0.5V CLK 4 2.5V + COMP - ADJ Vdd 0.6V LAMP ON/OFF OPS 13 5 RESET + - UNDER VOLTAGE SS1 EA UVLO LOCKOUT ENA + ENABLE FB 12 COMP t1 6 R1 300k - (slow start) ACTIVE "HIGH" 1.5V ZVS CONTROLLER PDR CMP 11 7 Pgate PDRV Ngate NDRV R4 70k NDR + R5 630k OLPROT PROTECTION 10 SS2 POFF 2.5V COMP I=12uA I=2.5uA GND SST SS1 t1+t2 8 V_SS2 (slow start) 9 R2 4K Note: OVP – Over Voltage Protection SCP – Short-Circuit Protection UVL – Under Voltage Lockout POFF MN1 Figure 2. Functional Block Diagram OZ965-SF-3.0 Page 2 OZ965 PIN DESCRIPTION Names REF HCLMP LCLMP SCP ADJ FB CMP GND SST Pin No. 1 2 3 4 5 6 7 8 9 I/O O I I I I I O GND I PDR NDR ENA OPS CT RT VDD 10 11 12 13 14 15 16 O O I I I/O I/O PWR Description Reference voltage output. Nominal voltage is 2.5 V. Clamping maximum duty cycle under normal operation. Clamping maximum duty cycle under open-lamp condition. Short-circuit protection input (VTH=0.6V) Reference voltage input for dimming control. Current sense feedback. Compensation for the current sense feedback. Ground. Soft-start ensures lamp current pulses gradually increases to its normal value Gate drive output for the P-MOSFET. Gate drive output for the N-MOSFET. Enable input, active high (VTH=1.5V) Output current sense (VTH=0.6V) Timing capacitor. CT and RT set the clock frequency. Timing resistor. Fosc = 1.91 / (Rt • Ct) Supply voltage input. ABSOLUTE MAXIMUM RATINGS VDD 5.5V GND +/- 0.3V Logic inputs -0.3 V to VDD+0.3V OZ965 Operating temp. o OZ965I o 0 C to 70 C o OZ965I .720W .690W .580W .550W Thermal Impedance 16-pin SOP 16-pin TSSOP 111 C/W o 115 C/W o 111 C/W o 115 C/W o -40 C to 85 C o Operating junction temp. Storage temp. o OZ965 Power dissipation 16-pin SOP 16-pin TSSOP 150 C o o -55 C to 150 C RECOMMENDED OPERATING RANGE VDD 5.0 V +/- 5% Fosc 30 KHz to 200 KHz Rosc 50 k to 150 k OZ965-SF-3.0 Page 3 OZ965 FUNCTIONAL SPECIFICATIONS Parameter Symbol Test Conditions 4.75 V < VDD < 5.25 V Limits Unit Min Typ Max 2.37 2.50 2.63 V - 6 - mV/V - 1 - mV/mA - 2.54 Reference Voltage Nominal voltage Vref Iload = 0.1 mA, Line regulation Load regulation Iload = 0.2 mA to 1.0 mA Oscillator Initial accuracy fosc Ct = 470 pF, Rt = 49.9 k Ramp peak Ramp valley 81 KHz - V - 0.48 - V TA = -40oC to 85oC - - 200 ppm/ oC Input bias current ADJ=FB=2.0 V - 0.25 - uA Input offset voltage VFB = 4.0 V 5 10 mV - VDD1.5 V Temp. stability Error Amplifier Input voltage range 0 Open loop voltage gain - 65 - dB Unity gain bandwidth - 1.5 - MHz Power supply rejection - 60 - dB Under-Voltage Lockout Positive-going threshold voltage See Table 1, page 5 Negative-going threshold voltage See Table 1, page 5 Supply - 195 - µA VDD = 5.0 V - 1.0 - mA VOH Isource = 10 mA, VDD = 5V - 4.75 - V Output low voltage VOL Isink = 10 mA, VDD = 5V - 0.25 0.5 V Output resistance ROUT - 10 - Ω - V Supply current - Enable Low IOFF Supply current - Enable High ION Output high voltage NDR output PDR output Output high voltage VOH Isource = 10 mA, VDD = 5V - 4.7 Output low voltage VOL Isink = 10 mA, VDD = 5V - 0.5 - V Output resistance ROUT - 15 - Ω Qn off to Qp on delay THL - 250 - ns Qp off to Qn on delay TLH - 220 - Ns 92 94 96 % - 14 - 92 94 96 - 14 - 6 - 95 Break-Before-Make High Clamp Duty cycle of NDR HCLMP OPS=1 V VHCLMP=0V OPS=1 V, VHCLMP=1.8V Low Clamp Duty cycle of NDR LCLMP OPS=0 V, VLCLMP=0V OPS=0 V, VLCLMP=1.8V % Max. / Min. Duty cycle Duty cycle of NDR OZ965-SF-3.0 % Page 4 OZ965 OZ965 Parameter Test Conditions 4.75V < VDD < 5.25V OZ965I Limits Unit Min Typ Max Positive-going threshold voltage - 3.9 4.3 Negative-going threshold voltage 3.2 3.4 - Limits Unit Min Typ Max V - 3.9 4.5 V V 3.0 3.4 - V Under-Voltage Lockout Table 1. Under-Voltage Lockout for OZ965 and OZ965I OZ965-SF-3.0 Page 5 OZ965 PACKAGE INFORMATION A2 A1 A 16 TSSOP-16 PACKAGE E E1 1 θ2 D R1 b Gauge Plane R e b c L c1 b1 Lead Cross Section θ3 DIM A A1 A2 L D E1 E R R1 b b1 c c1 L1 e θ1 θ2 θ3 OZ965-SF-3.0 INCHES MIN MAX 0.043 0.002 0.006 0.031 0.041 0.020 0.030 0.169 0.177 0.252BSC 0.004 0.004 0.007 0.012 0.007 0.010 0.004 0.008 0.004 0.006 0.039REF 0.026BSC 0° 8° 12°REF 12°REF θ1 L1 MILLIMETERS MIN MAX 1.20 0.05 0.15 0.80 1.05 0.45 0.75 4.90 5.10 4.30 4.50 6.40BSC 0.09 0.09 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 1.0REF 0.65BSC 0° 8° 12°REF 12°REF Page 6 OZ965 DIM E H SOP-16 PACKAGE A A1 B C D E e H L α INCHES MIN MAX 0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 0.050 BCS. 0.2284 0.244 0 0.016 0.050 0° 8° MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BCS. 5.80 6.20 0.40 0° 1.27 8° D A B e A1 C D L OZ965-SF-3.0 Page 7