ETC RTL8305S

RTL8305S
RTL8305S
5-PORT 10/100 MBPS SINGLE CHIP
SWITCH CONTROLLER
1. Features ..................................................................................................................................................................................... 2
2. General Description .................................................................................................................................................................. 2
3. Block Diagram .......................................................................................................................................................................... 3
4. Pin Assignments........................................................................................................................................................................ 4
5. Pin Descriptions ........................................................................................................................................................................ 6
5.1 Media Connection Pins ....................................................................................................................................................... 6
5.2 Mode Pins ........................................................................................................................................................................... 6
5.3 Port4 Related Pins............................................................................................................................................................... 7
5.4 LED Pins............................................................................................................................................................................. 8
5.5 Power Pins .......................................................................................................................................................................... 8
5.6 Miscellaneous Pins.............................................................................................................................................................. 8
5.7 Reserved Pins...................................................................................................................................................................... 8
6. Functional Description.............................................................................................................................................................. 9
6.1 Introduction......................................................................................................................................................................... 9
6.2 Switch Core Functional Overview ...................................................................................................................................... 9
6.2.1 Address Search, Learning and Aging........................................................................................................................... 9
6.2.2 Buffer Management.................................................................................................................................................... 10
6.2.3 Data Reception ........................................................................................................................................................... 10
6.2.4 Data Forwarding......................................................................................................................................................... 10
6.2.5 Flow Control ...............................................................................................................................................................11
6.2.6 Back-off Algorithm .....................................................................................................................................................11
6.2.7 Inter-Frame Gap ..........................................................................................................................................................11
6.2.8 Illegal Frame ...............................................................................................................................................................11
6.2.9 Broadcast Storm Control.............................................................................................................................................11
6.3 Physical Layer Functional Overview .................................................................................................................................11
6.3.1 Auto-negotiation .........................................................................................................................................................11
6.3.2 10Base-T Transmit Function.......................................................................................................................................11
6.3.3 10Base-T Receive Function ........................................................................................................................................11
6.3.4 Link Monitor ...............................................................................................................................................................11
6.3.5 100Base-TX Transmit Function ................................................................................................................................. 12
6.3.6 100Base-TX Receive Function .................................................................................................................................. 12
6.3.7 Power Saving Mode ................................................................................................................................................... 12
6.4 LED................................................................................................................................................................................... 12
6.5 MII Port............................................................................................................................................................................. 13
6.5.1 General Description ................................................................................................................................................... 13
6.5.2 MII/SNI PHY Mode................................................................................................................................................... 16
6.5.3 MII MAC Mode ......................................................................................................................................................... 16
7. Electrical Characteristics......................................................................................................................................................... 18
7.1 Absolute Maximum Ratings ............................................................................................................................................. 18
7.2 Operating Range ............................................................................................................................................................... 18
7.3 DC Characteristics (0°C<Ta<60°C, 3.15V<Vcc<3.45V) ................................................................................................. 18
7.4 AC Characteristics (0°C<Ta<60°C, 3.15V<Vcc<3.45V) ................................................................................................. 19
7.5 Digital Timing Characteristics .......................................................................................................................................... 20
7.6 Thermal Data..................................................................................................................................................................... 20
8. Application Information.......................................................................................................................................................... 21
9. System Application Diagram .................................................................................................................................................. 22
10. Mechanical Dimensions ........................................................................................................................................................ 23
2002/02/19
1
Rev. 1.2
RTL8305S
1. Features
5-port integrated switch with physical layer and
transceiver for 10Base-T and 100Base-TX with
5-port 10/100M UTP or
4-port 10/100M UTP + 1-port MII/SNI
PHY mode MII/SNI interface for router application
MAC mode MII interface for HomeLAN/100Base-FX
application
1Mbit internal RAM for packet buffer
Internal 1K look-up table entries
25MHz crystal or OSC input
Non-blocking wire-speed reception and transmission
Fully compliant with IEEE 802.3/802.3u
Supports broadcast storm filtering function
Support full duplex 802.3x flow control and half
duplex back-pressure flow control
LED indicators for link/activity, speed, full/half duplex
and collision
LEDs blinking upon reset for LED diagnostics
Unmanaged operation by strapping upon reset
Power saving with cable detection
Low power consumption at 3.3V operating voltage
128-pin PQFP package
2. General Description
The RTL8305S is a highly integrated layer 2 single chip switch controller which incorporates 5 MACs (Media Access
Controller), 5 physical layer transceivers, 1-Mbit SRAM and 1K-entry look-up table into one single chip.
The RTL8305S contains 5 ports, and each one provides support for a 10Base-T (10Mbps) or 100Base-TX (100Mbps) network
connection. The fifth port (port 4) can be configured as a MII/SNI to work with a routing engine, HomePHY or a fiber
transceiver for a 100Base-FX application. And each operation mode can be easily set up by hardware strapping upon restart or
power-on.
The RTL8305S is designed for a stand-alone switch system through hardware strapping upon reset to achieve unmanaged
operation and can be easily integrated with xDSL/Cable modem router. With the least peripheral components and using a
25MHz crystal, the RTL8305S has the best system cost structure. The integrated RTL8305S chip benefits from low power
consumption and ease of use for SOHO 5-port switch or xDSL/Cable router applications.
2002/02/19
2
Rev. 1.2
RTL8305S
3. Block Diagram
ENBRDCTRL
ENFCTRL
ENBKPRS
RESET#
NWAYHALF#
IBREF
Global functions
Waveform
Shaping
RXIP/N[0]
TXOP/N[0]
10BASE-T/
100BASE-TX
PHYceiver
Switch
MAC0 Engine
0
RXIP/N[1]
TXOP/N[1]
10BASE-T/
100BASE-TX
PHYceiver
Switch
MAC1 Engine
1
RXIP/N[2]
TXOP/N[2]
10BASE-T/
100BASE-TX
PHYceiver
Switch
MAC2 Engine
2
RXIP/N[3]
TXOP/N[3]
10BASE-T/
100BASE-TX
PHYceiver
Switch
MAC3 Engine
3
X1
X2
CK25MOUT
1K-entry
Look-up
Table
RAMFAIL#
Packet Buffer
Space
16K x 64 bits memory
Page Pointer
Space
Buffer Manager
RXIP/N[4]
TXOP/N[4]
TXC/RXC
TXEN/RXDV
TXD/RXD
RXC/TXC
RXDV/TXEN
RXD/TXD
COL
10BASE-T/
100BASE-TX
PHYceiver
MII
MAC
Out- mode
put
MII
PHY
mode
Switch
MAC4 Engine
4
LED
controller
Revers
circuit
LED_ACT[4:0]
LED_DUP[4:0]
LED_SPD[4:0]
P4MODE[1:0]
2002/02/19
P4LNKSTA#
P4DUPSTA#
P4SPDSTA#
P4FLCTRL#
SEL_MIIMAC#
ENP4LED
DIS_RST_BLNK#
LED_BLNK_TIME
3
Rev. 1.2
RTL8305S
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GND
NC
VDD
NC
P4MODE[0]
P4MODE[1]
NC
NC
GND
NC
NC
ENP4LED
DIS_RST_BLNK#
LED_BLNK_TIME
NC
VDD
NC
NC
NC
NC
NC
NC
ENBRDCTRL
GND
ENBKPRS
ENFCTRL
NWAYHALF#
NC
NC
NC
NC
CK25MOUT
VDD
RESERVED
SEL_MIIMAC#
MRXD[3]/MTXD[3]
MRXD[2]/MTXD[2]
GND
4. Pin Assignments
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8305S
08042T1
050A TAIWAN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
MGND
MRXD[1]/MRXD[1]
VDD
MRXD[0]/MTXD[0]
MRXDV/MTXEN
MRXC/MTXC
MCOL
MTXD[3]/MRXD[3]
MTXD[2]/MRXD[2]
MTXD[1]/MRXD[1]
MTXD[0]/MRXD[0]
VDD
MTXEN/MRXDV
MTXC/MRXC
GND
P4LNKSTA#
P4DUPSTA#
P4SPDSTA#
P4FLCTRL#
X2
X1
VDD
TESTDATA
TESTCLK
RESET#
GND
RGND
TGND
TXOP[0]
TXON[0]
TVDD
TVDD
TXON[1]
TXOP[1]
TGND
RGND
RXIP[1]
RXIN[1]
RVDD
RVDD
RXIN[2]
RXIP[2]
RGND
TGND
TXOP[2]
TXON[2]
TVDD
TVDD
TXON[3]
TXOP[3]
TGND
RGND
RXIP[3]
RXIN[3]
RVDD
RVDD
RXIN[4]
RXIP[4]
RGND
TGND
TXOP[4]
TXON[4]
TVDD
MVDD
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LED_DUP[0]
LED_ACT[0]
LED_SPD[0]
VDD
LED_DUP[1]
LED_ACT[1]
LED_SPD[1]
LED_DUP[2]
LED_ACT[2]
GND
LED_SPD[2]
VDD
LED_DUP[3]
LED_ACT[3]
LED_SPD[3]
LED_DUP[4]
LED_ACT[4]
LED_SPD[4]
TEST#
GND
AGND
IBREF
AVDD
RVDD
RXIN[0]
RXIP[0]
2002/02/19
4
Rev. 1.2
RTL8305S
' I ' stands for inputs; 'O' stands for outputs; 'A' stands for analog; 'D' stands for digital
Name
RGND
TGND
TXOP[0]
TXON[0]
TVDD
TVDD
TXON[1]
TXOP[1]
TGND
RGND
RXIP[1]
RXIN[1]
RVDD
RVDD
RXIN[2]
RXIP[2]
RGND
TGND
TXOP[2]
TXON[2]
TVDD
TVDD
TXON[3]
TXOP[3]
TGND
RGND
RXIP[3]
RXIN[3]
RVDD
RVDD
RXIN[4]
RXIP[4]
RGND
TGND
TXOP[4]
TXON[4]
TVDD
MVDD
GND
RESET#
TESTCLK
TESTDATA
VDD
X1
X2
P4FLCTRL#
P4SPDSTA#
P4DUPSTA#
P4LNKSTA#
GND
MTXC/MRXC
MTXEN/MRXDV
VDD
MTXD[0]/MRXD[0]
MTXD[1]/MRXD[1]
MTXD[2]/MRXD[2]
MTXD[3]/MRXD[3]
MCOL
MRXC/MTXC
MRXDV/MTXEN
MRXD[0]/MTXD[0]
VDD
MRXD[1]/MTXD[1]
MGND
2002/02/19
Pin No.
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61,
62
63
64
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
DVDD
DGND
I
I
I/O
DVDD
I
O
I
I
I
I
DGND
I/O
O
DVDD
O
O
O
O
I/O
I/O
I
I
DVDD
I
DGND
Name
GND
MRXD[2]/MTXD[2]
MRXD[3]/MTXD[3]
SEL_MIIMAC#
RESERVED
VDD
CK25MOUT
NC
NC
NC
NC
NWAYHALF#
ENFCTRL
ENBKPRS
GND
ENBRDCTRL
NC
NC
NC
NC
NC
NC
VDD
NC
LED_BLNK_TIME
DIS_RST_BLNK#
ENP4LED
NC,
NC
GND
NC
NC
P4MODE[1]
P4MODE[0]
NC
VDD
NC
GND
LED_DUP[0]
LED_ACT[0]
LED_SPD[0]
VDD
LED_DUP[1]
LED_ACT[1]
LED_SPD[1]
LED_DUP[2]
LED_ACT[2]
GND
LED_SPD[2]
VDD
LED_DUP[3]
LED_ACT[3]
LED_SPD[3]
LED_DUP[4]
LED_ACT[4]
LED_SPD[4]
TEST#
GND
AGND
IBREF
AVDD
RVDD
RXIN[0]
RXIP[0]
5
Pin No.
Type
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DGND
I
I
O
I
DVDD
O
I
I
I
DGND
I
DVDD
I
I
I
DGND
I
I
DVDD
DGND
O
O
O
DVDD
O
O
O
O
O
GND
O
DVDD
O
O
O
O
O
O
O
DGND
AGND
A
AVDD
AVDD
AI
AI
Rev. 1.2
RTL8305S
5. Pin Descriptions
5.1 Media Connection Pins
Pin Name
RXIP[4:0]
RXIN[4:0]
TXOP[4:0]
TXON[4:0]
Pin No. Type
11,12,15
AI
16,27,28
31,32,127
128
3,4,7,8
AO
19,20,23
24,35,36
Description
Differential Receive Data Input
Default
Differential Transmit Data Output
5.2 Mode Pins
Pin Name
ENBKPRS
ENFCTRL
ENBRDCTRL
LED_BLNK_TIME
DIS_RST_BLNK#
NWAYHALF#
TEST#
2002/02/19
Pin No.
78
77
80
89
90
76
121
Type
Description
Default
I Enable Back Pressure: This pin has no effect on port4 if it is operated as
1
an MII port.
I
I
I
I
I
O
1: Enable (UTP ports only)
0: Disable
Enable Flow Control: The RTL8305S will advertise its ability with flow
control during auto-negotiation. This pin has no effect on port4 if it is operated
as an MII port.
1: Enable Flow control (UTP ports only)
0: Disable
Enable Broadcast Control: This is for the UTP and MII port.
1: Enable
0: Disable
LED Blinking Time: This pin controls the blinking speed of the activity
and collision LEDs.
1: 43ms
0: 120ms
Disable Reset Blinking: This pin controls the blinking of LEDs during
reset and power up. Set to 0, the LEDs will not blink on reset or power up.
1: Enable
0: Disable
Nway Half Duplex: This pin advertises Nway ability to the link partner.
Setting this pin to 0 will advertise an Nway ability with 10/100 half duplex only.
1
1
1
1
1
1: Nway ability supports full duplex
0: Nway ability supports half duplex only
Test: An internal test pin
6
Rev. 1.2
RTL8305S
5.3 Port4 Related Pins
Pin Name
MRXD[3:0]
/MTXD[3:0]
Pin No.
67,66,63
61
MRXDV/MTXEN
60
MRXC/MTXC
59
MCOL
58
MTXD[3:0]
/MRXD[3:0]
57,56,55
54
Type
Description
Default
I For MII MAC mode, these pins are MRXD[3:0], MII receive data nibble.
For MII PHY mode, these pins are MTXD[3:0], MII transmit data nibble.
For SNI PHY mode, MTXD[0] is serial transmit data.
I For MII MAC mode, this pin represents MRXDV, MII receive data valid.
For MII PHY mode, this pin represents MTXEN, MII transmit enable.
I/O For MII MAC mode, it is receive clock, MRXC (acts as input).
For MII/SNI PHY mode, it is transmit clock, MTXC (acts as output).
I/O For MII MAC mode, this pin represents collision (acts as input)
For MII/SNI PHY mode, this pin represents collision (acts as output)
O For MII MAC mode, these pins are MTXD[3:0], MII transmit data nibble.
For MII PHY mode, these pins are MRXD[3:0], MII receive data nibble.
For SNI PHY mode, MRXD[0] is serial receive data.
O For MII MAC mode, this pin represents MTXEN, MII transmit enable.
For MII PHY mode, this pin represents MRXDV, MII receive data valid.
I/O For MII MAC mode, this pin is a transmit clock, MTXC (acts as input).
For MII/SNI PHY mode, this pin is a receive clock, MRXC (acts as output).
I Select Port 4 Operating Mode: 00: SNI PHY mode
11
01: MII PHY mode
1x: UTP / MII MAC mode
I Port 4 Link Status: When P4MODE[1]=1 (UTP/MII MAC mode), this
1
pin decides the link status of the MII port. If both UTP and MII MAC are
linked OK, UTP has higher priority.
MTXEN/MRXDV
52
MTXC/MRXC
51
P4MODE[1:0]
97,98
P4LNKSTA#
49
P4DPXSTA#
48
I
When P4MODE[1]=0 (PHY mode), this pin decides link status of Port4.
Active Low Duplex Status:
1: Half duplex
0: Full duplex
1
P4SPDSTA#
47
I
When P4 is operated in UTP mode, this pin has no effect.
Active Low Speed Status:
1: 10Mbps
0: 100Mbps
1
This pin must be kept floating for the three applications listed below.
This is because the speed is either determined by auto-negotiation or
fixed at 1M/10M Hz.
P4FLCTRL#
ENP4LED
SEL_MIIMAC#
46
91
68
I
I
O
1. For UTP mode, speed is determined by the auto-negotiation procedure.
2. For HomePNA (MII MAC mode), speed is determined by RXC and
TXC from HomePHY running at 1Mbps.
3. For SNI PHY mode, speed is dedicated to 10MHz clock rate.
Active Low Flow Control Enable: When P4 is operated in UTP mode,
this pin has no effect.
1: Disable
0: Enable
Enable Port 4 LED: In UTP applications, this pin should be floating to
drive the LEDs of port 4.
1
1
1: Drive LED pins of port4
0: Tri-state LED pins of port4
Select MII MAC: When P4MODE[1]=1, this pin indicates whether UTP
path or MII MAC path is selected.
1: UTP is selected
0: MII port is selected
While P4MODE[1]=1, the RTL8305S supports UTP/MII MAC auto-detect
function via the link status of P4 UTP and the status of P4LINKSTA# with
priority UTP over MII.
2002/02/19
7
Rev. 1.2
RTL8305S
5.4 LED Pins
Pin Name
LED_ACT[4:0]
LED_DPX[4:0]
LED_SPD[4:0]
Pin No.
119,116
111,108
104
118,115
110,107
103
120,117
113,109
105
Type
Description
O Active low (Link + Activity) LED pins.
Default
1
O
Active low (Fullduplex + Collision) LED pins.
1
O
Active low Speed100 LED pins.
1
5.5 Power Pins
Pin Name
TVDD
RVDD
AVDD
MVDD
VDD
RGND
TGND
AGND
MGND
GND
Pin No. Type
Description
5,6,21
P 3.3V Analog Transmit Power
22,37
13,14,29
P 3.3V Analog Receive Power
30,126
125
P 3.3V Analog Power
38
P 3.3V Internal RAM Power
43,53,62
P 3.3V Digital Power
70,87,100
106,114
1,10,17
P Analog Ground
26,33
2,9,18
P Analog Ground
25,34
123
P Analog GND
64
P Internal RAM GND
39,50,65
P Digital GND
79,94,102
112,122
Default
5.6 Miscellaneous Pins
Pin Name
X1
X2
CK25MOUT
RESET#
Pin No.
44
45
71
40
IBREF
124
TESTCLK
TESTDATA
41
42
Type
I
O
O
I
Description
Default
25MHz crystal or oscillator clock input
To crystal input. When using an oscillator this pin should be kept floating.
25MHz clock output
Active low reset signal. To complete the reset function, this pin must be
asserted for at least 10ms. After reset, about 30ms is needed for the
RTL8305S to complete the internal test function and initialization.
A Control transmit output waveform Vpp. This pin should be grounded
through a 1.96KΩ resistor.
I Test clock
I/O Test data
5.7 Reserved Pins
Pin Name
RESERVED
2002/02/19
Pin No.
69
Type
Description
I This pin is reserved for internal use and should be left floating.
8
Default
1
Rev. 1.2
RTL8305S
6. Functional Description
6.1 Introduction
Providing five 10/100 Mbps Ethernet channels and one MII port, the RTL8305S can be configured for either a five port 10/100
Ethernet application or a four 10/100 port Ethernet with an extra MII/SNI port. The MII/SNI port can be connected to an
external processor for routing purposes as public area network devices do, referred to as MII/SNI PHY mode, or connected to
a HomePNA physical chip or 100Base-FX PHYceiver, referred to as MII MAC mode.
In MII/SNI PHY mode, pins RXC, RXDV, and RXD correspond to TXC, TXEN, and TXD. In MII MAC mode, TXC, TXEN
and TXD correspond to RXC, RXDV and RXD.
The frame buffer is composed of 1M bits of built-in memory. The address look-up table for MAC addresses learning/searching
consists of 1K direct-mapping entries.
The RTL8305S uses Nway auto-negotiation to complete the UTP port connections of physical links which conform to IEEE
802.3u specifications. IEEE 802.3x full duplex flow control is supported. When operating in half duplex mode, a proprietary
back-pressure algorithm is implemented to prevent traditional hub devices from partitioning due to excessive collisions.
The RTL8305S supports non-blocking wire speed forwarding rates and special designs to resolve head-of-line blocking problems
and channel-capture problems. A broadcast storm filtering function is also provided for abnormal broadcast traffic issues.
6.2 Switch Core Functional Overview
6.2.1 Address Search, Learning and Aging
The RTL8305S contains a full 1K of look-up table entries and uses a direct-mapping scheme to achieve address search and
learning.
By extracting the least 10 bits of a destination MAC address to index the 1K-entry look-up table, the RTL8305S can decide
where the packet goes. If the searching result indexes to an empty entry, the packet is broadcast to all other ports. On the other
hand, the RTL8305S extracts the least 10 bits of a source MAC address to index the 1K-entry look-up table. If the result
indexes to an empty entry, it records the source MAC address and related switching information. If the result leads to an
occupied entry with different switching information, it updates the entry with the new information. This is referred to as
‘learning.’ The look-up engine will update time stamp information of an entry whenever the corresponding source MAC
address appears. If the time information is not updated for a period of time, the entry will be removed, referred to as the aging
process. The maximum aging time for the RTL8305S is approximately 300 seconds, and the minimum aging time is
approximately 200 seconds.
2002/02/19
9
Rev. 1.2
RTL8305S
6.2.2 Buffer Management
The 1M bit embedded memory buffer is divided into a packet buffer, which is used for data buffering, and a page pointer block
(PPB), which is used by the buffer manager. The Packet buffer is constructed of approximately 512 256-byte pages. Each page
includes 8-bytes of header information, which consists of next page pointer, packet byte count, and 248 bytes of data. The
linked pages construct a whole received packet which will be forwarded later according to its destination. The buffer manager
gets free page pointers from PPB and releases to each port to provide space for incoming packet buffering. When the buffer
manager can not support free page pointers any more, it indicates a buffer full condition and 802.3x flow control or back
pressure congestion control is implemented. If no flow control algorithms are activated, packets are dropped.
Page177
Buffer Manager
Page180
Page177 PTR
Page180 PTR
Free Page Pointers
Page193 PTR
Page189 PTR
Page189
Free Page Pointer FIFO
Page193
Frame Buffer
6.2.3 Data Reception
Each port contains a Receive FIFO for incoming packets, which are from physical medium, and a Free Page Pointer FIFO for
packet buffering indexes. Free Page Pointers are obtained from the Buffer Manager. Once a packet is received, it is segmented
into 248-byte pieces (as is fit into pages) and then moved into a packet buffer by the Receive DMA Engine with an 8-byte
header in every page.
6.2.4 Data Forwarding
Each port contains a Transmit FIFO, a Transmit Free Page Pointer FIFO and a Transmit Start Address Queue. The Transmit
Free Page Pointer FIFO stores Free Pages Pointers which have just been released from transmitted packets, and will return
these Free Pages to the Buffer Manager for buffering indexes of the next incoming packets. The Transmit Start Address Queue
keeps the first page pointer of every egress packet, which is from the transmit command issued by the reception port (source
port). The destination ports identify every transmit command on the global bus and receive it if they are the outlets. Finally, the
Transmit DMA engine of each port starts the DMA to move the pages (which construct a whole packet) to Transmit FIFO and
then to the physical medium. For broadcast packets, it’s the duty of the last port which finishes the transmission action last to
return the Transmit Free Page Pointers to the Buffer Manager.
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6.2.5 Flow Control
The RTL8305S supports IEEE 802.3x full duplex flow control and half duplex back-pressure congestion control. Once
the full duplex flow control ability is enabled via ENFCTRL, the Nway ability with full duplex flow control will be
negotiated during the auto-negotiation process. When operating in half duplex mode, a proprietary back-pressure
algorithm is enabled via the ENBKPRS pin, which can prevent traditional hub devices from partition due to excessive
collisions. For MII port applications, the same functions will be applied to port4 depending on the state of P4FLCTRL#
and P4DUPSTA#. If port4 is not configured to MII port application, it acts as a UTP port and behaves according to the
configuration of the ENFCTRL and ENBKPRS pins.
6.2.6 Back-off Algorithm
The RTL8305S implements the truncated exponential back-off algorithm compliant to the 802.3 standard. The collision
counter will be reset after 16 consecutive collisions, which leads to a smaller back-off time.
6.2.7 Inter-Frame Gap
The Inter-Frame Gap is 9.6us for 10Mbps Ethernet and 960ns for 100Mbps Fast Ethernet.
6.2.8 Illegal Frame
Illegal frames such as CRC error packets, runt packets ( packet length less than 64 bytes) and oversize packets (packet length
greater than 1536 bytes) will be discarded.
6.2.9 Broadcast Storm Control
The RTL8305S processes broadcast storm control via the latched value of the EnBrdCtrl pin upon reset. Once enabled, the
incoming consecutive broadcast packets will be discarded after consecutive 64 broadcast packets are received during an 800ms
time window. Any non-broadcast packets can reset the time window and broadcast counter such that the scheme restarts.
6.3 Physical Layer Functional Overview
6.3.1 Auto-negotiation
The RTL8305S obtains the states of duplex, speed and flow control ability through the auto-negotiation mechanism, defined in
IEEE802.3u specifications, for each UTP port. During auto-negotiation, each port advertises its ability to its link partner and
compares ability with those received from its link partner. By default, the RTL8305S advertises full capabilities (100Full,
100Half, 10Full, 10Half) together with flow control ability.
Asserting NWAYHALF# sets the Nway ability of the RTL8305S to half duplex only (100Half, 10Half). Deasserting
ENFCTRL sets the Nway ability without the flow control function. ENBKPRS is a pin to enable the half duplex flow control
scheme, which is defined in auto-negotiation. The MII port obtains its duplex, speed, flow control and link states from pins as
described in section 5.5.
6.3.2 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded and driven into the network medium. The internal filter shapes the
driven signals to reduce EMI emission, eliminating the need for an external filter.
6.3.3 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects that the signal level
has exceeded the configured squelch level.
6.3.4 Link Monitor
The 10Base-T link pulse detection circuit always monitors the RXIP/RXIN pins for the presence of valid link pulses.
Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs.
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6.3.5 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT3 encoding. After 4B/5B coding, the 5-bit serial data stream is scrambled as defined by the TP-PMD Stream Cipher
function to flatten the power spectrum energy such that EMI effects can be significantly reduced.
The scrambled seed is unique for each port, based on PHY addresses. After scrambling, the bit stream is driven into the
network medium in the form of MLT-3 signaling. Multi-level signaling technology moves the power spectrum energy from
high frequency to low frequency, which also benefits EMI emission issues.
6.3.6 100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits, to compensate for the
incoming distortion of the MLT-3 signal, MLT-3 to NRZI, NRZI to NRZ converter to convert analog signaling to a digital
bit-stream, and a PLL circuit to clock data bits precisely with minimum bit error rate. The de-scrambler, 5B/4B decoder and
serial-to-parallel conversion circuits follow. Finally, the converted parallel data is fed into the MAC.
6.3.7 Power Saving Mode
The RTL8305S implements power saving mode on per port basis. A port automatically enters power saving mode 10 seconds
after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its
TXOP/TXON pins and keeps monitoring RXIP/RXIN to try to detect any incoming signals, which might be a 100Base-TX
MLT-3 idle pattern, 10Base-T link pulses or Nway’s FLP (Fast Link Pulses). After it detects any incoming signals, it wakes up
from the power saving mode and operates in the normal mode according to the result of the connection.
6.4 LED
The RTL8305S supports three parallel LEDs for each port. LED_ACT indicates activity and link status, LED_DPX indicates
collision and duplex status, and LED_SPD indicates operating speed with state ‘0’ equal to 100Mbps. All LED pins are active
low, and blink when presenting activity and collision states. During power-on reset, the RTL8305S supports diagnostics of
chip reset and LED functions by blinking all parallel LEDs once. This function can be disabled by asserting
DIS_RST_BLINK# to 0. LED_BLINK_TIME determines LED blinking period for activity and collision, with 1 = 43ms and 0
= 120ms. LEDs corresponding to port 4 can be tri-stated (disable LED functions) for MII port applications by pulling
ENP4LED low.
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6.5 MII Port
6.5.1 General Description
PO W ER-O N
RESET
PH Y m ode
0
M A C m ode
1
P4M O D E[1]
U TP
SN I
0
P4M O D E[0]
1
SN IPH Y
10M bps
(10M H z)
1
M II
P4SPD STA #
M IIPH Y
10M bps
(2.5M H z)
M II
0
1
M IIPH Y
100M bps
(25M H z)
NO
P4LN K STA #
YES
U TP LIN K O N ?
0
M II M AC
H om eLAN /100FX
(1M /2.5M /25M H z)
S E L _M IIM A C #=0
U TP Port
10/100Base-T
S E L _M IIM A C #=1
The RTL8305S supports an extra MII interface for external devices. Two modes are implemented on the MII port, MII/SNI
PHY mode, and MII MAC mode. In MII/SNI PHY mode, a routing engine can connect ADSL or a cable modem to a LAN
through the MII port of the RTL8305S. In MII MAC mode, other types of LAN medium can be supported such as HomePNA
or 100Base-FX via the underlying physical devices through the MII port of the RTL8305S. The MII signals do not include
MTXER,MRXER and MCRS for RTL8305S. MDC/MDIO signals are also not supplied. Additional pins are used to complete
link, speed, duplex and flow-control settings described as follows.
When port4 is configured to something other than a UTP port, i.e. MII port is activated, four input pins, P4LNKSTSA#,
P4DPXSTA#, P4SPDSTA# and P4FLCTRL# are provided to determine link, duplex, and speed statuses as well as flow
control ability similar to force mode. These four pins are active low.
If P4LNKSTA#=0, the RTL8305S takes the MII port as link on, and will forward/receive packets to/from the MII port.
If P4DPXSTA#=0, the RTL8305S takes the MII port as full duplex, allowing simultaneous Tx/Rx.
If P4SPDSTA#=0, the RTL8305S takes the MII port as 100Base-TX, and outputs a 25MHz clock signal from the MTXC and
MRXC pins while in MII PHY mode. If P4SPDSTA#=1, it outputs a 2.5MHz clock signal instead. For SNI PHY mode
(P4MODE[1]=0, P4MODE[0]=0), both MTXC and MRXC are 10MHz clock output signals and P4SPDSTA# should be
floating. For MII MAC mode (P4MODE[1]=1), MTXC and MRXC are clock inputs from the underlying physical device.
It is suggested to keep P4SPDSTA# floating for SNI PHY mode and MII MAC mode for HomePNA applications, due to the
dedicated speed of these two applications.
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RTL8305S
The other active-low input pin is P4FLCTRL#, which determines if flow control algorithm is enabled through the MII port.
(default P4FLCTRL#=1 )
If P4FLCTRL#=0 and P4DPXSTA#=0, 802.3x flow control packets will flow through the MII port.
If P4FLCTRL#=0 and P4DPXSTA#=1, a back-pressure algorithm will be implemented through the MII port.
If P4FLCTRL#=1, no flow control algorithm is performed on the MII port.
All three input pins, P4DPXSTA#, P4SPDSTA#, and P4FLCTRL#, have no effect when P4LNKSTA#=1.
It is important to note that the MRXD[3:0] pins in MII/SNI PHY mode are MTXD[3:0] for MII MAC mode, and vice versa.
Also the same for pin MRXDV vs. MTXEN, and pin MRXC vs. MTXC.
NOTE: There are no MRXER, MTXER, MCRS and SMI (MDC/MDIO) pins for MII signaling. Because of the absence of
MCRS, system designers can wire MRXDV directly to CRS and RXDV of the opposite chip.
R TL8305S
x
x
x
x
x
x
x
x
Floating=High
Floating=High
Floating=High
Floating=High
P4Mode[1]
59 MRXC/MTXC
P4Mode[0]
60 MRXDV/MTXEN
P4LnkSta#
P4SpdSta#
67~61 MRXD[3:0]/MTXD[3:0]
Floating=High
P4DupSta#
Floating=High
P4FlCtrl#
52 MTXEN/MRXDV
EnP4Led
57-54 MTXD[3:0]/MRXD[3:0]
SelMiiMac#
58 COL
Floating=High
Not Used
4
51 MTXC/MRXC
A llshould be floating
4
5 UTP Mode (Default five port switch application)
For general cases, most of the option pins should be floating (=High=Enable), except EnBrdCtrl. This means that EnBrdCtrl
should be pulled down (=Low=Disable) for normal applications.
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RTL8305S
The illustrations below show a summary of MII/SNI application circuits for port4 of the RTL8305S.
Note that, as described above, the pins MRXC, MRXDV and MRXD in MII/SNI PHY mode are pins MTXC, MTXEN and
MTXD in MII MAC mode, and vice versa.
R TL8305S
x
Floating=High
Pull-down=Link On
Note1
Note1
51 MTXC/MRXC
P4Mode[0]
52 MTXEN/MRXDV
P4LnkSta#
P4SpdSta#
P4DupSta#
Note1
x
x
Floating=High
Not used
25M/2.5MHz
P4Mode[1]
57-54 MTXD[3:0] /MRXD[3:0]
4
59 MRXC/MTXC
P4FlCtrl#
60 MRXDV/MTXEN
EnP4Led
67~61 MRXD[3:0]/MTXD[3:0]
SelMiiMac#
58 COL
4
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
R outing Engine
MII PHY mode
R TL8305S
x
x
x
10MHz
P4Mode[1]
51 MTXC/MRXC
P4Mode[0]
52 MTXEN/MRXDV
Pull-down=Link On
P4LnkSta#
54 MTXD[0]/MRXD[0]
Floating=10M
P4SpdSta#
Note1
P4DupSta#
Note1
P4FlCtrl#
60 MRXDV/MTXEN
Floating=High
EnP4Led
61 MRXD[0]/MTXD[0]
SelMiiMac#
58 COL
Not used
1
59 MRXC/MTXC
1
RXC
CRS
RXDV
RXD
TXC
TXEN
TXD
COL
R outing Engine
SNI PHY mode
R TL8305S
x
x
x
x
x
x
Floating=High
Floating=High
P4Mode[1]
P4Mode[0]
1MHz
59 MRXC/MTXC
60 MRXDV/MTXEN
Pull-down=Link On
Floating=High
P4LnkSta#
Floating=High
P4DupSta#
Floating=High
P4FlCtrl#
52 MTXEN/MRXDV
EnP4Led
57-54 MTXD[3:0]/ MRXD[3:0]
SelMiiMac#
58 COL
Floating=High
Used
P4SpdSta#
67~61 MRXD[3:0]/ MTXD[3:0]
4
51 MTXC/MRXC
4
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
H om ePH Y
A M 79C 901A
D P83851
MII MAC mode (HomePNA Application)
R TL8305S
x
x
Floating=High
Floating=High
60 MRXDV/MTXEN
P4LnkSta#
Pull-down=100M
P4SpdSta#
P4DupSta#
Note1
x
59 MRXC/MTXC
P4Mode[0]
Pull-down=Link On
Note1
Floating=High
Used
25MHz
P4Mode[1]
67~61 MRXD[3:0]/ MTXD[3:0]
4
51 MTXC/MRXC
P4FlCtrl#
52 MTXEN/MRXDV
EnP4Led
57-54 MTXD[3:0]/ MRXD[3:0]
SelMiiMac#
58 COL
4
Single PH Y
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
Fiber
Transceiber
MII MAC mode (100Base-FX Application)
Note 1: Floating or Pull-down states depend on application.
Note 2: For general cases, most of the option pins should be floating (=High=Enable), except for EnBrdCtrl. This means that
EnBrdCtrl should be pulled down (=Low=Disable) for normal applications.
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Rev. 1.2
RTL8305S
6.5.2 MII/SNI PHY Mode
In routing applications, the RTL8305S cooperates with a routing engine to communicate with a WAN (Wide Area Network)
through MII/SNI. In such applications, P4LNKSTA# =0 and P4MODE[1] are pulled low upon power-on reset. P4MODE[0]
determines whether MII or SNI mode is selected. In MII (nibble) mode (P4MODE[0]=1), P4SPDSTA# =0 results in MII
operating at 100Mbps with MTXC and MRXC running at 25MHz; however, P4SPDSTA#=1 leads to MII operating at 10Mbps
with MTXC and MRXC running at 2.5MHz. In SNI (serial) mode (P4MODE[0]=0), P4SPDSTA# has no effect and must be
floating. SNI mode operates at 10Mbps only, with MTXC and MRXC running at 10MHz. In SNI mode, RTL8305S does not
loopback RXDV signals as a response to TXEN and does not support heart-beat functions (asserting the COL signal for each
complete TXEN signal).
By pulling-up ENP4LED (internal default =1), the RTL8305S displays the MII/SNI status through LEDs of port 4, such as
activity/link, collision/duplex, and speed.
6.5.3 MII MAC Mode
In HomePNA/100Base-FX applications, the RTL8305S provides the MII interface to the underlying HomePNA or
100Base-FX related physical devices to communicate with other types of LAN medium. In such applications, P4MODE[1] is
pulled high upon power-on reset and the RTL8305S supports the UTP/MII auto-detection function. When both UTP and MII
are active (link on), the UTP port has a higher priority over the MII port. In HomePNA applications, P4SPDSTA# must be
floating and, since HomePNA is half-duplex only, P4DPXSTA# should be floating as well. It is recommend to pull
P4LNKSTA# low instead of being wired to the LINK LED pin of the HomePHY because of the unstable link state of the
HomePHY configuration, which is a characteristic based on the HomePNA 1.0 standard. For 100Base-FX applications,
P4LNKSTA# =0, P4SPDSTA# =0 and P4DPXSTA# depends on the application.
By pulling-up ENP4LED (internal default =1), the RTL8305S displays the MII status through the LEDs of port 4, such as
activity/link, collision/duplex, and speed. Pin SEL_MIIMAC# can be used to indicate that the MII MAC port is active by a
LED for the sake of UTP/MII auto-detection. Finally, a 25MHz clock output (CK25MOUT) can be used as a clock source for
the underlying HomePHY/100Base-FX physical devices.
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Rev. 1.2
RTL8305S
A brief application for HomePNA and 100Base-FX is depicted below.
3.3V 3.3V 3.3V
LEDACT[4]
LEDDPX[4]
LEDSPD[4]
P4MODE[1]
P4MODE[0]
3.3V
RTL8305S
P4LNKSTA#
P4SPDSTA#
P4DPXSTA#
P4FLCTRA#
SEL_MIIMAC#
ENP4LED
CK25MOUT
MII
HomePHY
LED_LINK#
LED_ACT#
LED_COL#
LED_SPD#
Common LEDs (RTL8305S driving)
MII MAC mode (UTP / HomeLAN auto-detect)
3.3V
3.3V
3.3V
LEDACT[4]
LEDDPX[4]
LEDSPD[4]
P4MODE[1]
P4MODE[0]
3.3V
RTL8305S
P4LNKSTA#
P4SPDSTA#
P4DPXSTA#
P4FLCTRA#
SEL_MIIMAC#
ENP4LED
CK25MOUT
MII
Single
PHY
SD+/-
LED_LINK#
LED_ACT#
LED_COL#
LED_SPD#
RD+/-
TD+/-
Fiber Transceiver
Common LEDs (RTL8305S driving)
MII MAC mode (UTP / 100Base-FX auto-detect)
As illustrated above, P4LNKSTA# needs to be pulled low to enable the MII MAC port, accompanied with P4MODE[1] pulled
high. An LED connected to SEL_MIIMAC# pin can indicate whether the UTP or MII port is selected.
For 100Base-FX applications, the Link LED status pin can even be wired to P4LNKSTA# to implement the UTP/MII
auto-detection feature with no need to permanently disable port4 UTP capabilities. For the RTL8305S, UTP priority takes over
the MII port if both are link on.
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RTL8305S
7. Electrical Characteristics
7.1 Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device
reliability. All voltages are specified reference to GND unless otherwise specified.
Parameter
Min
Max
Units
Storage Temperature
-45
+125
°C
Vcc Supply Referenced to GND
-0.5
+4.0
V
Digital Input Voltage
-0.5
Vcc
V
DC Output Voltage
-0.5
Vcc
V
7.2 Operating Range
Parameter
Ambient Operating Temperature(Ta)
Vcc Supply Voltage Range(Vcc)
Min
0
3.15
Max
+60
3.45
Units
°C
V
7.3 DC Characteristics (0°C<Ta<60°C, 3.15V<Vcc<3.45V)
Parameter
Power Supply Current
SYM
Icc
Power Consumption
PS
TTL Input High Voltage
TTL Input Low Voltage
TTL Input Current
TTL Input Capacitance
Output High Voltage
Output Low voltage
LED Output Current
Vih
Vil
Iin
Cin
Voh
Vol
Ioh
2002/02/19
Conditions
10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100% utilization
10/100 Base-TX, low power without cable
10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100% utilization
10/100 Base-TX, low power without cable
Min
Typical
150
610
450
500
240
0.495
2.013
1.485
1.650
0.792
Max Units
mA
W
2.0
0.8
50
-50
5
Vcc-0.4
0.4
33
18
V
V
µA
pF
V
V
mA
Rev. 1.2
RTL8305S
Parameter
Output Tristate Leakage Current
TX+/- Output Current High
TX+/- Output Current Low
TX+/- Output Current High
TX+/- Output Current Low
TX+/- Output Current High
TX+/- Output Current Low
TX+/- Output Current High
TX+/- Output Current Low
Symbol
Conditions
|IOZ|
Transmitter, 100Base-TX (1:1 Transformer Ratio)
IOH
IOL
Transmitter, 10Base-T (1:1 Transformer Ratio)
IOH
IOL
Transmitter, 100Base-TX (1.25:1 Transformer Ratio)
IOH
IOL
Transmitter, 10Base-T (1.25:1 Transformer Ratio)
IOH
IOL
Receiver, 100Base-TX
Min
Typical
Max Units
10
µA
40
mA
uA
100
mA
µA
32
mA
µA
80
mA
µA
0
0
0
0
RX+/- Common-mode input voltage
RX+/- Differential input resistance
1.32
20
V
KΩ
20
340
kΩ
mV
Receiver, 10BaseT
Differential Input Resistance
Input Squelch Threshold
7.4 AC Characteristics (0°C<Ta<60°C, 3.15V<Vcc<3.45V)
Parameter
Symbol
VOS
Conditions
Transmitter, 100Base-TX
50Ω from each output to Vcc, Best-fit over
14 bit times
50Ω from each output to Vcc, |Vp+|/ |Vp-|
Differential Output Voltage,
peak-to-peak
Differential Output Voltage
Symmetry
Differential Output Overshoot
Rise/Fall time
Rise/Fall time imbalance
VOD
VOO
tr,tf
Percent of Vp+ or Vp10-90% of Vp+ or Vp-
TD Short Circuit Fault
Tolerance
TD Differential Output
Impedance (return loss)
TD Common-Mode Output Voltage
Transmitter Output Jitter
RD Differential Output
Impedance (return loss)
Harmonic Content
Start-of-idle Pulse width
2002/02/19
1.968
V
1
%
%
ns
ps
±175
±200
ps
0.9
1.0
ns
4.5
5.06
5.5
V
15.6
16
ms
3.3
VOD
13.6
Ecm
Period of time from start of TP_IDL to link
pulses or period of time between link pulses
Peak output current on TD short circuit for
10 seconds
Return loss from 5MHz to 10MHz for
reference resistance of 100 Ω
Terminate each end with 50Ω resistive load
Return loss from 5MHz to 10MHz for
reference resistance of 100 Ω
dB below fundamental, 20 cycles of all
ones data
TP_IDL width
35
19
Max Units
5
4.1
500
Deviation from best-fit time-grid, 010101...
Sequence
Idle pattern
Transmitter, 10Base-T
50Ω from each output to Vcc, all pattern
Timing jitter
Typical
3.32
3.8
200
|tr - tf|
Duty Cycle Distortion
Differential Output Voltage,
peak-to-peak
TP_IDL Silence Duration
Min
152
26
45.6
11.5
27
280
mA
40
dB
50
mV
ns
dB
28
dB
330
ns
Rev. 1.2
RTL8305S
7.5 Digital Timing Characteristics
Parameter
Active TX_EN Sampled to first
bit of “J on MDI output
Inactive TX_EN Sampled to
first bit of “T on MDI output
TX Propagation Delay
First bit of “J on MDI input to
CRS_DV assert
First bit of “T on MDI input to
CRS_DV de-assert
RX Propagation Delay
Symbol
Conditions
100Base-TX Transmit System Timing
Min
Typical
Max Units
Bits
Bits
tTXpd
From TXD[1:0] to TXOP/N
100Base-TX Receive System Timing
From RXIP/N to CRS_DV
Bits
From RXIP/N to CRS_DV
tRXpd
TX Propagation Delay
TXEN to MDI output
tTXpd
Carrier Sense Turn-on delay
Carrier Sense Turn-off Delay
RX Propagation Delay
tCSON
tCSOFF
tRXpd
LED On Time
LED Off Time
tLEDon
tLEDoff
Jabber Active
Jabber de-assert
From RXIP/N to RXD[1:0]
10Base-T Transmit System Timing
From TXD[1:0] to TXOP/N
From TXEN assert to TXOP/N
10Base-T Receive System Timing
Preamble on RXIP/N to CRS_DV asserted
TP_IDL to CRS_DV de-asserted
From RXIP/N to RXD[1:0]
LED Timing
While LED blinking
While LED blinking
Jabber Timing (10Base-T only)
From TXEN=1 to Jabber asserted
From TXEN=0 to Jabber de-asserted
6
8
Bits
16
18
Bits
15
17
Bits
5
5
6
6
Bits
Bits
9
12
Bits
Bits
Bits
12
8
9
43
43
60
60
70
Min
Typical
24
ms
ms
80
86
ms
ms
7.6 Thermal Data
Parameter
Thermal resistance: junction to
ambient,
0 ft/s airflow
Thermal resistance: junction to
case,
0 ft/s airflow
2002/02/19
Symbol
θja
Conditions
4 layers PCB, ambient temperature 25°C
θjc
4 layers PCB, ambient temperature 25°C
20
3.9
Max Units
°C/W
°C/W
Rev. 1.2
RTL8305S
8. Application Information
UTP (10Base-T/100Base-TX) Application
RXIP
RXIN
Pulse H1053
Transformer
1:1
50Ω
1%
50Ω
1%
TXON
1
0.1uF
2
AGND
3
4
3.3V
RTL8305S
TXOP
RJ45
3.3V
5
1:1
50Ω
1%
6
7
50Ω
1%
8
0.1uF
AGND
IBREF
75Ω ∗ 3
1.96ΚΩ, 1%
0.1uF/3KV
AGND
Chasis GND
RTL8305S UTP Application
2002/02/19
21
Rev. 1.2
RTL8305S
9. System Application Diagram
RTL8305S
RTL8305S
5X Transformer
4X Transformer
Fiber
interface
10/100Mbps x 4 UTP
100Base-FX x 1
10/100Mbps x 5 UTP
RTL8305S
RTL8305S
Routing
Engine
4X Transformer
HomePNA
device
4X Transformer
10/100Mbps x 4 UTP
HomeLAN x 1
2002/02/19
ADSL/
Cable
modem
10/100Mbps x 4 UTP
WAN x 1
22
Rev. 1.2
RTL8305S
10. Mechanical Dimensions
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
2002/02/19
Dimension in inch
Min Typical Max
0.134
0.004 0.010 0.036
0.102 0.112 0.122
0.005 0.009 0.013
0.002 0.006 0.010
0.541 0.551 0.561
0.778 0.787 0.797
0.010 0.020 0.030
0.665 0.677 0.689
0.902 0.913 0.925
0.027 0.035 0.043
0.053 0.063 0.073
0.004
0°
12°
Dimension in mm
Min Typical Max
3.40
0.10
0.25 0.91
2.60
2.85 3.10
0.12
0.32
0.22
0.05
0.25
0.15
13.75 14.00 14.25
19.75 20.00 20.25
0.25
0.75
0.5
16.90 17.20 17.50
22.90 23.20 23.50
0.68
1.08
0.88
1.35
1.85
1.60
0.10
0°
12°
1. Dimension D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/
intrusion.
3. Controlling dimension : Millimeter
4. General appearance spec. should be based on final
visual inspection spec.
TITLE : 128 QFP (14x20 mm ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 3.2 mm
LEADFRAME MATERIAL :
APPROVE
DOC. NO. 530-ASS-P004
VERSION
1
PAGE
OF
CHECK
DWG NO.
Q128 - 1
DATE
Oct. 08 1998
REALTEK SEMICONDUCTOR CO., LTD
23
Rev. 1.2
RTL8305S
Document Revision Information
Revision
1.00
1.01
1.02
1.03
Date
10/04/2000
10/05/2000
10/06/2000
11/15/2000
1.04
11/20/2000
1.05
1.06
1.07
11/29/2000
12/05/2000
12/06/2000
1.08
1.09
1.10
1.11
12/08/2000
12/18/2000
12/22/2000
01/11/2001
1.12
1.13
1.14
1.15
01/19/2001
01/29/2001
02/13/2001
02/16/2001
1.16
1.17
02/19/2001
05/14/2001
1.20
02/19/2002
Change
Original document.
Add system application diagram. P.3
Add power consumption. P.20
Rename TX+/- to TXOP/N and RX+/- to RXIP/N. P.5
Add pull-up 3.3V on resistors of TXOP/N. P.19
Update power consumption, Power Supply Current P.20
Update AC characteristics
Clarify Port4 diagram and function. P.14, P.16
Clarify Pin assignment, Port4 diagram and function. P.5, P.16
Update Maximum legal frame size 1728 as 1536. Update Port4
diagram and function. P.12, P.16, P.18
Update Thermal Theta JA & Theta JC. P.23
Add figure. Update figure note. P.15, P.16
Revise 8k as 1k. P.10
Revise pin name as TEST# on P.5, P.6, P.7
Revise range of Storage Temperature on P.21.
Revise Ta from 70 degree C to 60 degree C on P.21 and P.22
Revise aging time 300sec as Max 300 sec, Min 200 sec on P.10
It is no recommended to use internal power on auto reset on P.1 P.8
Clarify NwayHalf# pin description on P.7
Clarify P4LNKSTA# pin description on P.7
Clarify SEL_MIIMAC# pin description on P.8
Clarify Features description on P.1
Clarify general description on P.1
Change Picture Item color on P.16
General English adjustment.
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
WWW: www.realtek.com.tw
2002/02/19
24
Rev. 1.2