SED1180 SED1180 CMOS LCD 64-SEGMENT DRIVER ■ DESCRIPTION The SED1180 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through 4-bit bus, and serially transferred through 16 × 4 bit shift register. The display data is held in a 64-bit latch circuit. The LSI converts the level of the latched data to an LCD drive waveform. The SED1180 is used in conjunction with the SED1190 (64-bit row driver) to drive a large-capacity dot matrix LCD panel. ■ FEATURES • Low-power CMOS technology • 64-bit segment (column) driver • High-speed 4-bit data • Duty cycle ..................................... 1/64 to 1/128 • Daisy chain enable support • Wide range of LCD voltage .......... –14V to –25V • Supply voltage .................................. 5.0V ±10% QFP1-80 pin (F ) • Package ................................ QFP5-80 pin (F ) 0A 5A DIE: Al pad chip (D0A) ■ SYSTEM BLOCK DIAGRAM D0 ~ D3 XSCL LCD CONTR LP, FR YSCL YD SED1190 64 SED1180 SED1180 SED1180 SED1180 64 64 64 64 256 SEG × 64 COM DUTY: 1/64 425 SED1180 ■ BLOCK DIAGRAM 1 0 SEG 31 D0 D1 LCD Driver 32 bits D2 Level Shifter 32 bits Latch 32 bits Shift Register 32 bits D3 4 LP 4 XSCL Voltage Control EI ECL Enable Control EO FR 5 VSS VDD V2 V3 VSSH Shift Register 32 bits Latch 32 bits Level Shifter 32 bits LCD Driver 32 bits 32 33 SEG TEST 63 ■ PIN CONFIGURATION 64 41 65 40 SED1180 80 25 1 24 426 SED1180 Number Name Number Name Number Name Number Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG 9 SEG 8 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 EO D3 D2 D1 D0 XSCL LP FR SEG32 SEG33 SEG34 SEG35 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 VSSH V2 V3 VSS VDD TEST EI ECL SEG31 SEG30 SEG29 SEG28 ■ PIN DESCRIPTION Pin Name Function SEG0 to SEG63 Outputs to segment pins of LCD. Output level changes at each latch pulse XSCL Data shift clock input: display data is shifted in on the falling edge of this signal. LP Latch pulse for displayed data, falling edge trigger: display data is latched on the LP falling edge. falling edge of this signal. FR LCD AC-drive signal EI Active high daisy chain enable input EO Active high daisy chain enable output ECL Daisy chain enable clock: the daisy chain enable is propagated on the falling edge of this clock. D0 to D3 4-bit display data input TEST Test output VDD, VSS Logic power inputs V2, V3, VSSH LCD drive power inputs VSSH: –14V to –23V VDD ≥ V2 ≥ V3 ≥ VSSH 427 SED1180 ■ ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage (1) Supply voltage (2) Input voltage Symbol Ratings Unit VSS –7.0 to +0.3 V –28.0 to +0.3 V VSS – 0.3 to +0.3 V VSSH V2, V3 VI Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Soldering temperature time Tsol 260°C, 10 sec (at lead) — Notes: 1. All voltage measurements are based on VDD = 0V. 2. V2 and V3 must always satisfy the condition VDD ≥ V2, V3 ≥ VSSH. 3. Exceeding the absolute maximum ratings can result in permanent damage to the device. Functional operation under these conditions is not implied. 4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally stressing the package during board assembly. 428 SED1180 ■ ELECTRICAL CHARACTERISTICS DC Electrical Characteristics • Parameters Supply voltage (1) Supply voltage (2) Symbol (VDD = 0V, VSS = –5.0 V ± 10%, Ta = –20 to 75°C) Condition Rating Unit Min Typ Max VSS –5.5 –5.0 –4.5 V V2 VSSH — VDD V V3 VSSH VSSH — VDD V Recommended VSSH –25.0 — –14.0 V Operable VSSH (see note) –25.0 — –5.0 V HIGH-level input voltage VIH 0.2VSS — VDD–0.3 V LOW-level input voltage VIL VSS–0.3 — 0.8VSS V HIGH-level output voltage VOH IOH = -0.6 ma -0.4 — — V LOW-level output voltage VOL IOL = 0.6 ma — — VSS+0.4 V ILI 0 V ≤ VI ≤ VSS — 0.05 2.0 µA ILO 0 V ≤ VO ≤ VSS Input leakage current — 0.05 5.0 µA XSCL — — 6.0 MHz Frame signal FR — 1/60 — S Input capacitance CI pF Output leakage current Shift clock Segment output on resistance RSEG Ta = 25°C — 5.0 8.0 VSSH = –20.0 V — 1.9 2.9 VOH = VDD = –0.5 V VOL = VSSH = +0.5 V VSSH = –14.0 V SEG bit VSSH = –9.0 V — 2.4 3.9 — 3.6 7.0 — 11.5 500.0 — 0.05 30 µA — 90 200 µA — 40 80 µA VSSH = –5.0 V Quiescent current IQ VSSH = –25 V, VSSH = –5.5 V, VI = VDD kΩ VSS = –5.0 V, VIH = VDD, VIL = VSS, LP cycle=130 µS, Operating current for the logic Operating current for the LCD ISSO ISSHO FR cycle = 16.7 ms ECL cycle = 13 µS FR cycle = 16.7 ms ECL cycle = 13 µS (continued) 429 XSCL=1.5 MHz, (duty 50%) All data input reversed bit by bit. All output pins are open. VSS = –4.5 V, V2 = –4.0 V, V1 = –16.0 V, VSSH = –20.0 V, VIH = VDD, VIL = VSS, XSCL=1.5 MHz, (duty 50%), all data input reversed bit by bit. All output pins are open. SED1180 • DC Electrical Characteristics (continued) Parameters Symbol Condition Rating Unit Min Typ Max tCLC 166 — — ns Shift clock “H” width tWCLH 63 — — ns Shift clock “L” width tWCLL tDS tDH tWECH 63 — — ns 50 — — ns 30 — — ns See note 4 100 — — ns See note 4 100 — — ns See note 4 50 — — ns See note 4 20 — — ns Enable clock delay time tWECL tEDS tEDH tEDR See note 4 –10 — — ns Enable clock setup time tECS See note 4 70 — — ns tWLPH tWLPL tLT See note 2 110 — — ns 220 — — ns 100 — — ns Shift clock cycle Data setup time Data hold time Enable clock “H” width Enable clock “L” width Enable data setup time Enable data hold time Latch pulse “H” width Latch pulse “L” width Latch timing Latch hold time Latch pulse data setup time Latch pulse data hold time Permissible frame signal delay Input signal rise time Input signal fall time Enable output delay tLH tLDS tLDH tDFR tr 0 — — ns See notes 3 & 4 140 — — ns See notes 3 & 4 50 — — ns –500 — 500 ns — — See note 4 — — — See note 4 — 20 — 150 ns tf tPD See note 4 Notes: 1. While the drive is guaranteed to operate without error within this voltage range, the output resistance of the segment drivers will be higher than that in the recommended operating range. It is suggested that the drive capability of the driver under these conditions is tested using the target panel. 2. tWLPH = 160 ns (min) when LP is used as EI data. 3. tWLPH = 250 ns (min) when EO is reset by LP. 4. Applies to the SED1180F only. 5. tr, tf < (tCLC – tWCLH – tWCLL) / 2 and tr, tf ≤ 50 ns. 430 SED1180 ■ AC ELECTRICAL CHARACTERISTICS Data I/O Timing • 1 line period FR 1 2 3 4 61 62 63 64 1 2 LP Enlarged FR LP EI Valid Valid Valid ECL XSCL 1 D0 to D3 16 1 2 2 3 15 16 1 n 2 15 EO VIH = 0.2 x VSS VIL = 0.8 x VSS FR tWLPH tFR LP tLDH tLDS tWLPL tLT EI tLH Valid tEDS tr tEDH tr tWECH tWECL ECL tEDR tECS tCLC XSCL tWCLH tDS D0 to D3 Valid Valid tDC EO tWCLL tDH VIH VIL 431 16 1 SED1180 • Segment Drive Timing LP VIL VIH VIL FR tLPSD tFRSU Vn –0.5V Vn +0.5V SEG out VDO ,V2 V2, V3, VSSH VIH = 0.2VSS; VIL = 0.8VSS (VDD = 0V, VSS = –5.0 V ±10%, Ta = –20 to 75°C) Parameters Symbol Condition LP-SEG output delay time tLPSD FR-SEG output delay time tFRSD Rating Unit Min Typ Max VSSH=–14.0 to –25.0 V, — — 4.5 µs CL= 100 pF — — 4.5 µs 432 SED1180 ■ TYPICAL SYSTEM CONNECTION (64 × 640 pixels, 1/64 duty ratio) *2 LP YSCL YD YDIS SED1190 0 LCD PANEL COM 64 × 640 Full Dot Graphic Display VSSH FR YSCL LAT DIN INH 63 0 VSS VDD + R V1 + R V2 VDD, V1, V4, VSS + SEG 0 63 5R SEG 0 63 191 SED1180 SED1180 2 3 EI EO FR LP EO EI FR LP 576 SEG 0 63 1 EI 4 127 128 SED1180 C C + 63 64 C R + R *1 C 100Ω V4 VDD, VSS V2, V3 4 SED1180 10 EO EI FR LP 100Ω 4 4 2 4 2 4 *1 2 4 Notes: 1. Current limiting resistors 2. Bypass VSS and VSSH with capacitors of at least 0.01 µF 433 EO FR LP VSSH FR LP ECL, XSCL D0 to D3 SEG 0 63 V3 + 639 2 4 SED1180 THIS PAGE INTENTIONALLY BLANK 434