SED1330 CMOS GRAPHIC LCD CONTROLLER This part is replaced by SED1335. Some pin differences between SED1330 and SED1335 exist. Please check SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330. ■ DESCRIPTION The SED1330 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters (also an external CGROM can be supported). The SED1330 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family. The controller supports a set of rich commands that will allow the user to create a layered display of characters and graphics. Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost, medium-speed SRAM can be used. ■ FEATURES low-power graphic and character display • CMOS controller MPU interface is compatible with both • Selectable the Intel family and the Motorola family • Smooth scrolling support: • • • Programmable cursor • Internal character generator ROM • Supports external character generator ROM: • Horizontal and vertical scroll Scrolling of selected areas of the display Multimode display: 2 layers of overlapping character and graphics 3 layers of overlapping graphics Selectable display synthesis: Inverse video Flashing display, cursor on/off/blink Under and bar cursor, block cursor Simple animation • • • • 8 × 8 or 8 × 16 pixel characters Allows mixing of ROM and RAM character sets Supports 64K bytes of memory: 2 of 32K × 8 100ns SRAM or 8 of 8K × 8 100ns SRAM Display duty .................................. 1/2 to 1/256 Low power dissipation ................ 5mA (typical) 0.05µA (typical), standby Logic power supply ........................ 4.5 to 5.5V Package ................ Plastic QFP5-60 pin (FBA) Plastic QFP6-60 pin (FBB) ■ SYSTEM BLOCK DIAGRAM DATA CPU CONTROL SED1330F 68xx 80xx SRAM 125 LCD SED1330 ■ BLOCK DIAGRAM External CG ROM VRAM Interface Display Address Controller Refresh Address Counter LCD Controller Dot Counter CG ROM Layered Display Controller OSC XD D0 to D7 A0, CS RD, WR RES MPU Interface SEL1 SEL0 XD0 to XD3 LP, WF YSCL,YDIS I/O Register XG Cursor Address Controller LCD VD0 to VD7 VR/W VCE VA0 to VA15 CG RAM XSCL, XECL Video RAM 50 60 1 Index 5 6 45 40 SED1330FBA 10 30 29 15 20 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2 45 46 31 30 SED1330FBB Index 60 1 16 15 VA5 VA4 VA3 VA2 VA1 VA0 VR/W VCE NC RES NC NC RD WR SEL2 D2 D3 D4 D5 D6 55 D7 XD3 XD2 XD1 XD0 XECL XSCL VSS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 XD CS A0 VDD D0 D1 VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2 XG SEL1 SEL2 WR RD NC NC RES NC VCE VR/W VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 ■ PINOUT 126 XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 SED1330 ■ PIN DESCRIPTIONS Pin No. Pin Name I/O Functions SED1330FBA SED1330FBB XG 54 17 I Oscillator terminal XD 55 18 O Oscillator terminal VDD 58 21 +5V Power supply VSS 13 36 GND (0V) Power supply 53 • 52 16 • 15 I 22 to 29 I/O SEL1, 2 59 to 60 D0 to D7 1 to 6 MPU interface format selection Data bus A0 57 20 I Data type selection RD 50 13 I WR 51 14 I CS 56 19 I Chip select RES 47 10 I Reset O VRAM address bus 80 series Read strobe signal 68 series “E” clock 80 series Write strobe signal 68 series R/W signal 43 to 30 6 to 1 28 to 27 59 to 50 VD0 to VD7 26 to 19 49 to 42 I/O VRAM data bus VR/W 44 7 O VRAM R/W signal Memory control signal VA0 to VA15 VCE 45 8 O XD0 to XD3 10 to 7 33 to 30 O Dot data output bus to X driver XSCL 12 35 O Dot data shift clock for X driver XECL 11 34 O Chip enable shift clock for Y driver LP 14 37 O Dot data latch pulse WF 15 38 O Frame signal YSCL 18 41 O Scan data shift clock for Y driver YD 17 40 O Scan data output YDIS 16 39 O Power down signal when display OFF NC: No Connection ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • Parameter Supply voltage (VSS = 0V) Symbol Ratings Unit V VDD –0.3 to 7.0 Input voltage VI –0.5 to VDD+0.5 V Power dissipation PD 300 mW Operating temperature Topr –20 to 75 °C Storage temperature Tstg –60 to 150 °C Soldering temperature and time Tsol 260°C, 10s (at lead) — 127 SED1330 • DC ELECTRICAL CHARACTERISTICS Parameter (VDD = 5V±10%, VSS = 0V, Ta = –20 to 75°C) Symbol Condition Min Typ Max Unit Operating voltage VDD 4.5 5.0 5.5 V Register data retention voltage VOH 2.0 — 6.0 V High level input voltage VIHT D0 to D7, A0, CS, RD, WR, 2.2 — VDD+0.3 V Low level input voltage VILT VD0 to VD7, IOH= –5.0mA, –0.3 — 0.8 V T T L SCHMITT C M O S High level output voltage VOHT IOL=5.0mA, VR/W, VCE, 2.4 — — V Low level output voltage VOLT REF — — 0.4 V High level input voltage VIHC IOH=1.6mA, IOL= –1.6mA, 0.8VDD — — V Low level input voltage VILC SEL1, 2, SYNC, YD, XD0 to — — 0.2VDD V High level output voltage VOHC XD3, XSCL, XECL, LP, FR, VDD–0.4 — — V Low level output voltage VOLC YSCL, YDIS, OSC1, OSC2 — 0.4 Positive trigger threshold voltage VT+ Negative trigger threshold voltage VT– Input leakage current ILI Output leakage current ILO Average operating current IDDA Standby current IDDS Oscillation frequency fOSC External clock frequency fCLK Feed back resistance RES * VI=VDD or VSS fOSC=10MHz, No load (No external V-RAM) XG=CS=VDD AT X’tal XG, XD Rf * RES input pulse should be longer than 1.0ms. VL5 should be OFF when RES is “L”. 128 — V 0.5VDD 0.7VDD 0.8VDD V 0.2VDD 0.3VDD 0.5VDD V µA — 0.05 2.0 — 0.10 5.0 µA — 8 12 mA — 0.05 20 µA 1.0 — 10.0 MHz — — 10.0 MHz 0.5 1.0 5.0 MΩ SED1330 • ° AC CHARACTERISTICS System Bus READ/WRITE Timing I (8080) tAH8 A0, CS tAW8 tCYC tCC WR, RD tDS8 tDH8 D0~D7 (WRITE) tACC8 tOH8 D0~D7 (READ) Signal A0, CS WR, RD D0 to D7 Parameter Address hold time Address setup time System cycle time Control pulse width Data setup time Data hold time RD access time Output disable time Symbol tAH8 tAW8 tCYC tCC tDS8 tDH8 tACC8 tOH8 Rating Min Max 10 — 30 — *1 — 220 — 120 — 10 — — 120 10 50 Unit ns ns ns ns ns ns ns ns *1. tCYC = 2tc + tCC + tCEA + 75 > tACV + 245 ................ Memory control/movement control commands. = 4tC + tCC + 30 .............................................. All other commands. 129 Remark CL = 100 pF + 1TTL SED1330 ° System Bus READ/WRITE Timing II (6800) tCYC6 E tAW6 tEW R/W tAH6 A0, CS tDS6 tDH6 D0~D7 (WRITE) tACC6 tOH6 D0~D7 (READ) Signal Parameter A0, CS, R/W D0 to D7 E System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulse width Symbol tCYC6*1 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW Rating Min Max *2 — 30 — 10 — 120 — 10 — 10 50 — 120 220 — Unit ns ns ns ns ns ns ns ns *1. tCYC6 means a cycle of (CS.E) not E alone. *2. tCYC6 = 2tc + tEW + tCEA + 75 > tACV + 245 .............. Memory control/movement control commands. = 4tC + tEW + 30 ............................................ All other commands. 130 Remark CL = 100 pF + 1 TTL SED1330 ° Display Memory READ Timing tC EXTφO tW tCE tW VCE tCYR VA0~VA15 tASC VR/W tAHC tRCS tRCH tCE3 tCEA tOH2 tACY VD0~VD7 Signal EXT φ0 VCE VA0 to VA15 VR/W VD0 to VD7 Parameter Clock cycle VCE high-level pulse width VCE low-level pulse width Read cycle time VCE address setup time (fall) VCE address hold time (fall) VCE read cycle setup time (fall) VCE read cycle hold time (fall) Address access time VCE access time Output data hold time VCE data off time Symbol tC tW tCE tCYR tASC tAHC tRCS tRCH tACV tCEA tOH2 tCE3 *1. tCYR = 3tC *2. tACV = 3tC – 120 *3. tCEA = 2tC – 120 131 Rating Min Max 100 — tC – 40 — 2tC – 40 — *1 — tC – 45 — 2tC – 40 — tC – 45 — tC/2 – 35 — — *2 — *3 0 — 0 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1TTL SED1330 ° Display Memory WRITE Timing tC EXTφO tW tCE VCE tASC tCA tAHC VA0~VA15 tCYW tAS tWSC tWHC tAH2 VR/W tOH2 tOSC tOHC VD0~VD7 Signal Parameter Symbol EXT φ0 Clock cycle VCE HIGH-level pulse width VCE LOW-level pulse width Write cycle time VCE address hold time (fall) VCE address setup time (fall) VCE address hold time (rise) VR/W address setup time (fall) VR/W address hold time (rise) VCE write setup time (fall) VCE write hold time (fall) tC tW tCE tCYW tAHC tASC tCA tAS tAH2 tWSC tWHC VCE data input setup time (fall) VCE data input hold time (fall) VR/W data hold time (rise) tDSC tDHC tDH2 VCE VA0 to VA15 VR/W VD0 to VD7 * Lines VD0 to VD7 are latched. 132 Rating Min Max 100 — tC – 40 — 2tC – 40 — 3tC — 2tC – 40 — tC – 55 — 5 — 0 — 15 — tC – 55 — 2tC – 40 tWSC – 10 2tC – 30 10* — — — 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1TTL SED1330 ° LCD Control Timing ROW NO LP 1 frame period YD WF YSCL 1 line period WF YSCL ROW64 ROW1 ROW2 LP XSCL XD0~XD3 XECL tr XSCL tWX tf tDS tCX tDH XD0~XD3 tWL LP tL1 tL2 tS2 XECL tS1 tWXE WF(B) YD tDf YSCL tLD tDHY tWY 133 SED1330 Signal Parameter Symbol EXT φ0 Clock cycle Rising time Falling time Shift clock cycle time XSCL clock pulse width X-data hold time X-data setup time Latch data setup time LP signal pulse width XECL setup time XECL data hold time Enable setup time Enable delay time XECL clock pulse width Time allowance of WF delay LP delay time against YSCL YSCL clock pulse width Y-data hold time tC tr tf tCX tWX tDH tDS tLS tWL tL1 tL2 tS1 tS1 tWXE tDF tLD tWY tDHY XSCL XD0 to XD3 LP XECL WF YSCL YD 134 Rating Min 100 — — 4tC tCX2 – 80 tCX2 – 100 tCX2 – 100 tCX2 – 100 tCX4 – 80 tCX3 – 100 tC – 30 tC – 30 tC – 30 tCX3 – 80 — tCX4 – 100 tCX4 – 80 tCX6 – 100 Max — 35 35 — — — — — — — — — — — 100 — — — Unit Remark ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 5.0V ± 10% CL = 150F SED1330 ° Oscillator Timing VDD tOSP CLO tOSS YDIS Power ON Sleep period tRCL tFCL EXT 0O tWL tWH tCL Signal CLO EXT φ0 Parameter Time to stable CLO output after power-ON Time to stable CLO after sleep OFF External clock rise time External clock fall time External clock high-pulse width External clock low-pulse width External clock cycle Symbol Min Rating Max Unit tOSP — 3 ms tOSS — 1 ms tRCL tFCL tWH tWL tCL — — *1 *1 100 15 15 *2 *2 — ns ns ns ns ns *1. (tC – tRCL – tFCL) × 475/1000 < tWH, tWL *2. (tC – tRCL – tFCL) × 525/1000 > tWH, tWL 135 Remark RES = H 20 pF SED1330 ■ EXAMPLE OF APPLICATION 8.0MHz XD G1 A1 to A7 A0 Chip Selector CS MPU IORQ D0 to D7 D0 to D7 RD WR RESET VA13 to VA15 VR/W VA0 to VA12 A B C Y7 Y6 Y0 CS7 CS6 CS0 VA12 A0 to A12 WE A0 to A12 WE A0 to A11 SRM2064 CS1 (RAM1) CS2 SRM2064 CS1 (RAM7) CS2 2732 (EXT.CG) OE D0 to D7 CE D0 to D7 OE D0 to D7 OE VD0 to VD7 FR EI SED1180F VL3 FR EI SED1180F VL4 Vreg VL5 (X Driver) 136 FR EI SED1180F LP XSCL ECL D0 to D3 (Y Driver) VL2 LP XSCL ECL D0 to D3 VL1 LCD LP XSCL ECL D0 to D3 SCI7661 Poff X2 YSCL DI YDIS FR LAF SPU SED1190F XECL XSCL LP WF YDIS YD YSCL RESET RD WR RES XD0 to XD3 SED1330F A0 HC138 XG SED1330 ■ CHARACTER CODE TABLE (BUILT-IN CHARACTER GENERATOR) 0 1 2 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 2 3 4 5 6 7 A B C D 1 123 123 Note: 123 123 means all dots of 6 × 8 matrix are on. 137 E F THIS PAGE INTENTIONALLY BLANK 138