TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com High-Efficiency Integrated Dimming LED Lighting Controller Check for Samples: TPS92070 FEATURES DESCRIPTION • • • • • • The TPS92070 is an advanced PWM controller ideal for use in low-power, offline, LED lighting applications. The integrated dimming interface circuit of the TPS92070 features a non-dissipative dimmer trigger control circuit. The TPS92070 controller provides DC LED current with no photometric ripple effects. The DC current also results in higher efficacy of the LEDs. The TPS92070 provides exponentially controlled light output based on the external dimmer position. High power factor is achieved with a valley fill circuit. Once a leading-edge dimmer is detected, the TPS92070 sets an output to disable the PFC circuit and thus optimizes driver operation. The LED current sense precision error amplifier implements deep dimming. The TPS92070 current sensing scheme provides tight current regulation and eliminates the need for an optocoupler. The tight current regulation allows for strong color and intensity matching amongst individual bulbs or luminaires. 1 • • • • • • • • • • Advanced Integrated Dimming Interface Non-Dissipative TRIAC Dimmer Management Lamp-to-Lamp Uniformity During Dimming No Low-Frequency Photometric Ripple Exponential Dimming Profile Innovative Secondary-Side Feedback Eliminates Optocoupler Devices LED Current Regulation better than 5% Programmable Minimum LED Current Valley Switching and DCM Operation for Reduced EMI and Improved Efficiency Leading Edge Dimmer Detection Power Factor > 0.8 Cycle-by-Cycle Current Limit Protection Low Start-Up and Standby Currents Integrated PWM MOSFET Driver Thermal Shutdown 16-Pin, TSSOP package APPLICATIONS • • • • LED LED LED LED The TPS92070 also contains a variety of protection features including cycle-by-cycle peak-current limit, overcurrent protection, open-LED (output overvoltage) protection, undervoltage lockout, and thermal shutdown. Light Bulb Replacement Luminaires Downlights Wall Washers 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com APPLICATION DIAGRAM or – + TPS92070 GATE BP TDD VDD PCS GND PGND DTC VZ VD ISO CS SEN COMP MIN LP UDG-11185 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (2) (1) (2) TEMPERATURE RANGE (TJ) PACKAGE PINS –40°C to 140°C Plastic TSSOP 16 TRANSPORT MATERIAL UNITS ORDERABLE NUMBER Tube 70 TPS92070PW Tape and Reel 2000 TPS92070PWR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging ABSOLUTE MAXIMUM RATINGS (1) (2) (3) All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE Supply voltage Input voltages MIN MAX VDD (4) –0.3 25.0 ISO, CS, COMP, LP, MIN, SEN, PCS –0.3 7.0 BP, GATE, TDD –0.3 7.2 VD –1.4 7.0 –0.3 20.0 VZ, DTC (5) VZ (pulse < 1 ms) 5 –0.5 BP Input current DTC 30 Average 16 (6) Lead temperature (10 seconds) (2) (3) (4) (5) (6) mA 5 Operating junction temperature (6) (1) 0 Peak VDD Storage temperature UNITS –40 140 °C –65 150 °C 260 °C These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability All voltages are with respect to GND. All currents are positive into the terminal, negative out of the terminal. VDD clamped at approximately 23 V. See ELECTRICAL CHARACTERISTICS table. VZ clamped at approximately 12.5 V. See ELECTRICAL CHARACTERISTICS table. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 3 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C. MIN TYP MAX UNIT VDD Input Voltage 9 21.5 V VZ Current 1 100 μA RMIN Resistor from MIN to GND 25 75 kΩ RVD1 Valley detect resistor from AUX winding to VD pin 50 200 kΩ CVZ VZ bypass capacitor 4.7 nF CBP BP capacitor CVDD VDD capacitor (1) CVDD,BP VDD bypass capacitor, ceramic (1) (2) 1 (2) 0.47 1 μF 10×CBP7 4.7 μF μF 0.1 RMIN values greater than 75K will produce lower minimum current values. However accuracy of the minimum current will degrade, and there may be flickering at very low values of Imin. If a ceramic capacitor is used for CVDD then this capacitor is not needed. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MAX UNIT ESD Rating, Human Body Model (HBM) 1.5 kV ESD Rating, Charged Device Model (CDM) 500 V ELECTRICAL CHARACTERISTICS Unless otherwise stated, −40°C < TA < 125°C, TJ = TA, VVDD = 12 V, GND =0 V, IVZ = 50 μA, RMIN = 71.5 kΩ, CVDD = 4.7µF, CBP = 1 µF, CLP = 220nF PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1.0 10 μA 11.5 12.5 13.5 V 134 240 BIAS and STARTUP ISTART VZ startup current VVDD = 7 V, Measured IVZ VVZ VZ voltage VVDD = 7 V, 15 μA < IVZ < 100 μA VDD startup current VVDD = 7.5 V Standby current VLP = 0 V, VSEN = 0 V Switching current fGATE = 138 kHz, GATE – unloaded VVDD(uvlo) VDD UVLO threshold Measured at VDD (falling) VVDD(ovp) VDD clamp and OVP Measured at VDD (rising) RVZ(ovp) OVP VZ discharge resistance VVDD = VVDD(ovp), VZ = 3 V VBP BP Regulation voltage 9 V < VVDD < 19V, IBP = –0 μA IVDD 750 1500 1880 2500 7 7.88 8.4 21.5 23.5 25 4.8 μA V V kΩ 6.7 7 7.2 V Measured at SEN (rising) 4.75 5 5.25 Measured at SEN (falling) 0.9 1 1.10 5.75 6 6.25 V 40 100 nA 16 20 25 kΩ VDTC = 3 V, VSEN (rising), VSEN < VSEN(hi) 100 156 300 Ω VSEN < VSEN(lo) 100 156 300 Ω DIMMER TRIGGER CIRCUIT VSEN(hi) Dimmer sense thresholds VSEN(lo) VSEN(clamp) SEN Clamp voltage ISEN = 100 µA IDTC(lkg) DTC to PGND leakage current VDTC = 12 V, VSEN > VSEN(hi) VDTC = 3 V, VSEN (falling), VSEN(lo) < VSEN < VSEN(hi) RDTC(pgnd) DTC to PGND resistance V CURRENT SETPOINT VMIN MIN regulation voltage 2.5 ROUT(lp) LP output resistance 500 VOH(lp) LP Maximum voltage level VOL(lp) 4 LP Minimum voltage level kΩ VSEN = 6 V, ILP = 0 μA 2.9 3 3.1 V VSEN = 0 V, ILP = 0 μA –0.02 5 0 0.025 V Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, −40°C < TA < 125°C, TJ = TA, VVDD = 12 V, GND =0 V, IVZ = 50 μA, RMIN = 71.5 kΩ, CVDD = 4.7µF, CBP = 1 µF, CLP = 220nF PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIER VIOS Input offset voltage 5 mV < VCS < 100 mV, VCOMP = 3 V VCOMP(min) Minimum COMP clamp voltage VCS = 150 mV, VLP < 3 V VCOMP(max) Maximum COMP clamp voltage VCS < 100 mV, VLP > 2.1 V VCS(min) Minimum CS reference voltage VLP = 0, RMIN = 71.5 kΩ, TA = 25°C VCS(max) Maximum CS reference voltage VLP > 2.1 V, TA = 25°C ±500 μV 1.45 1.53 1.60 3.6 3.7 3.8 V 2.835 3.15 3.465 mV 97 100 103 mV V MODULATION fCLAMP(max) Maximum frequency clamp Measured at GATE, VCOMP = 3.5 V, TA = 25°C 132 138 146 fCLAMP(min) Minimum frequency clamp Measure at GATE, VCOMP = 1.53 V, VVD = 0 V, TA = 25°C 10 20 30 kHz VALLEY DETECT Measured when GATE is high, IVD = –15 μA –560 Measured when GATE is low and VD is falling –125 VDCLAMP VD clamp mV VVD(en) VD enable threshold Minimum peak of resonant valley, VCOMP = 1.8 V VVD(zc) Zero-crossing detect threshold Measured at VD (falling) 80 100 135 mV tVD(vw) Valley wait timer VCOMP > VMINF_DET, VVD = 0 V, wait time for next PWM pulse with zero-crossing detected 10 12.7 14 µs IVD(min) Current required for valley detection 600 mV –50 µA OVERCURRENT PROTECTION VPCS(oc) Over current limit Measure at PCS (rising), VCOMP = 4 V tPCS_G1(oc) Propagation delay Measured between PCS and GATE falling 670 700 750 mV 10 64 190 ns 180 220 300 ns 600 650 PWM COMPARATOR tLEB Leading edge blanking VPWM(max) VPWM VCOMP = VCOMP(max) PWM thresholds VPWM(min) tPCS_G1(cl) Measured at GATE, VCOMP = 3.5 V Propagation delay VCOMP = 3.5 V 460 500 550 Measured at PCS rising, COMP ≤ 2 V 40 65 80 Measured between PCS and GATE falling 10 54 120 ns 240 270 350 Ω 6.7 7 7.2 –0.01 0 0.01 mV LED ISOLATED CURRENT SENSE RISO(pd) Pull down resistance GATE is high PWM OUTPUTS VGATE(oh) Output voltage high VGATE(ol) Output voltage low tFALL(pwm) Fall time CGATE = 1 nF, TA = 25°C 43 70 tRISE(pwm) Rise time CGATE = 1 nF, TA = 25°C 105 155 Measured at GATE V ns TRIAC DIMMER DETECTION VTDD(oh) Output voltage high VTDD(ol) Output voltage low tFALL(tdd) Fall time tRISE(tdd) Rise time tDLY_1V_5V Minimum delay from 1V to 5V SEN signal transitions for no dimmer detection Measured at TDD 6.7 7 7.2 –0.01 0 0.01 CTDD = 1 nF 120 190 CTDD = 1 nF 130 220 135 170 105 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 V ns µs 5 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM TPS92070 VDD + OVP 23 V TSD 155°C 140°C UVLO + 8V GND Valley Valley Detect VZ VD Control to Period Translator 12.5 V VDD 7V 1V + + S Q SEN BP R 6V 7V Q + PWM and Fault Logic 5V GATE 7V DTC TRIAC Dimmer Detection TDD PCS + 20 kW GND OCP PWM Comparator 160 W LP Set-Point Filter Exponential Dimming Control 0.7 V VPWM Control to Peak Current Translator + ISO From PWM Similar to GATE ISET COMP 2.5 V + + 2.5 V CS + VIOS < 500 mV MIN RMAX 100 kW R GM 500 W UDG-11186 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com TPS92070 PW (TSSOP) PACKAGE (TOP VIEW) BP 1 16 GATE VDD 2 15 TDD GND 3 14 PCS VD 4 13 PGND ISO 5 12 DTC CS 6 11 VZ COMP 7 10 SEN LP 8 9 MIN PIN DESCRIPTIONS PIN NAME DESCRIPTION NO. BP 1 Connect a 1-uF ceramic capacitor to GND to bypass the internal voltage regulator. COMP 7 Loop compensation output. Connect the loop compensation components between this pin and GND CS 6 LED current sense feedback and positive input terminal of the error amplifier. DTC 12 Dimmer trigger control input. Connect this pin to thesource of the HV N-channel MOSFET cascode device of the DTC circuit. GATE 16 PWM drive signal output. Connect to flyback power MOSFET. GND 3 Ground for internal circuitry ISO 5 Inverting input of secondary side current sense comparator and isolation transformer buffer. Connect to GND for non-isolated applications. LP 8 Pole for DTC low pass filter. Connect a capacitor to GND to set the response time of the dimming level detection circuit. MIN 9 Minimum current programming input. Connect a resistor to GND to set the minimum LED current. PCS 14 Primary current sense input. Connected to shunt resistor for primary side current sense. PGND 13 Power ground for GATE Driver. Connected to GND SEN 10 Dimmer sense input. An internal window comparator continuously monitors this pin to determine the dimmer setting. TDD 15 TRIAC dimmer detect. Drives bypass FET in Valley Fill PFC when dimmer is detected. For non PFC applications, leave this pin open VD 4 Valley detect input. Connect to the Aux winding through a resistor divider. VDD 2 Provides power to the device. Connect a bypass capacitor directly to GND. See RECOMMENDED OPERATING CONDITIONS for suggested values. VZ 11 Voltage clamp. This pin clamps the maximum voltage on the gate of the external HV DTC N-channel MOSFET. (1) (1) See Application Section for layout recommendations Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 7 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com TYPICAL CHARACTERISTICS Unless otherwise stated, –40°C ≤ TA = TJ ≤+125°C, VVDD = 12 V, GND =0V, IVZ = 50 μA, RMIN = 71.5 kΩ, CVDD = 10 µF, CVZ = 1 nF, CLP = 220 nF 20.4 Minimum Clamp Freqency (kHz) Maximum Clamp Frequency (kHz) 144 142 140 138 136 134 132 130 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 105 103 101 99 97 80 95 110 125 19.4 19.2 19.0 18.8 5 20 35 50 65 Temperature (°C) 80 95 110 125 G000 3.30 3.25 3.20 3.15 3.10 3.05 3.00 −40 −25 −10 G000 Figure 3. Maximum Current Sense Voltage vs. Temperature 8 19.6 Figure 2. Minimum Clamp Frequency vs. Temperature Minimum Current Sense Voltage (mV) Maximum Current Sense Voltage (mV) 107 20 35 50 65 Temperature (°C) 19.8 G000 109 5 20.0 18.6 −40 −25 −10 110 125 Figure 1. Maximum Clamp Frequency vs. Temperature 95 −40 −25 −10 20.2 5 20 35 50 65 Temperature (°C) 80 95 110 125 G000 Figure 4. Minimum Current Sense Voltage vs. Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com APPLICATIONS STARTUP BIAS AND UVLO During powerup when VDD is less than the UVLO threshold of 8 V, the VZ pin is trickle charged with IVZ(start) of approximately 10 μA through the startup-resistor connected to the bulk rectified voltage. As VZ is being charged, VDD tracks VZ (less VGSTH) through the external cascode HV MOSFET (Q1) supplying a VDD startup current of 135 μA. Once VZ reaches the TPS92070 zener clamp regulation level of 12.5 V, the device enters into a stand-by mode during which the dimmer trigger circuit (DTC), set-point filter, 7-V bias regulator, and a minimal amount of housekeeping circuitry is active. The TPS92070 remains in this state until the SEN pin exceeds 5 V indicating that adequate line voltage is present, either through TRIAC firing, or line voltage presence. The typical start-up waveforms are shown in Figure 5. PWM switching GATE 6V LP SEN 0V VDD 12.5 V VZ 0V 7V BP IOUT 0V IMIN 0V UDG-11187 Figure 5. Typical Startup Waveforms for a TRIAC Triggered VIN(ac) Input Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 9 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com DTC and PHASE DETECTION The DTC pin is a current sink which loads the dimmer with approximately 20 mA during the zero-crossing of the AC line to ensure that the TRIAC is reliably triggered. This current sink is switched on when the voltage on the SEN pin is below 5 V. The setpoint filter in conjunction with the SEN and LP pins is used to determine the firing angle of the TRIAC dimmer (if any) connected to the input of the LED driver. An internal window comparator monitors the SEN (dimmer sense input) pin and the resulting duty-cycle is transformed into a voltage at the LP pin using the LP filter. The relation between the TRIAC firing angle and the LP voltage is shown in Figure 6. It illllustrates the conversion of the TRIAC firing angle to LP voltage and exponential dimming control of ISET based on internal control voltage. As the voltage on the LP varies from 0 V to 3 V based on the mapping of 0% to 100% SEN duty-cycle, an internal control voltage is linearly modulated by TPS92070 from 400 mV to 200 mV. Low-Pass Filter Voltage (V) 3 1.98 1 0 Internal Control Voltage (mV) 400 Current Sense Voltage (mV) 200 VCS(max) 100 VCS(min) 33% 66% SEN Duty-Cycle UDG-11188 Figure 6. TRIAC Firing Angle vs. Low-Pass Filter Voltage 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com The internal control voltage, VCTRL is clamped to 0.4 V for LP < 1 V and clamped to 0.2 V for LP > 1.98V . As the control voltage is linearly modulated between 0.4 V and 0.2 V, the current sense reference voltage VCS is exponentially controlled between the pre-set maximum of 100 mV and the externally programmed minimum limit of VCS_MiN. The current setpoint level, VCS_MiN is programmed by RMIN. 225 VCS(min ) = RMIN (1) The exponential control of the set-point current extends the dimming control range and enables up to two decades of LED current-programming between the VCS(min) and VCS(max) = 100 mV levels. LED CURRENT SENSE The secondary-side LED current is sensed using the CS pin and tightly regulated using the low-offset (500 μV) transconductance amplifier. The transconductance (gM) of the amplifier is internally set to approximately gM = 1/500 S. In the direct current-sense mode (non-isolated), the ISO pin is connected to GND. In the isolated-mode, the secondary-side LED current is sensed using a small transformer with the secondary of the transformer connected between CS and ISO pins as shown in Figure 7. The ISO pin has a switched pull-down resistance of 270 Ω. CS VP ISO R DS(on) 270 W GATE UDG-11189 Figure 7. Isolated Current Sense MODULATION The internal ISET current and RGM sets a reference input for the transconductance current sense amplifier which controls the voltage on the COMP pin. The COMP pin is used for loop compensation. The voltage on the COMP pin modulates the peak of the primary current and the switching frequency (frequency modulation) of the flyback converter. The modulation on the primary current and the switching frequency are shown in Figure 8. The peak of the primary current is modulated by varying the threshold on the PWM comparator. The threshold is modulated from 0.6 V to 0.065 V while the switching frequency varies between 20 kHz and 138 kHz as COMP pin varies from 3.7 V to 2.6 V. The maximum COMP pin voltage is clamped at 3.7 V allowing the maximum cycle-by-cycle peak current limit PWM threshold to be 0.6 V. The switching frequency is linearly modulated from 138 kHz to 20 kHz with the PWM threshold clamped at 0.065 V as the COMP pin varies from 2.6 V to 1.63 V. The minimum frequency is clamped at 20 kHz and TPS92070 enters the minimum frequency detect state for COMP <1.6 V. The minimum voltage on the COMP is clamped at 1.53 V. The PWM threshold is related to the COMP pin voltage as shown in Equation 2 and Equation 3. For 2.6 ≤ VCOMP ≤ 3.7, - 2.5 V VPWM = COMP 2 (2) For VCOMP < 2.6 V, VPWM = 0.065 (3) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 11 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com tPERIOD tPERIOD(max) tPERIOD(min) PWM Threshold Voltage VPWM(max) VPWM(min) 1.63 2.6 VCOMP(max) Loop Compensation Voltage (V) UDG-11194 Figure 8. Switching Period and PWM Threshold Modulation Based on COMP pin Voltage PRIMARY CURRENT SENSE The primary current is sensed by monitoring the voltage developed across an external current-sense resistor connected between the source of the external HV MOSFET and PGND. The PCS pin is used for monitoring the voltage and it is then compared with the PWM threshold (VPWM). The PWM comparator has a leading-edge blanking time of 220 ns to avoid any false-tripping of the comparator due to capacitive charge spikes on the PCS pin. The GATE output is pulled low once the PCS pin reaches the PWM threshold. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com VALLEY DETECT TPS92070 ensures that the flyback converter always operates in either DCM or QR mode of operation and initiates a new PWM switching cycle only after the energy in the flyback transformer is completely reset to zero. This is accomplished by monitoring the auxiliary winding waveform using a resistive divider connected to the VD pin. The TPS92070 initiates a new switching cycle based on the following conditions: • For normal operation with 1.63 V ≤ VCOMP ≤ 3.7 V, a new PWM switching cycle is initiated when the internal timer tPERIOD has expired and the next valley is detected. The VD pin must go below 100 mV (VVD(zc)) prior to valley detection to enable the valley detector circuit. • In the minimum frequency clamp state when VCOMP < 1.63 V, the switching period is fixed at tPERIOD(max) (corresponding to fCLAMP(min)) and the valley detector is disabled. • The relationship of tPERIOD to the switching frequency is shown in Equation 4 and Equation 5. 1 fCLAMP(max ) = tPERIOD(min ) (4) fCLAMP(min ) = 1 tPERIOD(max ) (5) By turning on the flyback power switch at the resonant valley, the switching losses are reduced thereby enabling higher efficiency. The voltage at the VD pin is clamped at –0.56 V during the negative excursions on the AUX winding when GATE is high. When GATE is low and during the resonant valley detection, the VD pin is clamped at –0.2 V. The interface to the VD pin to the AUX winding is shown in Figure 9. The TPS92070 requires that the positive peak of the resonant ring at the VD pin is higher than 0.6 V (VVD(en)) to ensure that the valley-detect circuit is enabled for detection on the falling edge when VCOMP > 1.63 V. Hence, RVD2 need to be selected in such a way that this condition is met for all AUX voltages when VCOMP > 1.63 V. A current IVD(min) of at least 50 µA must be drawn from the VD pin when the GATE is high to ensure proper valley detection. This requirement determines the value of RVD1. The waveforms associated with the valley detect are shown in Figure 10. If the voltage at the AUX winding is not sufficient for valley detection when VCOMP > 1.63 V, an internal valley wait timer of 12.7 µs (tVD(vw)) expires after the tPERIOD times out. The time out of the valley wait timer would initiate a new PWM switching pulse following the 100 mV threshold crossing on the VD pin. SPACER (do not translate) . NP NS (1) Resonanat ring at VD pin (2) Resonant clamp at -0.2 V (3) On-time clamp at -0.56 V NB RVD1 Valley Switching VD (1) Resonant Valley Detect RVD2 (2) tPERIOD Figure 9. Auxiliary Winding Interface to VD tPERIOD Time UDG-11191 (3) UDG-11192 Figure 10. HV MOSFET Drain and VD Waveforms Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 13 TPS92070 SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 www.ti.com TRIAC DIMMER DETECT The TDD pin is used to drive an external by-pass FET that disables valley-fill PFC when a dimmer is detected by TPS92070. The TDD pin is set to logic high state (VTDD(oh) = 7 V) as the part is powered up and if no dimmer is detected by continuously sensing the SEN pin, the TDD pin is then reset to logic low (VTDD(ol) = 0 V). The presence of a dimmer is detected by monitoring the time delay in a window between 1 V and 5 V comparators that are monitoring the SEN pin. If the rise time from 1 V to 5 V is greater than 135 µs for four consecutive half-line cycles, direct connection to the AC line without dimmer is assumed, and the TDD output goes low. Otherwise the TDD pin remains high. If the TDD pin is low and the delay time (tDLY_1V_5V) is detected to be less than 135 µs, for four consecutive half-line cycles, the TDD pin goes high once the SEN pin falls below 1 V indicating dimmer detection. PROTECTION FEATURES Output Over Voltage Protection (OVP) Output (secondary-side) overvoltage protection / open LED detection is achieved by disabling the controller whenever the VDD voltage rises enough to trigger its internal 23 V clamp. Upon OVP detection, GATE is pulled low and the TDD pin is reset to logic-high state. The TPS92070 is disabled and an internal pull-down resistor (RVZ(ovp)) discharges the VZ pin, until the VDD voltage drops below the UVLO threshold when a restart is triggered. Overcurrent Protection (OCP) Overcurrent faults are detected when the PCS pin exceeds the internal 700-mV threshold. Upon the detection of an OCP condition, the GATE signal is pulled low, and the LP pin voltage is reset to 0 V corresponding to the minimum LED output condition. GATE switching and current regulation resumes from the minimum LED light setting once the SEN pin crosses the 5 V. Thermal Shutdown (TSD) TPS92070 is disabled if the junction temperature of the part exceeds approximately 155°C and enters into the restart mode where the VZ pin is discharged until VDD falls below the UVLO threshold. The device stays in this restart mode until the junction temperature falls below approximately 140°C when it resumes normal operation with the light output preset to the minimum setting. PCB Layout Use good layout practices when constructing the PCB. Maintain the location of bypass components close to the pins being bypassed. Route power ground (PGND) separate from signal ground (GND) to keep the high current paths and the small signal paths separate. Connect PGND to GND at a single point, preferably under the device. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS92070 PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS92070PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS92070PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS92070PWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92070PWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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