ETC SMT4004F

SUMMIT
SMT4004
MICROELECTRONICS, Inc.
Distributed Power Hot-Swap Controller
FEATURES
l Programmable Watchdog and Longdog Timers
l Programmable Voltage and Current Monitoring
(0 to 6.4 seconds)
w Monitors 4 independent supplies
l Operates From Any One of Four Supply Voltages
w Programmable Host-side Under- and OverVoltage Thresholds
l Nonvolatile Fault Register
w Records Source of Any Interrupt
w Programmable Card-side Under-Voltage
Monitors
w Readable in “Dead Board” Environment
w Programmable Card-side Circuit Breaker
Delay and QuickTrip™ Threshold Levels
l All Communications to Configuration Registers
and Memory Array are via 2-wire Serial Interface
l Programmable Card-side Trakker Function
w Programmable Slew Rate Control
w Guarantees and Enforces Supply Differential
Tracking
FUNCTIONAL BLOCK DIAGRAM
PWR_ON FORCE_SD SEATED1# SEATED2#
33
11
10
27
MR# IRQ_CLR#
5
6
UV_OVERRIDE 12
7
IRQ#
13 RST1#
VO1 20
CB1 37
VI1 41
VO2 21
CB2 36
VI2 40
14 RST2#
SUPPLY
MANAGER
#1
RESET &
STATUS
OUTPUT
CONTROL
LOGIC
16 RST4#
3
CROWBAR
25 CBFAULT
SEQUENCE
ENABLE
LOGIC
SUPPLY
MANAGER
#2
15 RST3#
26 HEALTHY#
32 VGATE1
31 VGATE2
VO3 22
CB3 35
VI3 39
VO4 23
CB4 34
VI4 38
CHARGE
PUMP &
VGATE
CONTROL
SUPPLY
MANAGER
#3
30 VGATE3
29 VGATE4
28 VGG_CAP
24 ENABLE
TRAKKER
LOGIC
SUPPLY
MANAGER
#4
9
TRKR_IRQ#
48 WLDI
TIMER
LOGIC
POWER
SUPPLY
ARBITRATION
1
LDO#
2
WDO#
4
1.25VREF
43 A0
MEMORY
& 2-WIRE
BUS
INTERFACE
44 A1
45 A2
46 SDA
47 SCL
42
8
VDD_CAP PGND
18
19
17
DGND
AGND
PGND
2049 BD 2.1
©SUMMIT MICROELECTRONICS, Inc., 2000 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com
Characteristics subject to change without notice
2049 2.2 9/13/00
1
SMT4004
DESCRIPTION
The SMT4004 is a fully integrated programmable voltage
manager IC, providing supervisory functions and tracking
control for up to four independent power supplies. The
four internal managers perform the following functions:
Monitor source (bus-side) voltages for under- and overvoltage conditions, monitor each supply for over-current
conditions, monitor back end (card-side) voltages for two
staged levels of under-voltage conditions, insure power to
the card-side logic tracks within the specified parametric
limits, and provide supply status information to a host
processor.
The SMT4004 incorporates nonvolatile programmable
circuits for setting all of the monitored thresholds for each
manager. Individual functions are also programmable
allowing interrupts or reset conditions to be generated by
any combination of events. Because of a proprietary
EEPROM technology that it employs it is also able to store
fault conditions as they occur. In the case of a catastrophic
failure the fault is recorded in the registers and then can be
read for analysis.
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
WLDI
SCL
SDA
A2
A1
A0
VDD_CAP
VI1
VI2
VI3
VI4
CB1
48-Pin TQFP
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
CB2
CB3
CB4
PWR_ON
VGATE1
VGATE2
VGATE3
VGATE4
VGG_CAP
FORCE_SD
HEALTHY#
CBFAULT
RST1#
RST2#
RST3#
RST4#
PGND
DGND
AGND
VO1
VO2
VO3
VO4
ENABLE
13
14
15
16
17
18
19
20
21
22
23
24
LDO#
WDO#
CROWBAR
1.25VREF
MR#
IRQ_CLR#
IRQ#
PGND
TRKR_IRQ#
SEATED1#
SEATED2#
UV_OVERRIDE
2049 PCon 2.1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....................... -55°C to 125°C
Storage Temperature ............................ -65°C to 150°C
Lead Solder Temperature (10 secs) ................... 300 °C
Terminal Voltage with Respect to GND:
V0, V1, V2, and V3 ........... -0.3V to 6.0V
All Others ........................ -0.3V to 6.0V
2
*COMMENT
Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Parameter
Notes
Min.
VI
Supply voltages VI1 through VI4
Highest VI (≥2.7V) powers the
SMT4004
2.7
IDD On
IDD Off
Power supply current
PWR_ON and ENABLE active
Programmable VI input threshold
8-bit resolution, 20mV/bit
range
VIHYS
OV/UV trip hysteresis
VQCB
VREF
VVG On
VVG Off
IVG
SRVG
Quick-trip voltage
1.25VREF output voltage
VGATE drive output voltage
OVHYS
Programmable.
Set by Register R1B,
data bits D1 & D0,
respectively
Programmable.
Set by Register R1A,
data bits D7 & D6
(e.g.), respectively
Input low voltage
VOL
Open drain outputs
Crowbar output pulse width
V
3
mA
0.1
mA
6.0
V
25
mV
30
mV
0
25
µs
0
1
50
µs
1
0
100
µs
1
1
200
µs
0
0
Off
0
1
75
mV
1
0
100
mV
1
1
150
mV
1.23
1.25
1.27
V
14
16
V
VGSINK = 1mA
0
0.4
V
80
µA
0
0
100
V/s
0
1
250
V/s
1
0
500
V/s
1
1
1000
V/s
100
mV
VO pins, delta differential
allowed
8-bit resolution, 20mV/bit
0.9
OV input hysteresis
VIL
5.5
MOSFET switches On
VGATE output voltage slew rate
Input high voltage
Units
0
RLOAD = 2kΩ
Programmable.
Set by Register R10,
data bits D3 & D2 or
D1 & D0, respectively
VIH
tCROW
20
MOSFET switches On
Programmable card-side voltage
threshold range
Max.
10
VGATE drive output current
SRDELTA TRAKKER slew differential
POVT
0.9
Circuit breaker trip voltage
CBDELAY Over-current filter
1
ENABLE inactive
PVIT
VCB
Typ.
6.0
10
V
mV
VI = 2.7V
0.9 × VI
VI
V
VI = 5V
0.7 × VI
VI
V
VI = 2.7V
–0.1
0.1 × VI
V
VI = 5V
–0.1
0.3 × VI
V
ISINK = 2mA
0
0.4
V
2.5V min. into 1kΩ
4
7
µs
5
2049 Elect Table 1.0
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
3
SMT4004
PIN DESCRIPTIONS AND DEVICE OPERATION
THE TRAKKER SUPPLY VOLTAGES
SUPPLY MANAGERS
The VI inputs of all four supply managers are diode ORed
and tied to the device's internal VDD node. The TRAKKER
will use the highest VI input for its supply voltage. At least
one VI input must be at or above 2.7V for proper device
operation.
The electrical placement of the SMT4004 on a printed
circuit card is such that it separates the host power supply
and any on-board DC-to-DC converters (or LDOs) from
the backend circuitry such as multiple DSPs, microprocessors and associated glue logic. The host supplies, and
any other regulated voltages that will be “switched” by the
device, are referred to as bus-side voltages. The voltages
that are on the backend circuitry side of the switches are
referred to as card-side voltages.
VDD_CAP — Charge storage connection for the chip's
internal power suply. For most applications a 10µF
capacitor should be connected to his pin.
VGG_CAP — This pin should be tied to a capacitor to be
charged by the charge pump. The capacitor should be of
sufficient size so as to provide current to the VGATE
outputs under varying load conditions.
PGND — Power ground
The four supply manager blocks are identical. Each
contains three primary functional blocks: the first monitors
the bus-side voltages, the second monitors the card-side
voltages, and the third monitors over-current conditions
for that particular supply.
DGND — Digital Ground
BUS-SIDE MANAGEMENT
AGND — Analog Ground
Figure 1 illustrates the functional blocks of the four supply
managers. Each manager block can be independently
enabled or electrically removed from the device.
TIMERS
LDO# — The longdog timer output is an active-low opendrain output that can be wire-ORed with other open-drain
signals. The longdog timer is generally programmed to
generate an output at a time interval longer than the
watchdog timer. The time interval is programmed in
Register R1C.
WDO# — The watchdog timer output is an active-low
open-drain output that can be wire-ORed with other opendrain signals. The watchdog timer is generally programmed to generate an output at a time interval shorter
than the longdog timer. The time interval is programmed
in Register R1C.
WLDI — Watchdog and longdog timer reset input. A lowto-high transition on this pin will reset both the watchdog
timer and the longdog timer.
The watchdog and longdog work in tandem: resetting one
resets the other. Generally, the longdog will be programmed to time out sometime after the watchdog. As an
example, the WDO# output could be used to generate a
warning interrupt and the LDO# output could be tied to a
system reset line.
Both timers can be turned off, facilitating system debug
and also allowing operating systems to ‘boot up’ and
configure themselves without interrupts or resets.
4
The VI input monitors the bus-side voltage for both undervoltage and over-voltage conditions. The thresholds for
the under-voltage detection for VI inputs are programmed
in Registers R00 through R03. The VI input is effectively
the VREF of a nonvolatile DAC. The DAC has been
designed so that the threshold can be determined by
multiplying the binary value of the Register times 20mV
and adding that to 0.9V in the formula PVIT = 0.9V + (0.2mV
× n), where n is the register value (0 - 255 decimal). This
allows very precise monitoring of voltages in the range of
0.9V to 6V without the use of external resistor divider
networks.
The over-voltage section works in a similar manner, with
the formula being Offset = (PVIT × 1.2) + [(0.04 × PVIT) × n],
where n is the register value in R04 through R07. All
enabled manager blocks must ensure their respective VI
inputs are within the programmed limits before the VGATE
outputs can be turned on and the TRAKKER logic enabled. The VI comparator outputs can also be used to
generate a general interrupt.
It should be noted that either one or both of the bus-side
monitors could be disabled via Registers R04 through
R07.
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
VIX
–
+
OV
Comparator
VGATE Enable
+
VREF
CBX
Programmable
Delay
UV
–
Comparator
+
25mV
VGATE and
TRAKKER
Logic
Circuit
Breaker
Comparator
( = Programmable)
–
OC
To IRQ
+
–
Quick
Trip
Comparator
Programmable
Quick Trip
Threshold
VOX
Quick Trip
To Crowbar
–
+
To RST
UV1
Comparator
+
VREF
–
UV2
Comparator
2049 Fig01 1.0
Figure 1. Supply Manager Circuit
CARD-SIDE MANAGEMENT
On the card-side the TRAKKER monitors two programmable under-voltage thresholds on the VO inputs: UV1
and UV2. UV1 can be used to generate a warning interrupt
that the supply is decaying, and UV2 can be used to
generate a reset condition or a crowbar output. The cardside under-voltage (UV1) threshold value is programmed
in Registers R08 through R0B. Like the bus-side thresholds the levels can be programmed in 20mV increments
(on top of 0.9V). The second level (UV2) is determined by
SUMMIT MICROELECTRONICS, Inc.
the formula UV2 = UV1 – [(UV1 × 0.01) × n], where n is the
value in Registers R0C through R0F.
It should be noted that either one or both of the card-side
monitors can be disabled via Registers R0C through R0F.
OVER-CURRENT PROTECTION
The CB inputs are the circuit breaker inputs for the supply
voltages. With a series resistor placed in the supply path
between VI and CB the circuit breaker will trip whenever
the voltage across the resistor exceeds 25mV.
2049 2.2 9/13/00
5
SMT4004
The on-board electronic circuit breaker can be programmed to application specific levels. The circuit
breaker delay defines the period of time the voltage drop
across RS is greater than 25mV but less than VQCB before
the VGATE output will be shut down. This is effectively a
filter to prevent spurious shutdowns of VGATE. The
delays that can be programmed are 25µs, 50µs, 100µs
and 200µs. The programmable delay bits are located in
Register R1B.
The Quick-Trip circuit breaker threshold (VQCB) can be set
to 150mV, 100mV, 75mV or off (Register R1A). This is the
threshold voltage drop across RS that is placed between
VSS and CBSense. If the voltage drop exceeds the
programmed threshold, the electronic circuit breaker will
immediately trigger with no delay.
The outputs of these comparators can be used to generate
interrupts and reset conditions and toggle the crowbar
output.
POWER-ON SEQUENCING
In order to begin sequencing of the card-side supplies
(ramping the VGATE outputs) a number of conditions
must be met. All enabled bus-side voltages must be above
their respective under-voltage thresholds, the card-side
voltages (e.g., residual capacitor stored potentials) must
be near zero volts, and the following inputs must be
properly set.
ENABLE — When active the ENABLE input brings
the IC out of a standby mode where the charge pump
supplying the VGATE outputs is turned on (and
begins charging the VGG_CAP) and the bandgap
reference is turned on. The ENABLE input can be
programmed to be either active low (default from the
factory) or active high (Register R1B).
SEATED1# and SEATED2# — the SEATED inputs
are effectively two additional enable inputs that must
be low to enable the sequencing of the card-side
voltages. In a staggered pin environment these
inputs can be tied to the “short” pins, insuring the card
is fully seated before any power is applied to the cardside logic. These inputs can also be tied to card
insertion switches to indicate proper seating.
PWR_ON — the PWR_ON input is the last input that
will typically be driven to enable power sequencing to
the card-side. The PWR_ON input can be programmed to be either active low (default from the
factory) or active high (Register R1B).
6
TRAKKING AND SOFTSTART CONTROL
VGATE — The VGATE outputs are used to control the
“turning-on” of the card-side voltages. The ramp rate (for
both turn-on and turn-off) of the outputs is programmable
from 100V/s to 1000V/s (Register R10). The four outputs
ramp at the same slew-rate, so normally there will be no
differential voltage between any of the supplies until each
reaches its maximum level.
The ramp rates are inherently adaptive. That is, if the
difference between any VO input is greater than 100mV in
the linear region, the slew rate will be increased or decreased to minimize the differential. The comparisons are
made between VO1 and VO2, VO2 and VO3, VO3 and
VO4, and VO4 and VO1. If at any time a differential of
greater than 300mV is detected a pre-programmed (Register R10) action can be taken. The TRAKKER can shut
down the offending supply, generate an interrupt output, or
ignore the situation.
If SoftStart is enabled (Registers R0C through R0F) the
supply or supplies designated will be ramped as soon as
the input conditions are met and no Trakking will be
performed. Any supply not designated as a softstart
supply will not be ramped until the designated supply has
reached its VO threshold. This type of operation would
commonly be used where a bus voltage (e.g., 5V) is first
switched to a DC-to-DC converter or group of LDOs; and
then their outputs would be switched in a Trakking mode
to the card-side logic.
Supply managers designated for Trakking will not begin
start-up until the soft start channels are fully turned on.
The delay is approximated by the formula tD =16,000 ÷ SR,
where tD is the time delay in milliseconds between the
PWR_ON signal going high and the start of the tracking
ramp-up, and SR is the programmed start-up slew rate in
V/s. For example, the time delay for a programmed slew
rate of 500V/s is: tD = 16,000 ÷ 500 = 32ms.
POWER MANAGEMENT STATUS OUTPUTS
The TRAKKER has two types of status outputs that it
provides to the host system or host processor resident on
its board. One type of output is “hardwired” internally and
the other is programmable.
HEALTHY# — The HEALTHY output is an active-low
open-drain output that can be wire-ORed with other opendrain signals. It is driven low when all of the enabled
managers’ card-side voltages are valid and there are no
over-current conditions. The signal is used to indicate the
power supplies are within their programmed operating
limits.
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
CBFAULT — CBFAULT is driven active whenever an
over-current condition is detected. It is a programmable
output that can be either an active high or active low
(factory default) output.
RESETS
RST1# to RST4# — Associated with each manager is a
reset output. They are active-low open-drain outputs that
can be wire-ORed with other open-drain signals. The user
can select UV1, UV2 and/or an over-current condition as
the trigger for the reset pulse by programming Registers
R11 and R12 (the default condition from the factory is all
conditions generate a reset). The reset pulse width is
adjustable by writing to Register R1C (default condition
from the factory is pulse of 200ms).
MR# — When driven low the manual reset input will
automatically drive all four reset outputs low.
FAULT REGISTER
Whenever an interrupt is generated the cause of the fault
will be recorded in the nonvolatile status Register. In order
to avoid false recordings during power-down situations,
no faults will be recorded if the PWR_ON input has been
deactivated. The fault Registers are located at R1D
through R1F. The fault source is indicated by a “1” in the
assigned bit location. Overwriting the fault Register with
“0’s” is the only way to clear a recorded fault condition.
CROWBAR — The CROWBAR output is another form of
status output. The conditions to generate a crowbar
output are programmable in Register R19. Whenever one
of the conditions occurs the CROWBAR output will strobe.
Rapid shutdown of the card-side supplies may be required
to prevent damage to the DSP’s or microprocessors.
SCRs with a fast turn-on time make excellent crowbar
devices and only need a pulse of gate current to ‘trigger.’
MEMORY AND REGISTER ACCESS
INTERRUPTS
IRQ# — the IRQ output is an active low open-drain output
that is driven low whenever one or more of its programmed
triggers is active. There are twenty programmable
sources for generating the interrupt: bus-side over- and
under-voltage, card-side under-voltage 1 and 2, and an
over-current condition. Each source is individually enabled by writing to Registers R13, R14 and R15. The
default from the factory is to enable all sources. The IRQ#
output can only be cleared by bringing IRQ_CLR# low, or
after a power-down/power-up sequence.
TRKR_IRQ# — the TRAKKER interrupt indicates there
was a skew of greater than 300mV during the power on
cycle. The source of the TRKR_IRQ# is programmable
and can be initiated by any one of the managers. The
configuration Registers R11 and R12 select the source of
interrupt. Configuration Register R10 enables the
TRKR_IRQ# output (or one of three other options). The
default from the factory is to enable all sources. The
TRKR_IRQ# output can only be cleared by bringing
IRQ_CLR high or after a power-down/power-up sequence.
A0, A1 & A2 — The address pins are biased either to the
highest VI pin or GND, and provide a mechanism for
assigning a unique address to the SMH4004.
SDA — SDA is a bidirectional serial data pin. It is
configured as an open drain output and will require a pullup to the highest VI pin.
SCL — SCL is the serial clock input.
MISCELLANEOUS MANAGER SIGNALS
1.25VREF — This pin is a 1.25V Reference output that can
be used in conjunction with external circuitry.
UV_OVERRIDE — The Under-Voltage Override input will
disable the under-voltage comparators. This can be used
for board test and also during system margining.
FORCE_SD — When asserted the Force Shut Down input
will immediately clamp the VGATE outputs to ground. This
can be used in conjunction with the CROWBAR. The
active level for FORCE_SD is programmable and accessible in Register R1B.
In order to avoid false interrupts during a power-on sequence there is a programmable “power-on interrupt holdoff” register. The delay can be programmed from 200ms
to 1600ms. The interrupt hold-off is in Register R15 and
its default value from the factory will be 1600ms.
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
7
SMT4004
REGISTER FORMATS AND FUNCTIONS
There are four basic register types. The first are those that
set a monitoring threshold where the binary value written
to the register is multiplied times the base incremental
voltage. The second type enables or disables a specific
function: unless otherwise indicated a “1” will always
enable the function and a “0” will disable or deselect that
function. Note: only the enabled condition will be depicted
in the following tables. The third Register type allows
selection of various timer values. These are not incremen-
tal, like the thresholds, but specific bit patterns select
specific timer values. The fourth register type is the
nonvolatile fault register that records fault conditions. A “0”
in any bit location indicates its corresponding monitor
function was within specified limits when the fault occurred. A “1” in any bit location indicates its corresponding
monitor function was outside its specified limits when the
fault occurred.
Bus-side Under-voltage Threshold
Registers 00, 01, 02 and 03 are identical. Their contents
select the under-voltage threshold for the VI1, VI2, VI3 and
VI4 inputs, respectively.
Register R00, R01, R02, R03
D7
D6
D5
D4
D3
D2
D1
D0
Action
1
1
1
1
1
1
1
1
Highest threshold adjustment = 6.0V
0
0
0
0
0
0
0
0
Lowest threshold adjustment = 0.9V
0
0
0
0
0
0
1
0
Threshold = 0.9V + (2 × .02V) = 0.94V, e.g.
2049 Table01 1.0
Bus-side Under-voltage Threshold Enable and
Over-voltage Offset
Registers 04, 05, 06 and 07 are identical. Their contents
determine whetheror not the under- or over-voltage capabilities are enabled, and establish the over-voltage offset
value for the VI1, VI2, VI3 and VI4 inputs, respectively.
Register R04, R05, R06, R07
D7
D6
D5
D4
D3
D2
D1
D0
Action
x
1
x
x
x
x
x
x
Enables under voltage detection
x
x
1
x
x
x
x
x
Enables over voltage detection
x
x
x
0
0
0
1
0
Threshold = (VITHRESHOLD + 20%) + (n ×
.04VITHRESHOLD) where n = register binary value
2049 Table02 1.0
Card-side Under-voltage Threshold
Registers 08, 09, 0A and 0B are identical. Their contents
select the under-voltage threshold for the VO1, VO2, VO3
and VO4 inputs, respectively.
Register R08, R09, R0A, R0B
D7
D6
D5
D4
D3
D2
D1
D0
Action
1
1
1
1
1
1
1
1
Highest threshold adjustment = 6.0V
0
0
0
0
0
0
0
0
Lowest threshold adjustment = 0.9V
0
0
0
0
0
0
1
0
Threshold = 0.9V + (2 × .02V) = 0.94V, e.g.
2049 Table03 1.0
8
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
agement functions and soft start capability. Their contents
also determine whether the under- or over-voltage capabilities are enabled and the contents establish the overvoltage offset value for the VO1, VO2, VO3 and VO4
inputs, respectively.
Card- side Under-voltage Threshold Enable
and Over-voltage Offset
Registers 0C, 0D, 0E and 0F are identical These registers
will either enable or disable their associated power man-
Register R0C, R0D, R0E, R0F
D7
D6
D5
D4
D3
D2
D1
D0
1
x
x
x
x
x
x
x
Power management channel enabled
x
1
x
x
x
x
x
x
1 = Enable soft start; 0 = Enable Trakking
x
x
1
x
x
x
x
x
Enables under voltage 2
0
Threshold = (UV1) – (n × UV1 × 0.01) where
n = register binary value
x
x
x
0
0
0
1
Action
2049 Table04 1.0
any bus request addressing its device type identifier, or
whether it will be selective and only respond if the A2, A1
and A0 bits match the biasing of the external pins. Bit 6
selects the device type identifier to be used for the memory
array.
Addressing and Slew Rate Control
Configuration Register 10 is used to configure the addressing protocol for the TRAKKER. Bit 7 determines
whether the device will respond with an acknowledge to
Register R10
D7
D6
0
x
1
x
x
0
x
1
D5
D4
D3
D2
D1
D0
Action
Responds only to Pin biased bus
addresses
Responds to all bus addresses
x
Memory device-type identifier 1010
Memory device-type identifier 1011
TRAKKER over/under 300mV differential action
0
0
Ignore
0
1
Shut down the faulty supply and
TRKR_IRQ#
1
0
Shut down all supplies and
TRKR_IRQ#
1
1
Generate TRKR_IRQ#
x
x
TRAKKER slew rate low to high (off to on)
x
0
0
0
1
1
0
1
1
100V/s
250V/s
x
500V/s
1000V/s
TRAKKER slew rate high to low (on to off)
0
100V/s
0
1
250V/s
1
0
500V/s
1
1
1000V/s
0
x
2049 Table05 1.0
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
9
SMT4004
Reset Source Select and TRAKKER IRQ Select (for Supply Managers 1 and 2)
Register R11
D7
D6
D5
D4
D3
D2
D1
D0
VO1-1
VO1-2
VI1O
TRKR1
VO2-1
VO2-2
VI2O
TRKR2
1
x
x
x
x
x
x
x
Selects card-side1 UV1 as RST#1
trigger
x
1
x
x
x
x
x
x
Selects card-side1 UV2 as RST#1
trigger
x
x
1
x
x
x
x
x
Selects CBI1 as RST#1 trigger
x
x
x
1
x
x
x
x
Selects TRK1 error as an interrupt
source
x
x
x
x
1
x
x
x
Selects card-side2 UV1 as RST#2
trigger
x
x
x
x
x
1
x
x
Selects card-side2 UV2 as RST#2
trigger
x
x
x
x
x
x
1
x
Selects CBI2 as RST#2 trigger
x
x
x
x
x
x
x
1
Selects TRK2 error as an interrupt
source
Action
2049 Table06 1.0
Reset Source Select and TRAKKER IRQ Select (for Supply Managers 3 and 4)
Register R12
D7
D6
D5
D4
D3
D2
D1
D0
VO3-1
VO3-2
VI3O
TRKR3
VO4-1
VO4-2
VI4O
TRKR4
1
x
x
x
x
x
x
x
Selects card-side3 UV1 as RST#3
trigger
x
1
x
x
x
x
x
x
Selects card-side3 UV2 as RST#3
trigger
x
x
1
x
x
x
x
x
Selects CBI3 as RST#3 trigger
x
x
x
1
x
x
x
x
Selects TRK3 error as an interrupt
source
x
x
x
x
1
x
x
x
Selects card-side4 UV1 as RST#4
trigger
x
x
x
x
x
1
x
x
Selects card-side4 UV2 as RST#4
trigger
x
x
x
x
x
x
1
x
Selects CBI4 as RST#4 trigger
1
Selects TRK4 error as an interrupt
source
x
x
x
x
x
x
x
Action
2049 Table07 1.0
10
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
IRQ Source Select (for Supply Managers 1 and 2)
Register R13
D7
D6
D5
D4
D3
D2
D1
D0
VI1-OV
VI1-UV
VO1-1
VO1-2
VI2-OV
VI2-UV
VO2-1
VO2-2
1
x
x
x
x
x
x
x
Selects bus-side1 OV as an IRQ#
trigger
x
1
x
x
x
x
x
x
Selects bus-side1 UV as an IRQ#
trigger
x
x
1
x
x
x
x
x
Selects card-side1 UV1 as an IRQ#
trigger
x
x
x
1
x
x
x
x
Selects card-side1 UV2 as an IRQ#
trigger
x
x
x
x
1
x
x
x
Selects bus-side2 OV as an IRQ#
trigger
x
x
x
x
x
1
x
x
Selects bus-side2 UV as an IRQ#
trigger
x
x
x
x
x
x
1
x
Selects card-side2 UV1 as an IRQ#
trigger
x
x
x
x
x
x
x
1
Selects card-side2 UV2 as an IRQ#
trigger
Action
2049 Table08 1.0
IRQ Source Select (for Supply Managers 3 and 4)
Register R14
D7
D6
D5
D4
D3
D2
D1
D0
VI3-OV
VI3-UV
VO3-1
VO3-2
VI4-OV
VI4-UV
VO4-1
VO4-2
1
x
x
x
x
x
x
x
Selects bus-side3 OV as an IRQ#
trigger
x
1
x
x
x
x
x
x
Selects bus-side3 UV as an IRQ#
trigger
x
x
1
x
x
x
x
x
Selects card-side3 UV1 as an IRQ#
trigger
x
x
x
1
x
x
x
x
Selects card-side3 UV2 as an IRQ#
trigger
x
x
x
x
1
x
x
x
Selects bus-side4 OV as an IRQ#
trigger
x
x
x
x
x
1
x
x
Selects bus-side4 UV as an IRQ#
trigger
x
x
x
x
x
x
1
x
Selects card-side4 UV1 as an IRQ#
trigger
x
x
x
x
x
x
x
1
Selects card-side4 UV2 as an IRQ#
trigger
Action
2049 Table09 1.0
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
11
SMT4004
IRQ Power-on Delay and Source Select (for All Supply Managers)
Register R15
D7
D6
D5
D4
D3
D2
D1
D0
Action
x
0
0
0
x
x
x
x
IRQ# power on delay off (0ms)
x
1
0
0
x
x
x
x
IRQ# power on delay 200ms
x
1
0
1
x
x
x
x
IRQ# power on delay 400ms
x
1
1
0
x
x
x
x
IRQ# power on delay 800ms
x
1
1
1
x
x
x
x
IRQ# power on delay 1600ms
x
x
x
x
1
x
x
x
Supply 1 over-current triggers IRQ#
x
x
x
x
x
1
x
x
Supply 2 over-current triggers IRQ#
x
x
x
x
x
x
1
x
Supply 3 over-current triggers IRQ#
x
x
x
x
x
x
x
1
Supply 4 over-current triggers IRQ#
2049 Table10 1.0
CROWBAR Source Enables
Register R19
D7
D6
D5
D4
D3
D2
D1
D0
FORCE
_SD
IRQ#
TRK_
IRQ#
RST1
RST1
RST1
RST1
QUICK
TRIP
1
x
x
x
x
x
x
x
Enable FORCE_SD
x
1
x
x
x
x
x
x
General interrupt
x
x
1
x
x
x
x
x
TRAKKER interrupt
x
x
x
1
x
x
x
x
Supply 1 reset
x
x
x
x
1
x
x
x
Supply 2 reset
x
x
x
x
x
1
x
x
Supply 3 reset
x
x
x
x
x
x
1
x
Supply 4 reset
x
x
x
x
x
x
x
1
Quick Trip condition
Action
2049 Table11 1.0
12
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
Quick-trip Voltage Thresholds
Register R1A
D7
D6
D5
MANAGER 1
0
0
0
1
1
0
1
1
D4
MANAGER 2
D3
D2
D1
MANAGER 3
D0
Action
MANAGER 4
Off
75mV
x
100mV
150mV
0
x
Off
0
0
1
1
0
1
1
x
75mV
x
100mV
150mV
0
0
0
1
1
0
1
1
Off
100mV
150mV
0
Off
0
1
75mV
1
0
100mV
1
1
150mV
0
x
75mV
x
2049 Table12 1.0
Over-current Delay and Active Pin Level Select
Register R1B
D7
D6
D5
D4
D3
D2
na
na
CB
EN
PO
F-SD
1
x
x
x
x
x
D1
D0
Action
OC - DLY
x
x
CBFAULT output (1 = active high)
x
1
x
x
x
x
ENABLE input (1 = active high)
x
x
1
x
x
x
PWR_ON input (1 = active high)
x
x
x
1
x
x
FORCE_SD input (1 = active high)
Over-current delay
x
x
x
x
x
x
0
0
25µs
x
x
x
x
0
1
50µs
x
x
x
x
1
0
100µs
x
x
x
x
1
1
200µs
2049 Table13 1.0
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
13
SMT4004
Timer Configuration Register
Register R1C
D7
D6
RESET PERIOD
0
0
0
1
1
0
1
1
x
x
D5
D4
D3
LONGDOGTIMER
D2
D1
D0
Action
WATCHDOG TIMER
25ms
x
50ms
x
100ms
200ms
0
x
x
Off
1
0
0
800ms
1
0
1
1
1
0
3200ms
1
1
1
6400ms
x
x
1600ms
0
x
x
Off
1
0
0
400ms
1
0
1
800ms
1
1
0
1600ms
1
1
1
3200ms
2049 Table14 1.0
14
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
Status Registers
SR1D
D7
D6
D5
D4
D3
D2
D1
D0
VI1-UV
VI2-UV
VI3-UV
VI4-UV
VI1-OV
VI2-OV
VI3-OV
VI4-OV
1
x
x
x
x
x
x
x
Bus-side1 UV
x
1
x
x
x
x
x
x
Bus-side2 UV
x
x
1
x
x
x
x
x
Bus-side3 UV
x
x
x
1
x
x
x
x
Bus-side4 UV
x
x
x
x
1
x
x
x
Bus-side1 OV
x
x
x
x
x
1
x
x
Bus-side2 OV
Action
x
x
x
x
x
x
1
x
Bus-side3 OV
x
x
x
x
x
x
x
1
Bus-side4 OV
2049 Table15 1.0
SR1E
D7
D6
D5
D4
D3
D2
D1
D0
VO1UV1
VO2UV1
VO3UV1
VO4UV1
VO1UV2
VO2UV2
VO3UV2
VO4UV2
Action
1
x
x
x
x
x
x
x
Card-side1 UV1
x
1
x
x
x
x
x
x
Card-side2 UV1
x
x
1
x
x
x
x
x
Card-side3 UV1
x
x
x
1
x
x
x
x
Card-side4 UV1
x
x
x
x
1
x
x
x
Card-side1 UV2
x
x
x
x
x
1
x
x
Card-side2 UV2
x
x
x
x
x
x
1
x
Card-side3 UV2
x
x
x
x
x
x
x
1
Card-side4 UV2
2049 Table16 1.0
SR1F
D7
D6
D5
D4
D3
D2
D1
D0
TRK1
TRK2
TRK3
TRK4
OC1
OC2
OC3
OC4
1
x
x
x
x
x
x
x
TRAKKER error supply 1
x
1
x
x
x
x
x
x
TRAKKER error supply 2
x
x
1
x
x
x
x
x
TRAKKER error supply 3
x
x
x
1
x
x
x
x
TRAKKER error supply 4
x
x
x
x
1
x
x
x
Over-current supply 1
x
x
x
x
x
1
x
x
Over-current supply 2
x
x
x
x
x
x
1
x
Over-current supply 3
x
x
x
x
x
x
x
1
Over-current supply 4
Action
2049 Table17 1.0
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
15
SMT4004
AC OPERATING CHARACTERISTICS
Over recommended operating conditions
Symbol
Parameter
Conditions
Min.
Max.
Units
0
100
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
4.7
µs
tHIGH
Clock high period
4.0
µs
tBUF
Bus free time
4.7
µs
tSU:STA
Start condition setup time
4.7
µs
tHD:STA
Start condition hold time
4.0
µs
tSU:STO
Stop condition setup time
4.7
µs
tAA
Clock edge to valid output
SCL low to valid SDA (cycle n)
0.3
tDH
Data Out hold time
SCL low (cycle n+1) to SDA change
0.3
tR
SCL and SDA rise time
1000
ns
tF
SCL and SDA fall time
300
ns
Before new transmission
3.5
µs
µs
tSU:DAT
Data In setup time
250
ns
tHD:DAT
Data In hold time
0
ns
TI
Noise filter SCL and SDA
tWR
Write cycle time
Noise suppression
100
ns
5
ms
2049 Table18 2.0
tR
tF
tHIGH
tLOW
SCL
tSU:SDA
tHD:SDA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA In
tAA
tDH
SDA Out
2049 Fig02 1.0
Figure 2. Memory Operating Characteristics
16
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
Master
S
T
A
R Device Type Bus
T Address Address
1 0 1 0
SDA
R
B B
A A A /
2 1 8 W
S
T
A
R
T
SDA
R
B B
A A A /
2 1 8 W
S
T
A
R
T
SDA
SDA
A A A A A A A A
7 6 5 4 3 2 1 0
Up to 15
additional bytes
can be written
before issuing
the stop.
S
T
O
P
A
C
K
A
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
The host may continue
clocking out data so long as
it provides an ACK response
after each byte.
1 00 1
R
B B
A A X /
W
2 1
A
C
K
Reading the Configuration Register
1 00 1
B B
R
A A X /
2 1
W
Slave
D D D D D D D D
7 6 5 4 3 2 1 0
C C C C C C C C
7 6 5 4 3 2 1 0
A
C
K
S
T
A
R
T
S
T
O
P
Writing Configuration Registers
Slave
Master
A
C
K
A
C
K
Slave
Master
A
C
K
Current Address Read
(Alternate memory device type)
10 10
S
T
O
P
D D D D D D D D
7 6 5 4 3 2 1 0
A A A A A A A A
7 6 5 4 3 2 1 0
A
C
K
Slave
Master
Typical Write Operation
(Standard memory device type)
C C C C C C C C
7 6 5 4 3 2 1 0
A
C
K
A
C
K
S
T
A
R
T
A S
C T
K O
P
1 00 1
B B
R
A A X /
2 1
W
D D D D D D D D
7 6 5 4 3 2 1 0
A
C
K
A
C
K
2049 Fig03 2.0
Figure 3. Read and Write Operations
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
17
SMT4004
MEMORY AND REGISTER OPERATION
The TRAKKER has a nonvolatile memory that is configured as a 256 x 8 array. Configuration Registers reside in
another ‘device type’ address space.
All read and write operations to both ‘device type’ spaces
are handled via an industry standard two-wire interface.
The bus was designed for two-way, two-line serial communication between different integrated circuits. The two
lines are a serial data line (SDA), and a serial clock line
(SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus
Data Protocol
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device that receives data as
a “receiver.” The device controlling data transmission is
called the “master” and the controlled device is called the
“slave.” The TRAKKER will always be a “slave” device
since it never initiates a data transfer.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because changes on the data line while SCL is high
will be interpreted as start or stop condition.
START and STOP Conditions
When both the data and clock lines are high, the bus is said
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the “START” condition. A low-to- high transition on the data line while the
clock is high is defined as the “STOP” condition.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will
pull the SDA line low to ACKnowledge that it received the
eight bits of data.
The TRAKKER will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected
the TRAKKER will respond with an ACKnowledge after
Device Type
Bus Address
D7
D6
D5
D4
1
0
1
0
1
0
1
1
1
0
0
1
D3
D2
the receipt of each subsequent 8-bit word. In the READ
mode the TRAKKER transmits eight bits of data, releases
the SDA line, and then monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP
condition is generated by the master, the TRAKKER will
continue to transmit data. If an ACKnowledge is not
detected the TRAKKER will terminate further data transmissions and await a STOP condition before returning to
the standby power mode.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four bits of the slave address are the device type
identifier (see the following Table). The next three bits
are the physical device address.
Read/Write Bit
The last bit of the data stream defines the operation to
be performed. When set to “1,” a read operation is
selected; when set to “0,” a write operation.
MEMORY WRITE OPERATIONS
The TRAKKER allows two types of write operations: bytewrite and page write. A byte-write operation writes a single
byte during the nonvolatile write period (tWR). The page
write operation allows up to 16 bytes in the same page to
be written during tWR.
Byte Write
After the slave address is sent (to identify both the slave
device and a read or write operation), a second byte is
transmitted which contains the 8-bit address of any one of
the 256 words in the array. Upon receipt of the word
address the TRAKKER responds with an ACKnowledge.
After receiving the next byte of data it again responds with
an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the
TRAKKER begins the internal write cycle. While the
internal write cycle is in progress the TRAKKER inputs are
disabled, and the device will not respond to any requests
from the master.
R/W
D1
D0
Action
Memory device-type address
A2
A1
A0
1/0
Alternate memory device-type address
Configuration registers device-type address
2049 Table19 1.0
18
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
Page Write
Write Cycle
In Progress
The TRAKKER is capable of a 16-byte page-write operation. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word the master can transmit up to 15 more
bytes of data. After the receipt of each byte the TRAKKER
will respond with an ACKnowledge.
Issue Start
Issue Stop
The TRAKKER automatically increments the address for
subsequent data words. After the receipt of each word, the
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the master transmit more than 16 bytes, prior to
generating the STOP condition, the address counter will
“roll over” and the previously written data will be overwritten. As with the byte-write operation, all inputs are
disabled during the internal write cycle. Refer to Figure 3
for the address, ACKnowledge and data transfer sequence.
Issue Slave
Address and
R/W = 0
No
ACK
Returned
Yes
Next
Operation
a Write?
Acknowledge Polling
No
Yes
When the TRAKKER is performing an internal WRITE
operation it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete. See the flow diagram for the proper
sequence of operations for polling.
Issue Stop
Issue
Address
Proceed
With
Write
Await
Next
Command
READ OPERATIONS
2049 Flow01 1.0
Read operations are initiated with the R/W bit of the
identification field set to “1.” There are two different read
options:
Random Address Read
1. Current Address Byte Read
2. Random Address Byte Read
Current Address Read
The TRAKKER contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
TRAKKER receives the slave address field with the R/W
bit set to “1” it issues an acknowledge and transmits the 8bit word stored at address location n+1. The current
address byte read operation only accesses a single byte
of data. The master does not acknowledge the transfer,
but does generate a stop condition. At this point the
TRAKKER discontinues data transmission.
SUMMIT MICROELECTRONICS, Inc.
Flow Chart
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condition
and the slave address field (with the R/W bit set to WRITE),
followed by the address of the word it is to read. This
procedure sets the internal address counter of the TRAKKER to the desired address. After the word address
acknowledge is received by the it the master immediately
reissues a start condition followed by another slave address field with the R/W bit set to READ. The TRAKKER
will respond with an acknowledge and then transmit the 8
data bits stored at the addressed location. At this point, the
master does not acknowledge the transmission but does
generate the stop condition. The TRAKKER discontinues
data transmission and reverts to its standby power mode.
2049 2.2 9/13/00
19
SMT4004
Sequential READ
Sequential reads can be initiated as either a current
address READ or random access READ. The first word
is transmitted as with the other byte read modes (current
address byte READ or random address byte READ).
However, the master now responds with an ACKnowledge, indicating that it requires additional data from the
TRAKKER. The TRAKKER continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP condition. During a
sequential read operation the internal address counter is
automatically incremented with each ACKnowledge signal. For read operations all address bits are incremented,
allowing the entire array to be read using a single read
command. After a count of the last memory address the
address counter will ‘roll-over’ and the memory will continue to output data.
20
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
APPLICATION CIRCUIT
GND
4 × 330µF
1.8V
2 × 330µF
10Ω
10Ω
VO4
VO3
VO2
VO1
SMT4004
CBFAULT
IRQ#
HEALTHY#
A2
A1
A0
SCL
SDA
AGND
DGND
PGND
PGND
10kΩ
GND
4.7µF
RAW3.3V
RAW5V
VGG_CAP
10kΩ
4.7µF
To
Pullup
RS
10kΩ
1.8V
@10A
2.5V
@4A
VI4
VI3
VI2
VI1
2mΩ
5mΩ
2mΩ
2.5mΩ
CB4
CB3
CB2
CB1
ENABLE
UV_OVERRIDE
SEATED1#
PWR_ON
FORCE_SD
SEATED2#
10Ω
10Ω
VGATE4
VGATE3
VGATE2
VGATE1
WLDI
WDO#
LDO#
MR#
IRQ_CLR#
1.25VREF
TRKR_IRQ#
100nF
RST1#
RST2#
RST3#
RST4#
CROWBAR
VDD_CAP
10µF
500µF
5 × 220µF
5V
3.3V
2.5V
See Figure 4. A typical circuit soft starting the 5V supply
and TRAKKING the 3.3V, 2.5V and 1.8V supplies
2049 Fig04 2.0
Figure 4. Application Circuit
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
21
SMT4004
ORDERING INFORMATION
SMT4004
F
Package
F = 48 Pin TQFP
Base Part Number
Register
Hex Contents
Configured as:
R0
B4
VO Threshold of 4.5V
R1
69
V1 Threshold of 3.OV
R2
41
V2 threshold of 2.2V
R3
28
V3 Threshold of 1.7V
R4
60
V0 UV and OV enabled OV set to 5.5V
R5
60
V1 UV and OV enabled OV set at 3.6V
R6
62
V2 UV and OV enabled OV set at 2.8V
R7
67
V3 UV and OV enabled OV set at 2.5V
R8
B9
Card Side VO Threshold of 4.6V
R9
6E
Card Side V 1 Threshold of 3.1 V
RA
46
Card Side V2 threshold of 2.3V
RB
2D
Card Side V3 Threshold of 1.8V
RC
A2
Card Side VO Threshold 2 of 4.5V
RD
A3
Card Side V 1 Threshold 2 of 3.OV
RE
A4
Card Side V2 threshold 2 of 2.2V
RF
A6
Card Side V3 Threshold 2 of 1.7V
R10
05
Responds to pin biased addresses, 1010BIN, 250V/s slew rate on and off
R11
FF
Enable all RESET sources
R12
FF
Enable all RESET and IRQ sources
R13
FF
Enable all IRQ sources
R14
FF
Enable all IRQ sources
R15
EF
800 ms POR to IRQ delay, enable all sources
R19
81
Enable Crowbar on manual input and Quicktrip only
R1A
AA
Enable 100mV Quicktrip all manager circuits
RIB
02
All outputs active low, over current delay 100µs
RIC
F6
Reset 200ms, Longdog 3200ms, Watchdog 1600ms
2049 Reg Table 1.0
22
2049 2.2 9/13/00
SUMMIT MICROELECTRONICS, Inc.
SMT4004
PACKAGE
48 PIN TQFP PACKAGE
8.975 – 9.025
0.353 – 0.355
0.02
0.50 BSC
0.003
0.009
0.22
8.975 – 9.025
0.353 – 0.355
0.076
1.35 – 1.45
DETAIL "A"
0.053 – 0.057
6.5 – 7.1
0.271 – 0.280
6.5 – 7.1
0.271 – 0.280
0.063
1.60 max
1 ref
Pin 1
0.018 – 0.030
0.45 – 0.75
0.004 – 0.008
0.10 – 0.20
A
B
mm.
in.
DETAIL "B"
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating
parameters, and may vary depending upon a user’s specific application. While the information in this publication has
been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any
error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications
where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to
significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless
SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is
adequately protected under the circumstances.
© Copyright 2000 SUMMIT Microelectronics, Inc.
I2C is a trademark of Philips Corporation.
SUMMIT MICROELECTRONICS, Inc.
2049 2.2 9/13/00
23