CSD75211W1723 www.ti.com SLPS250 – MAY 2010 Dual P-Channel NexFET™ Power MOSFET Check for Samples: CSD75211W1723 PRODUCT SUMMARY FEATURES 1 • • • • • • • Dual P-Ch MOSFETs Common Source Configuration Small Footprint 1.7 mm × 2.3 mm Ultra Low Qg and Qgd Pb Free RoHS Compliant Halogen Free VDS Drain to Source Voltage -20 V Qg Gate Charge Total (-4.5V) 4.5 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) nC 50 mΩ VGS = -2.5V 39 mΩ VGS = -4.5V 32 mΩ Threshold Voltage -0.7 V Text Added for Spacing ORDERING INFORMATION APPLICATIONS • • • 0.9 VGS = -1.8V Battery Management Battery Protection DC-DC Converters Device Package Media Qty Ship CSD75211W1723 1.7-mm × 2.3-mm Wafer Level Package 7-Inch Reel 3000 Tape and Reel Text Added for Spacing ABSOLUTE MAXIMUM RATINGS DESCRIPTION The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with thermal characteristics in an ultra low profile. Low on resistance and gate charge coupled with the small footprint and low profile make the device ideal for battery operated space constrained application in load management as well as DC-DC converter applications Top View G1 D1 D1 D1 S S S S G2 D2 D2 D2 TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage -20 V VGS Gate to Source Voltage +8 V -4.5 A -6 A 1.5 W –55 to 150 °C Continuous Drain Current (1) (2)(3) ID Pulsed Drain Current (1) (2)(3) Continupus Gate Clamp Current (4) IG Pulsed Gate Clamp Current (4) PD Power Dissipation (1) TJ, TSTG Operating Junction and Storage Temperature Range (1) (2) (3) (4) May be limited by Max source current Based on Min Cu footprint Per MOSFET Total for device P0114-01 RD1D2(on) vs VGS 80 ID = -2A 70 60 T C = 125°C 50 40 30 T C = 25°C 20 10 0 0 1 2 3 4 5 6 7 8 -VGS - Gate-to-Source Voltage - V 9 10 G006 RD1D2(on) - Drain-Drain On-State Resistance - mΩ RDS(on) - Drain-Source On-State Resistance - mΩ RDS(on) vs VGS 140 ID = -2A 120 100 T C = 125°C 80 60 40 T C = 25°C 20 0 0 1 2 3 4 5 6 7 8 -VGS - Gate-to-Source Voltage - V 9 10 G013 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD75211W1723 SLPS250 – MAY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = -250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = -16V IGSS Gate to Source Leakage Current VDS = 0V, VGS = ±8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = -250mA RDS(on) Drain to Source On Resistance RDD(on) Drain to Drain On Resistance gfs Transconductance -20 -0.4 V -1 mA ±100 nA -0.7 -1.1 VGS = -1.8V, IDS = -2A 50 70 mΩ V VGS = -2.5V, IDS = -2A 39 50 mΩ VGS = -4.5V, IDS = -2A 32 40 mΩ VGS = -1.8V, IDS = -2A 80 110 mΩ VGS = -2.5V, IDS = -2A 61 75 mΩ VGS = -4.5V, IDS = -2A 46 55 mΩ VDS = -10V, ID = -2A 6.4 S Dynamic Characteristics CISS Input Capacitance 460 600 pF COSS Output Capacitance CRSS Reverse Transfer Capacitance 220 290 pF 73 95 RG pF Seried Gate Resistance 1.6 3.2 Ω Qg Gate Charge Total (-4.5V) 4.5 5.9 nC Qgd Gate Charge Gate to Drain 0.9 nC Qgs Gate Charge Gate to Source 0.9 nC Qg(th) Gate Charge at Vth 0.4 nC QOSS Output Charge 4.9 nC td(on) Turn On Delay Time 3.7 ns tr Rise Time 4.1 ns td(off) Turn Off Delay Time 9.1 ns tf Fall Time 1.6 ns VGS = 0V, VDS = -10V, f = 1MHz VDS = -10V, ID = -2A VDS = -17V, VGS = 0V VDS = -10V, VGS = -4.5V, ID = -2A, RG = 2Ω Diode Characteristics VSD Diode Forward Voltage ID = -2A, VGS = 0V 0.7 Qrr Reverse Recovery Charge 11 nC trr Reverse Recovery Time VDD= -17V, IF = -2A, di/dt = 300A/ms 1 V 19 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER MIN R qJA Thermal Resistance Junction to Ambient (Minimum Cu area) R qJA Thermal Resistance Junction to Ambient (1 in2 Cu area) (1) (2) (3) 2 (1) (2) (2) (3) TYP MAX UNIT 160 °C/W 69 °C/W Device mounted on FR4 material with minimum Cu mounting area. Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1 in2 of 2oz. Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 CSD75211W1723 www.ti.com SLPS250 – MAY 2010 CSD75211W1723 TTA MIN Rev 0 CSD86311W1723 CSD75211W1723 TTA MIN Rev 0 CSD86311W1723 Max RqJA = 69°C/W when mounted on 1inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RqJA = 160°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. G1 S G2 D2 D1 G1 S G2 D2 D1 M0183-01 M0182-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.01 0.1 0.05 Duty Cycle = t1/t2 0.02 0.01 P t1 Single Pulse t2 0.001 0.0001 0.0001 Typical RqJA = 128°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA 0.001 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 3 CSD75211W1723 SLPS250 – MAY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) 20 20 18 18 -IDS - Drain-to-Source Current - A -IDS - Drain-to-Source Current - A (TA = 25°C unless otherwise stated) 16 14 VGS = -4.5V 12 10 VGS = -1.8V VGS = -3.5V 8 VGS = -3V 6 4 VGS = -2.5V 2 VDS = -5V 16 T C = 25°C 14 12 10 8 6 T C = 125°C 4 2 0 0 0 0.3 0.6 0.9 1.2 -VDS - Drain-to-Source Voltage - V 0 1.5 0.2 G001 Figure 2. Saturation Characteristics 0.4 0.6 0.8 1 1.2 1.4 1.6 -VGS - Gate-to-Source Voltage - V G002 1k 4.5 3 2.5 2 1.5 Ciss = Cgd + Cgs C - Capacitance - nF C - Capacitance - nF 4 3.5 Coss = Cds + Cgd 100 Crss = Cgd 1 f = 1MHz VGS = 0V 0.5 10 0 0.5 1 1.5 2 2.5 3 Qg - Gate Charge - nC 3.5 4 4.5 0 5 10 15 -VDS - Drain-to-Source Voltage - V G003 0.9 ID = -250µA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -25 25 75 T C - Case Temperature - °C 20 G004 Figure 5. Capacitance 125 175 RDS(on) - Drain-Source On-State Resistance - mΩ Figure 4. Gate Charge -VGS(th) - Threshold Voltage - V 2 ID = -2A VDS = -10V 0 80 ID = -2A 70 60 T C = 125°C 50 40 30 T C = 25°C 20 10 0 0 1 2 G005 Figure 6. Threshold Voltage vs. Temperature 4 1.8 Figure 3. Transfer Characteristics 5 -VGS - Gate-to-Source Voltage - V T C = -55°C 3 4 5 6 7 8 -VGS - Gate-to-Source Voltage - V 9 10 G006 Figure 7. RDS(on) vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 CSD75211W1723 www.ti.com SLPS250 – MAY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) 1.6 140 ID = -2A Normalized On-State Resistance RD1D2(on) - Drain-Drain On-State Resistance - mΩ (TA = 25°C unless otherwise stated) 120 100 T C = 125°C 80 60 40 T C = 25°C 20 1 2 3 4 5 6 7 8 -VGS - Gate-to-Source Voltage - V 9 10 1.2 1 0.8 0.6 0.4 0.2 -25 25 75 T C - Case Temperature - °C 125 175 G007 G013 Figure 8. RD1D2(on) vs. Gate-to-Source Voltage Figure 9. Normalized On-State Resistance vs. Temperature 10 -IDS - Drain-to-Source Current - A 10 -ISD - Source-to-Drain Current - A ID = -2A VGS = -8V 0 -75 0 0 1.4 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 -VSD - Source-to-Drain Voltage - V 1 1ms 1 10ms 0.1 Area May be Limited by RDS(on) Single Pulse Typical R θJA = 128°C/W (min Cu) 0.01 0.01 1s DC 0.1 1 10 -VDS - Drain-to-Source Voltage - V G008 Figure 10. Typical Diode Forward Voltage 11110 100ms 100 G009 Figure 11. Maximum Safe Operating Area 5 4.5 -ID - Drain Current - A 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 T J - Junction Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 5 CSD75211W1723 SLPS250 – MAY 2010 www.ti.com MECHANICAL DATA CSD75211W1723 Package Dimensions Pin A1 Mark 1 3 2 4 +0.00 –0.08 A 1.74 B C 2.32 +0.00 –0.08 0.62 Max Top View Side View 0.04 0.62 Max 0.35 ±0.10 Seating Plate Front View 1.50 0.50 Solder Ball Ø 0.31 ±0.015 0.50 0.50 C 1.00 0.50 Pinout B A Pin A1 Mark (Hidden) 1 2 3 Position Designation A2, A3, A4 Drain 1 C2, C3, C4 Drain 2 A1 Gate 1 C1 Gate 2 B1, B2, B3, B4 Source 4 Bottom View M0184-01 NOTE: All dimensions are in mm (unless otherwise specified) 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 CSD75211W1723 www.ti.com SLPS250 – MAY 2010 Land Pattern Recommendation 1.50 0.50 0.50 0.50 Ø 0.25 1.00 0.50 A B C 1 2 3 4 M0185-01 NOTE: All dimensions are in mm (unless otherwise specified) Text Added for Spacing Text Added for Spacing Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 45° Max 4.00 ±0.10 1.90 ±0.05 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 Pin A1 Mark 0.30 0.80 ±0.05 0.254 ±0.02 45° Max 2.45 ±0.05 M0186-01 NOTE: All dimensions are in mm (unless otherwise specified) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD75211W1723 7 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2010 PACKAGING INFORMATION Orderable Device CSD75211W1723 Status (1) ACTIVE Package Type Package Drawing DSBGA YZG Pins Package Qty 12 3000 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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