SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER FEATURES The serialized data is presented on the differential serial data output DOUT with a differential clock signal on output CLK. The frequency of CLK is 8× the DCLK input pixel clock rate. 1 • • • • • • • MIPI CSI-1 and SMIA CCP Support Connects Directly to OMAP CSI Interface 4×4 mm QFN Package ESD Rating >3 kV (HBM) Camera Input Ports and >2 kV (HBM) All Other Ports Pixel Clock Range 3.5–26 MHz Three Operating Modes to Conserve Power – Active Mode VGA Camera 30 fps: 7 mA – Typical Shutdown and Standby: 0.5 µA EMI Flexible printed circuit (FPC) cabling typically interconnects the SN65LVDS315 with the CSI-1 compliant receiver. Compared to parallel signalling, the SN65LVDS315 outputs significantly reduce the EMI of the interconnect. The SN65LVDS315 supports three power modes (shutdown, standby and active) to conserve power. The TXEN input may be used to put the SN65LVDS315 in a shutdown mode. The SN65LVDS315 enters an active standby mode if the input clock, DCLK, stops. This minimizes power consumption without the need for controlling an external terminal. APPLICATIONS • • Camera to Host Controller (e.g. OMAP2420, OMAP2430, OMAP3430) Mobile Phones and Smart Phones The SN65LVDS315 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs offer failsafe operation to protect the input from damage during power up and to avoid current flow into the device inputs during power up. The core supply of the SN65LVDS315 is 1.8 V. To provide greater flexibility, the camera data inputs support a supply range from 1.8 V to 3.3 V. DESCRIPTION The SN65LVDS315 is a camera serializer that converts 8-bit parallel camera data into MIPI-CSI1 or SMIA CCP compliant serial signals. The device converts the parallel 8-bit data to two sub-low-voltage differential signaling (SubLVDS) serial data and clock output. The parallel data is latched in with the pixel clock input DCLK on the falling clock edge. The control inputs VS and HS are used to determine line and frame synchronization. Camera RGB IF LVDS315 FPC Application processor with integrated MIPI CSI-1 receiver 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8 Packet Engine: Packet Validation 8 Force EOF D[0:7] HS Load SubLVDS PLL x8 SubLVDS DOUT+ DOUT- ++ Reset VS 8-Bit Parallel to Serial FUNCTIONAL BLOCK DIAGRAM Counter Line Count & MODE DCLK CLK+ CLK- Low Frequency Detector Standby, Shutdown, and Startup Controller Glitch Supression TXEN 2 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 D6 GNDD DCLK D5 D4 D3 24-PIN QFN 0.5MM PITCH (RGE) 18 17 16 15 14 13 D1 HS 21 10 D0 VDDIO 22 9 VDDA VDDD 23 8 MODE FSEL 24 7 TXEN GNDD 1 2 3 4 5 6 GNDA 11 CLK+ VS 20 CLK- D2 DOUT+ 12 DOUT- D7 19 Table 1. Pin Description QFN Package PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN 1 GNDD 2 DOUT– 3 SIGNAL 7 TXEN 13 D3 19 D7 8 MODE 14 D4 20 VS DOUT+ 9 VDDA 15 D5 21 HS 4 CLK– 10 D0 16 DCLK 22 VDDIO 5 CLK+ 11 D1 17 GNDD 23 VDDD 6 GNDA 12 D2 18 D6 24 FSEL Table 2. TERMINAL FUNCTIONS TERMINAL NAME DOUT+, DOUT– DESCRIPTION TYPE SubLVDS out SubLVDS data link CSI-1 compliant (active during normal operation; high-impedance during power down or standby) DOUT is valid on the rising edge of CLK+. CLK+, CLK– SubLVDS clock output (CSI-1 Mode 0 compliant) D0–D7 Data inputs (8) for pixel data; These inputs are sampled on the falling DCLK edge; inputs incorporate bus hold Note: D[7:0] states are latched into the SN65LVDS315 on the falling DCLK input edge VS Vertical Sync (also called frame sync); Data input (high active). This input is sampled on every falling DCLK edge Input incorporates bus hold CMOS in (1) HS Horizontal Sync (also called line sync); Data input (high active). This input is sampled on every falling DCLK edge Input incorporates bus hold DCLK Data input Clock; DCLK represents the camera pixel clock. All 8 pixel bits as well as VS and HS are latched into the device on the falling edge of DCLK (falling edge clocking) Input incorporates bus hold (1) These inputs are referenced to the VDDIO supply rail and support a voltage range of 1.65 V to 3.6 V Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 3 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Table 2. TERMINAL FUNCTIONS (continued) TERMINAL NAME DESCRIPTION TYPE Disables the subLVDS Drivers and turns off the PLL putting device in Shutdown mode 1 – Transmitter enabled 0 – Transmitter disabled (shutdown) TXEN Note: TXEN input incorporates glitch-suppression logic to avoid device malfunction on short input spikes. It is necessary to pull TXEN high for longer than 10 µs to enable the transmitter. It is necessary to pull the TXEN input low for longer than 10 µs to disable the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0. Do not leave TXEN floating. CMOS in (2) Frequency Select FSEL=0: DCLK input frequencies from 3.5 MHz to 13 MHz are supported FSEL=1: DCLK input frequencies from 7.0 MHz to 26 MHz are supported Do not leave FSEL floating. FSEL MODE The mode pin enables line counting to generate proper EOF signalling in case VS and HS do not reset during the same DCLK cycle (0-line counter disable; 1-counter enabled). The impact of the MODE pin setting is described in detail in the VS and HS Timing to Generate the Correct Control Signals section. If you are unsure about the proper setting of the MODE input, it is recommended to set MODE=high. Do not leave the MODE input floating. VDDIO IO Supply Voltage for inputs D[0:7], HS, VS, and DCLK, (1.8 V up to 3.3 V) VDDD Digital supply voltage (1.8 V only) GNDD Power Supply (3) Supply Ground for VDDIO and VDDD VDDA PLL and SubLVDS I/O supply voltage (1.8 V only) GNDA PLL and SubLVDS Ground (2) (3) These inputs can tolerate an input voltage up to 3.6 V while the actual input threshold from logic low to logic high is at 0.9 V nominal; This allows driving these inputs from a 1.8 V or 3.3 V GPIO independent of the camera supply voltage. In a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. FUNCTIONAL DESCRIPTION Parallel Input Port Timing Information The parallel input data must comply with the following signal timing: HS (Line Valid) DCLK Valid Image Data Blanking D[0:7] P0 P1 P2 Blanking P3 P4 P(n-1) Pn Figure 1. Parallel Input Timing Diagram 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 The relationship between frame sync and line sync shall be the following: VS (Frame Valid) Last Visible Line HS (Line Valid) A B C B D E 0 £ tA 0 £ tB 8x1/fDCLK £ tC 0 £ tD if MODE = high or tD = 0: 8x1/fDCLK £ tE if MODE = low or tD > 0: 12x1/fDCLK £ tE A - Time between VS and HS rising edge: B - Number of pixel in active line: C - Horizonal line blanking: D - Time between VS and HS falling edge: E - Time between HS falling and HS rising edge: Figure 2. VS and HS Timing Diagram MIPI CSI-1 / CCP2-Class 0 Interface When MODE is held low, the SN65LVDS315 provides a MIPI CSI-1 compliant serial output. The output data on DOUT is set on each falling edge of the differential clock signal, CLK. The CSI-1/CCP2 receiver should latch the data in on the rising CLK edge. The clock signal is free running (and not gated as optional in the CCP2 spec). The data format is bytewise (8-bit boundary) with the least significant bit (LSB) sent first. When nothing is being transferred (e.g. during blanking), DOUT remains high, except during power shutdown. CLK+ D0+/- 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 Figure 3. Data and Clock Output in CSI-1/CCP2 Camera Mode Class-0 Transferring a Data Sequence of 0xFF011223h Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 5 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Frame Structure and Synchronization Codes Camera images are transferred in frames. Each frame contains one camera image. Each frame consists of a number of lines. A frame is always larger than the number of visible lines. The non-visible lines within a frame are called frame blanking. Frame blanking must be signaled on the SN65LVDS315 parallel input via a low VS signal. Each line within a frame has an invisible area as well — this area is called line blanking, and is indicated with a low HS signal. The CSI-1/CCP2-compliant output only transmits visible pixels within each frame. During line and frame blanking (also called horizontal and vertical blanking), the data output is set high. To indicate the line start, line end, frame start, and frame end, the SN65LVDS315 transmits synchronization codes. Four synchronization codes are generated and embedded in the serial bit-stream: Start Of Line Code SOL=0xFF00:0000 This code identifies the start of a new line SOL; It is received for every line, except for the first line, which starts with a FSC End Of Line Code EOL=0xFF00:0001 This code identifies the end of a line EOL; It is received for every line, except for the last line, which ends with a FEC Start of Frame Code SOF=0xFF00:0002 This code identifies the start of a new frame SOF End of Frame Code This code identifies the end of the last line and the end of the current frame EOF EOF=0xFF00:0003 Every synchronization code is transmitted byte-wise least significant bit (LSB) first. For example, the code 0xFF00:0002 transmitted from the image sensor corresponds to the following bit stream: 11111111 – 00000000 – 00000000 – 01000000. Every default code starts with a set of eight 1s and sixteen 0s that are never received in pixel data (as having eight 1s and sixteen 0s is not allowed in pixel data). 6 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Preventing Wrong Synchronization To avoid actual pixel data from being erroneously interpreted as a control command, the SN65LVDS315 incorporates bit manipulation. If the SN65LVDS315 parallel input detects a bit sequence of eight 1s followed by sixteen 0s, it replaces the LSB of the 0x00 parallel input word with a one instead of a zero (so the actual pixel value will be adjusted from 0x00 to 0x01). Here are a few examples: input code on DIN: 0xFF.00.00 serial output sequence on D0: 0xFF.00.01 input code on DIN: 0xFE.01.00.00 serial output sequence on D0: 0xFE.01.01.00 D[7:0] parallel input Code serial output code before correction Byte 1 Byte 2 Byte 3 Byte 4 MSB—LSB MSB—LSB MSB—LSB MSB—LSB 11111111 00000000 00000000 xxxxxxxx 11111111 00000000 00000000 xxxxxxxx 1111111x 00000001 00000000 xxxxxxx0 x1111111 10000000 00000000 0xxxxxxx 111111xx 00000011 00000000 xxxxxx00 xx111111 11000000 00000000 00xxxxxx 11111xxx 00000111 00000000 xxxxx000 xxx11111 11100000 00000000 000xxxxx 1111xxxx 00001111 00000000 xxxx0000 xxxx1111 11110000 00000000 0000xxxx 111xxxxx 00011111 00000000 xxx00000 xxxxx111 11111000 00000000 00000xxx 11xxxxxx 00111111 00000000 xx000000 xxxxxx11 11111100 00000000 000000xx 1xxxxxxx 01111111 00000000 x0000000 xxxxxxx1 11111110 00000000 0000000x ---time-------------------------------------------→ ↓↓ ↓↓ D[7:0] parallel input Code (corrected) serial output code after correction Byte 1 Byte 2 Byte 3 Byte 4 MSB—LSB MSB—LSB MSB—LSB MSB—LSB 11111111 00000000 00000001 xxxxxxxx 11111111 00000000 10000000 xxxxxxxx 1111111x 00000001 00000001 xxxxxxx0 x1111111 10000000 10000000 0xxxxxxx 111111xx 00000011 00000001 xxxxxx00 xx111111 11000000 10000000 00xxxxxx 11111xxx 00000111 00000001 xxxxx000 xxx11111 11100000 10000000 000xxxxx 1111xxxx 00001111 00000001 xxxx0000 xxxx1111 11110000 10000000 0000xxxx 111xxxxx 00011111 00000001 xxx00000 xxxxx111 11111000 10000000 00000xxx 11xxxxxx 00111111 00000001 xx000000 xxxxxx11 11111100 10000000 000000xx 1xxxxxxx 01111111 00000001 x0000000 xxxxxxx1 11111110 10000000 0000000x ---time------------------------------------------------------→ Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 7 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Frame Structure SOF Line 1 Frame of imageCheck data (visible) EOL SOL Last visible line EOF Line blanking period The next two graphs show the construction and transmission of a frame: Frame blanking period Figure 4. Frame Structure SOF Line 1 EOL SOL Line 4 EOL SOL Line 2 EOL SOL SOF Line 1 last visible line EOL SOL Line 3 EOL EOF SOL Line 2 time Figure 5. Data and Clock Output in CSI-1 / CCP2 Camera Mode Class-0 Transferring a Data Sequence of 0xFF011223h 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 VS and HS Timing to Generate the Correct Control Signals The VS and HS timing received from camera sensors varies. The SN65LVDS315 responds in the following way: CLK Frame Start and Line Start Frame start is indicated by a VS transition from low to high. The rising edge on HS following the VS high transition or occurring simultaneously with VS indicates the first valid data line and initiates the transmission of SOF. D[0:8] B B B B B B B B P1 P2 P3 P4 P5 SOF3 SOF4 P1 P3 P4 P5 P6 SOL3 SOL4 P1 P2 VS HS OUT (Serial) SOF1 SOF2 CLK Any additional rising edge on HS initiates transmission of SOL until VS is de-asserted to low. D[0:8] P1 P2 VS HS OUT (Serial) SOL1 SOL2 CLK Line End and Frame End A falling edge of HS indicates the end of a valid line, causing the SN65LVDS315 to transmit the EOL data word. D[0:8] P480 B B B B B B B VS HS OUT P476 P477 P478 P479 P480 EOL1 EOL2 EOL3 EOL4 (Serial) B CLK If HS and VS are set low with the same DCLK cycle, the device will transmit EOF instead of EOL. D[0:8] P480 B B B B B B B VS HS OUT P476 P477 P478 P479 P480 EOF1 EOF2 EOF3 EOF4 (Serial) B Ideally, the VS and HS falling edge occur during the same clock period. In such case, the MODE input can be kept low (MODE=0), and the response of the SN65LVDS315 output to the parallel input data looks like the following: Line 1 Blanking Line 1 Line 2 Blanking Last Line New Frame CLK D[0:8] B B B B P1 P2 P3 P4 P479 480 B B B B B B B B B B B B B B P1 P2 P3 P4 P5 180 B B B B B B B B P1 476 P477 P478 P479 P480 EOF1 EOF2 EOF3 EOF4 B B B B B B P1 P2 P3 P4 P5 VS HS OUT (Serial) SOF1 SOF2 SOF3 SOF4 P1 176 P477 P478 P479 P480 EOL1 EOL2 EOL3 EOL4 SOL1 SOL2 SOL3 SOL4 SOF1 SOF2 SOF3 SOF4 P1 Figure 6. VS and HS Timing Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 9 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 MODE = 1 MODE = 0 Caution: Some camera sensors generate a frame CLK sync (VS) signal that lasts longer than the HS of the last visible line. In such case, and with MODE=low, B D[0:7] P480 B B B B B B B the SN65LVDS315 transmits EOL during the last HS VS low transition and transmits EOF when VS transitions low. If the CSI-1 receiver can tolerate receiving EOL HS followed by EOF, it is recommended to keep the OUT P476 P477 P478 P479 P480 EOL1 EOL2 EOL3 EOL4 EOF1 (Serial) MODE input pin set to low. If the CSI-1 receiver cannot tolerate reception of an CLK EOL packet followed by an EOF packet, the SN65LVDS315 can also be configured in a mode that B B B B B B B B D[0:7] P480 allows it to predict the number of visible lines and VS generate an EOF packet at the proper time. A high MODE = High and Line_Count = Frame_ Count HS level on the the MODE input enables a line counter OUT within the SN65LVDS315 that counts every HS rising P476 P477 P478 P479 P480 EOF1 EOF2 EOF3 EOF4 B (Serial) edge while VS is high. The OMAP processors require the MODE signal to be set high. The counter value is stored into register frame_count when VS transitions low and the counter is reset to zero. When the counter reaches the value stored in frame_count, an EOF packet is transmitted instead of the EOL packet. As long as the active number of lines remains constant, this implementation ensures proper transmission of EOF. If, however, the camera sensor changes the number of transmitted lines during active transmission, the EOF will not be generated properly for that particular frame. If the number of lines transmitted by the camera sensor increases, an EOF will be sent too early. All active lines following EOF are then ignored during this particular frame. Blanking will be signaled instead. The frame_count register will be updated at the end of the frame in order to properly transmit the next frame. Line 4 - Last visible line Frame blanking period New Frame Line 1 – first visible line visible image data Line 8 - Last visible line Line blanking period visible image data Line blanking period Original Frame Line 1 – first visible line Frame blanking period [MODE=0] VS and HS edge aligned; (ideal response) B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 1 2 SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOF B B B B B B B B SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOF B B B B B B B B [MODE=1] B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 1 2 [MODE=0] VS lags behind HS by >1/fDCLK cycle SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOF B B B B B B B B B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 1 2 SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOL B B B EOF SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 6 Line 5 Line 6 Line 6 Line 7 EOL EOL EOL EOL EOL EOL EOL EOL B B B B B B B EOF SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOL B B B B B B B EOF Figure 7. If the number of lines transmitted by the camera sensor decreases, EOL will be sent improperly after the last camera line. When VS is detected low, the EOF command will follow. 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com Original Frame Line 1 – first visible line visible image data Line 8 - Last visible line Line blanking period SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Frame blanking period visible image data Line 4 - Last visible line Line blanking period New Frame Line 1 – first visible line Frame blanking period [MODE=0] VS and HS aligned (ideal response) B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 1 2 [MODE=1] SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOF B B B B B B B B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 1 2 [MODE=0] VS lags behind HS by>1/fDCLK cycle SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOF B B B B B B B B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOL B B B EOF B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOF B B B B B B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 1 B 2 B 3 B 4 B 5 B 1 2 SOF SOL SOL SOL SOL SOL SOL SOL Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 EOL EOL EOL EOL EOL EOL EOL EOL B B B B B B B EOF B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOL B B B EOF B SOF SOL SOL SOL Line 1 Line 2 Line 3 Line 4 EOL EOL EOL EOL B B B EOF B Frame Counter Size The maximum size of frame_count is limited to 2046 lines. Transmitting more than 2046 active lines within one frame causes an error if MODE is held high. Data Formats The SN65LVDS315 supports the transfer of following data formats: Table 3. Supported Data Formats DATA TYPE ABBR. COMMENT YUV 422 image data YUV422 D[0:7] inputs are used as data inputs; The host processor must be configured to receive YUV 422 data; the SN65LVDS315 is transparent to these data formats (no special configuration required); The camera sensor must provide a UYVY output data sequence (e.g. U1,Y1,V1,Y2,U2,Y3,V3,Y4,U3,Y5...) YUV 420 image data YUV420 D[0:7] inputs are used as data inputs; The host processor must be configured to receive YUV 420 data; the SN65LVDS315 is transparent to these data formats (no special configuration required); The camera sensor must provide an odd/even (or UYY.../ VYY...) output data sequence (e.g. odd like U1,Y1,Y2,U3,Y3,Y4,... followed by an even line V1,Y1,Y2,V3,Y3,Y4,...) RGB 888 image data RGB888 D[0:7] inputs are used as data inputs; The host processor must be configured to receive RGB888 data; the SN65LVDS315 is transparent to these data formats (no special configuration required); The camera sensor must provide an output data sequence of B1,G1,R1,B2,G2,R2,... RGB 565 image data RGB565 This data format can only be supported if the camera sensor outputs a 16-bit data format (two output bytes of 8-bit each) with the following format: First byte: B[0:4] and G[0:2] (G2 is MSB on device input D7) Second byte: G[3:5] and R[0:4] (R4 is MSB on device input D7) Raw bayer, 8-bit image data RAW8 D[0:7] inputs are used as data inputs; The host processor must be configured to receive RAW8 data; The camera line length should be a multiple of 4 pixel; the SN65LVDS315 is transparent to these data formats (no special configuration required); The camera sensor must provide an output data sequence of P1,P2,P3,P4,,... Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 11 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Following data formats are not supported by the SN65LVDS315: – RGB 444 image data – Raw Bayer 10-bit image data – Raw Bayer 6-bit image data – Raw Bayer 12-bit image data – Raw Bayer 7-bit image data – JPEG 8-bit data POWERDOWN MODES The SN65LVDS315 transmitter has two power-down modes to facilitate efficient power management. Shutdown Mode The SN65LVDS315 enters shutdown mode when the TXEN terminal is asserted low. This turns off all transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high impedance. Current consumption in shutdown mode is nearly zero. Standby Mode The SN65LVDS315 enters the standby mode if TXEN is high and the DCLK input signal frequency is less than 500 kHz. All circuitry except the DCLK input monitor is shut down, and all outputs enter the high-impedance state. The current consumption in standby mode is very low. When the DCLK input signal is completely stopped, the IDD current consumption is minimized. NOTE: Leaving the TXEN, FSEL or MODE input floating (left open) allows leakage currents to flow from VDD to GND. To prevent excessive leakage current, a CMOS gate must be kept at a valid logic level, either high (above VIH min) or low (below VIL min). This can be achieved by applying an external voltage or ground to these inputs. Inputs Dx, VS, HS, and DCLK incorporate bus hold, and can be left floating or tied high or low. Switching inputs also causes increased leakage currents. Only if no input signal is switching will the IDD current be at its minimum. ACTIVE MODES When TXEN is high and the DCLK input clock frequency is higher than 3 MHz, the SN65LVDS315 enters the active mode. Current consumption in the active mode depends on operating frequency and the number of data transitions in the data payload. Acquire Mode (PLL Approaches Lock) The PLL is enabled and attempts to lock to the input clock. All outputs remain in the high-impedance state. First, the PLL monitor waits until it detects stable PLL operation. If MODE is set low, the digital core will wait for one HS low-to-high transition (new frame start) before the device switches from the acquire mode to the transmit mode. This ensures that the outputs turn on when a new image frame is transmitted by the camera sensor. If MODE is set low, the digital core will wait for two (instead of one) HS low-to-high transitions before the device switches from the acquire mode to the transmit mode. This not only ensures that the device waits for a new camera frame, but also allows the internal SN65LVDS315 counter to be initiated with the proper line count. For proper device operation, the pixel-clock frequency (fDCLK) must fall within the valid fDCLK range specified under recommended operating conditions. If the pixel clock frequency is higher than 3 MHz but lower than fDCLK(min), the SN65LVDS315 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation). Transmit Mode After the PLL achieves lock, the device enters the normal transmit mode. The CLK and DOUT terminals output CSI-1 compliant serial data. 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 STATUS DETECT AND OPERATING MODES FLOW DIAGRAM The SN65LVDS315 switches between the power saving and active modes in the following way: Power Up TXEN=1 DCLK Input Inactive TXEN Low for > 10 ms Power Up TXEN=0 ShutDown Mode Standby Mode TXEN High for > 10 ms DCLK Stops or Lost TXEN Low for > 10 ms DCLK Stops or Lost DCLK Active Power Up TXEN=1 DCLK Active Transmit Mode TXEN Low for > 10 ms PLL Achieved Lock; if MODE=High: Wait for 2 Frame Counts Acquire Mode (so counter is initiated properly) Figure 8. Status Detect and Operating Modes Flow Diagram Table 4. Status Detect and Operating Modes Descriptions MODE CHARACTERISTICS CONDITIONS TXEN is low for longer than 10 µs (1) (2) Shutdown Mode Least amount of power consumption (most circuitry turned off); All outputs high impedance. Standby Mode Low power consumption (only clock activity circuit active; PLL TXEN is high for longer than 10 µs; DCLK input signal is disabled to conserve power); all outputs are high impedance. is missing or inactive. (2) Acquire Mode PLL tries to achieve lock; if MODE is high, initiate line counter (to place EOF at proper position); All outputs are high impedance. TXEN is high; DCLK input monitor detected input activity. Transmit Mode Data transfer (normal operation); transmitter serializes data and transmits data on serial output. TXEN is high and PLL is locked to the incoming clock. (1) (2) In Shutdown Mode, all SN65LVDS315 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input pin remains active. Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs without an internal bus hold (e.g. FSEL, TXEN, MODE) must be tied to a valid logic level during shutdown or standby Mode. Table 5. Mode Transition Use Cases MODE TRANSITION Shutdown -> Standby USE CASE TRANSITION SPECIFICS Set TXEN high to enable transmitter 1. TXEN high > 10 µs 2. Transmitter enters Standby mode a. All outputs are in high-impedance state. b. Transmitter turns on clock input monitor Standby-> Acquire DCLK input activity detected 1. DCLK input monitor detects clock input activity; 2. Outputs remain in high-impedance state. 3. PLL circuit is enabled Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 13 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Table 5. Mode Transition Use Cases (continued) MODE TRANSITION Acquire -> Transmit USE CASE TRANSITION SPECIFICS Device is ready to transfer data Transmit -> Standby Request transmitter to enter standby mode by stopping DCLK Transmit/Standby -> Shutdown Turn off transmitter by pulling TXEN low 1. PLL is active and approaches lock 2. PLL achieves lock within twakeup 3. Parallel data input latches into shift register. 4. Data input patterns are monitored and the line counter is initialized 5. CLK output turns on 6. DOUT turns on and sends out first serial data bit. 1. DCLK Input monitor detects missing DCLK. 2. Transmitter indicates standby, putting all outputs into high-impedance state. 3. PLL shuts down. 4. DCLK activity input monitor remains active. 1. TXEN pulled low for > tpwrdn. 2. Transmitter indicates standby by switching output CLK+ and CLK– into high-impedance state. 3. Transmitter drives DOUT into high-impedance state. 4. Most IC circuitry is shut down for least power consumption. ORDERING INFORMATION PART NUMBER PACKAGE SHIPPING METHOD SN65LVDS315RGER 24-Pin QFN 0,5 mm pitch Reel ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT –0.3 to 4 V –0.3 to 2.175 V Voltage range at any output terminal –0.5 to 2.175 V Voltage range at any input terminal –0.5 to 2.175 V ±3 kV Charged-Device Model (4) (All pins) ±500 V Machine Model (5) (All pins) ±200 V VDDIO Supply voltage range (2) VDDD, VDDA Human Body Model (3) (All pins) Electrostatic discharge Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum- rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. In accordance with JEDEC Standard 22, Test Method A114-A. In accordance with JEDEC Standard 22, Test Method C101. In accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS (1) (2) 14 PACKAGE CIRCUIT BOARD MODEL TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING RGE Low-K (2) 536 mW 6.7 mW/°C 134 mW RGE High-K 1.6 W 21.1 mW/°C >420 mW This is the inverse of the junction-to-ambient thermal resistance with the Low-K thermal metric definitions of EIA/JESD51–2 and with no air flow.. In accordance with the Low-K thermal metric definitions of EIA/JESD51–2. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS fDCLK = 3.5 MHz fDCLK = 11 MHz fDCLK = 26 MHz 10.8 17.7 21.2 mW mW mW VDDx = 1.95 V, TA = –40°C fDCLK = 3.5 MHz fDCLK = 26 MHz 15.7 26.0 mW mW Device power dissipation Maximum UNIT VDDx = 1.8 V, TA = 25°C Typical PD VALUE RECOMMENDED OPERATING CONDITIONS (1) MIN VDDIO VDDD VDDA 1.65 1.65 1.65 Supply voltage VDDn(PP) Supply voltage noise magnitude fDCLK Data clock frequency f(VDDn(PP)) = 1 Hz to 2 GHz (test set-up see Figure 15) NOM MAX UNIT 1.8 1.8 3.6 1.95 1.95 V 100 mV FSEL = 0, See Figure 1, Figure 2, Figure 3 3.5 13 FSEL = 1, See Figure 1, Figure 2, Figure 3 7 26 Standby mode (2) MHz 500 kHz tH x fDCLK DCLK Input duty cycle 0.35 0.65 TA Operating free-air temperature –40 85 °C tjit(per)DCLK DCLK RMS period jitter (3) 5 ps-rms tjit(TJ)DCLK DCLK total jitter (4) tjit(CC)DCLK DCLK peak cycle to cycle jitter (5) Measured on DCLK input (6) MODE = VIH; count the number of HS↓ transitions within one frame 1 0.05/fDCLK s 0.02/fDCLK s Icount Number of active video lines 2046 thblank Horizontal blanking time 4 UI (1/DCLK) tvblank Vertical blanking time 8 UI (1/DCLK) DCLK, D[0:1], VS, HS VIH High-level input voltage See Figure 9 0.7×VDDIO VDDIO VIL Low-level input voltage See Figure 9 0 0.3×VDDIO V tDS Data set up time prior to ↑↓ DCLK See Figure 10 2.0 ns tDH Data hold time after ↑↓ DCLK See Figure 10 2.0 ns V MODE, TXEN, FSEL VIH High-level input voltage See Figure 9 0.7×VDDO 3.6 V VIL Low-level input voltage See Figure 9 0 0.3×VDDO V (1) (2) (3) (4) (5) (6) Unused single-ended inputs must be held high or low to prevent them from floating. DCLK input frequencies lower than 500 kHz will force the SN65LVDS315 into standby mode. Input frequencies between 500 kHz and 3 MHz might activate the SN65LVDS315. Input frequencies beyond 3MHz will activate the SN65LVDS315. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. Total jitter reflects the maximum jitter amplitude observed over a time period of 1012 data bits. It is often derived by adding all deterministic jitter components (ps peak-to-peak values) and the geometric sum of all random components (ps-rms values × 14.069 for 10–12 bit error rate) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles over a random sample of 1,000 adjacent cycle pairs. For a VGA resolution of 640x480, lcount would be 480 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 15 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Supply current IDD TYP (1) MAX VDDIO = VDDD = VDDA, RL(CLK) = RL(D0) = 100 Ω, VIH=VDDIO, VIL=0V, TXEN and MODE at VDDD, typical blanking power test pattern. See Table 6 FSEL FSEL FSEL FSEL = VIL, fDCLK = 3.5 MHz = VIL, fDCLK = 11 MHz = VIH, fDCLK = 11 MHz = VIH, fDCLK = 26 MHz 4.8 7.6 5.9 9.6 VDDIO = VDDD = VDDA, RL(CLK) = RL(D0) = 100 Ω, VIH=VDDIO, VIL=0V, TXEN and MODE at VDDD, Alternating (worst-case) 1010 serial bit pattern. See Table 7 FSEL FSEL FSEL FSEL = VIL, fDCLK = 3.5 MHz = VIL, fDCLK = 11 MHz = VIH, fDCLK = 11 MHz = VIH, fDCLK = 26 MHz 5.7 8.9 7.2 11.3 8.1 11.2 9.5 13.3 Standby mode (TXEN at VDD) VDDIO = VDDD = VDDA, RL(CLK) = RL(D0) = 100 Ω, VIH=VDDIO, VIL=0 V, TXEN and MODE at VDDD, All inputs held static high (VIH) or static low (VIL) 0.2 10 0.2 10 VDDIO = VDDD = VDDA, RL(CLK) = RL(D0) = 100 Ω, VIH=VDDIO, VIL=0 V, TXEN and Mode = VIL; D[7:0] VS, HS, and DCLK left open 0.02 10 0.03 5 Shutdown mode (TXEN at GND) Standby mode (TXEN at VDD) Shutdown mode (TXEN at GND) (1) MIN UNIT mA µA All typical values are at 25°C and with 1.8 V supply unless otherwise noted. OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 0.925 1.0 V 10 mV UNIT subLVDS OUTPUTS (DOUT+, DOUT–, CLK+, and CLK–) VOCM(SS) Steady-state common-mode output voltage 0.8 ΔVOCM(SS) Change in steady-state common-mode output voltage between logic states –10 VOCM(PP) Peak-to-peak common mode output voltage |VOD| Differential output voltage magnitude |VDOUT+ – VDOUT– |, |VCLK+ – VCLK–| Δ|VOD| Change in differential output voltage between logic states ZOD Differential small-signal output impedance TXEN at VDD IOSD Differential short-circuit output current VOD = 0 V; fDCLK = 26 MHz IOZ High-impedance state output current VO = 0 V or VDD(max), TXEN at GND (1) See Figure 9, Output load see Figure 13 100 170 –10 75 mV 250 mV 10 mV 10 mA 3 µA 5 kΩ 1 –3 All typical values are at 25°C and with 1.8V supply unless otherwise noted. INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Dx, VS, HS, DCLK IIL(hold) Bus hold input current (2) VDDIO = 1.65 V and VDDIO = 3.6 V 15 100 µA IIH(hold) Bus hold input current (3) VDDIO = 1.65 V and VDDIO = 3.6 V –15 –100 µA CIN Input capacitance 1.5 pF MODE, TXEN, FSEL IIL High-level input current VIH = 0.7 VDDD, See Figure 9 –200 –0.7 200 nA IIH Low-level input current VIL = 0.3 VDDD, See Figure 9 –200 0.5 200 nA CIN Input capacitance VI = TBD (1) (2) (3) 16 1.5 pF All typical values are at 25°C and with 1.8 V supply unless otherwise noted. IIL(hold) is the input current the bus-hold input stage is able to source to maintain a low logic level; The bus-hold current becomes minimal as the input approaches GND. IIL(hold) is the least amount of current a camera output must source to overcome the bus hold and force a high signal. IIH(hold) is the input current the bus-hold input stage is able to source to maintain a high logic level. The bus-hold current becomes minimal as the input approaches VDDIO. IIL(hold) is the least amount of current a camera output must be able source to overcome the bus hold and switch to a low signal. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN TYP (1) MAX UNIT tr 20%-to-80% differential output signal rise fDCLK=3.5 MHz, See Figure 12 and time Figure 13 360 460 730 ps tf 20%-to-80% differential output signal fall time 360 460 730 ps ts(DOUT) Setup time DOUT valid before CLK+ rising edge FSEL = 0, fDCLK = 13 MHz FSEL = 1, fDCLK = 26 MHz 3.327 1.163 4.2 1.8 ns th(DOUT) Hold time DOUT valid before CLK+ ringing edge FSEL = 0, fDCLK = 13 MHz FSEL = 1, fDCLK = 26 MHz 4.627 2.463 5.4 3.0 ns tpd(L) Propagation delay time, input to serial output (data latency) 4.5/fDCLK 4.7/fDCLK 5.5/fDCLK 0.45 0.50 0.55 PARAMETER TEST CONDITIONS fDCLK=3.5 MHz, See Figure 12 and Figure 13 See Figure 11 TXEN at VDDD, VIH = VDDD, VIL=GND, RL = 100 Ω, See Figure 14 tH x fCLKO Output CLK duty cycle tGS TXEN glitch suppression pulse width (2) VIH = VDDD, VIL=GND, TXEN toggles between VIL and VIH, See Figure 16 3.8 Enable time from power down (↑TXEN) MODE at VDD; time from TXEDN pulled high to CLK and DOUT outputs enabled and transmit valid data; See Figure 16 100 tpwnup Disable time from active mode (↓TXEN) tpwrdn Enable time from standby (↑↓DCLK) twakup Disable time from standby (DCLK stopping) (1) (2) 100µs + 2×VS↑ 11 TXEN and MODE at VDD; device in standby; time measurement from DCLK starts switching to CLK and DOUT enabled and transmit valid data; See Figure 17 100 100µs + 2×VS↑ <8/fDCLK µs µs TXEN is pulled low during transmit mode; time measurement until output becomes disabled and PLL is shutdown; See Figure 16 TXEN at VDD; device in transmitting; time measurement from DCLK input signal stops starts until CLK + DOUT outputs becomes disabled and PLL is shutdown, See Figure 17 tsleep 10 µs µs 100 µs All typical values are at 25°C and with 1.8 V supply unless otherwise noted. The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed. MEASUREMENT INFORMATION (VO++VO-)/2 II D[0:7], VS, HS, FSEL, TXEN, MODE IO CLK+, DOUT+ IO CLK-, DOUT- V OD V O+ VI V OInput V OCM Output Figure 9. I/O Voltage and Current Definition Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 17 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 tDS 80% VOH D[0:7], VS, HS 20% VOL tDH 80% VOH DCLK 20% VOL tF Figure 10. Input signal Setup and Hold Time Definition tDS and tDH tCLK+ CLK- CLK+ ts(DOUT) th(DOUT) Bit(n-1) DOUT+/- Bitn Figure 11. Output signal Setup and Hold Time Definition ts(DOUT) and th(DOUT) VOD tF tR 150 mV (nom) 80% 0V 20% -150 mV (nom) Figure 12. Rise and Fall Time Definition 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 CLK+ DOUT+ R1 = 49.9 W VDx+ or VCLK+ 975 mV (nom) VDx- or VCLK- 825 mV (nom) VOD CLKDOUT- VOCM R2 = 49.9 W SN65LVDS315 C1 1 pF VOCM(PP) C2 1 pF VOCM(SS) NOTES: A. 88 MHz output test pattern on CLK output and 44 MHz output test pattern on DOUT; this is achieved by: 1. MODE = 0 2. fPCLK = 11 MHz 3. Inputs D0 ¯ = D2 ¯= D4 = D6 = VDDIO and ¯ D1 = D3 = D5¯ = D7 ¯ ¯ = GND 4. Toggle VS , HS , HS ¯, VS¯, VS , HS , HS¯, VS¯, VS , HS B. C1 and C2 include instrumentation and Fixture capacitance; +/- 20% C. R1 and R2 tolerance +/- 1% D. The measurement of VOCM(PP) and VOC(SS) are taken with test equipment bandwidth > 1 GHz Figure 13. Driver Output Voltage Test Circuit and Definitions D[0:7] pixel(n) pixel(n + 1) VDD2 DCLK tPROP CLK+ D0(n) DOUT+ D1(n) D2(n) Figure 14. tpd(L) Propagation Delay Input to Output SN65LVDS315 1W 1 Noise Generator 100 mV VDDIO VDDA 2 VDDD 10 nF GND Note: The generator regulates the noise amplitude at point 1 to the target amplitude given under the table 1.6 mH 1.8 V Supply Figure 15. Power Supply Noise Test Set-up Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 19 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 3 ms 2 ms <20 ns Glitch shorter than t GS will be ignored less than 20 ns Spike will be rejected Glitch shorter than t GS will be ignored TXEN tpwrup tpwrdn CLK+ tGS I CC tGS DCLK Transmitter aquires lock; when MODE=VDD TX also detects line count for one entire frame Transmitter output remains disabled Transmitter disabled (OFF) Transmitter Transmitter turns OFF disabled (OFF) Transmitter enabled (ON) Figure 16. Glitch Suppression Enable/Disable Time DCLK twakeup tsleep CLK+ Transmitter Disabled (OFF) Transmitter acquires lock; Transmitter enabled Transmitter Transmitter When MODE = VDD also acquires line output data valid enabled; output Disabled count for frame boundary detection, outputs (OFF) data invalid still disabled Figure 17. Standby Detection 20 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Typical Blanking Power Consumption Test Pattern During blanking VS is low, and the SN65LVDS315 data output DOUT presents a high signal. The typical power consumption test patterns during the blanking time consists of one data word. The pattern repeats itself throughout the entire measurement. Table 6. Typical IC Power Consumption Test During Blanking WORD 1 TEST PATTERN D[7:0] VS HS 0x00 0 x Maximum Power Consumption Test Pattern The maximum (or worst-case) power consumption of the SN65LVDS315 is tested using an alternating 1010 test pattern. The pattern repeats itself throughout the entire measurement. Table 7. Worst Case IC Power Consumption Test Pattern 1 WORD TEST PATTERN D[7:0] VS HS 1 0x00 1 1 2 0xFF 1 1 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 21 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 Jitter Performance The jitter performance of the SN65LVDS315 is tested using a pattern that stresses the interconnect, particularly to test for ISI. The test pattern uses very long run lengths of consecutive bits. The pattern incorporates very high and low data rates, and maximizes switching noise. The pattern is self-repeating for the duration of the test. Table 8. Jitter Test Pattern WORD 22 TEST PATTERN D[7:0] VS HS 1 0x00 1 1 2 0x00 1 1 3 0x00 1 1 4 0x01 1 1 5 0x03 1 1 6 0x07 1 1 7 0x18 1 1 8 0xE7 1 1 9 0x35 1 1 10 0x02 1 1 11 0x54 1 1 12 0xA5 1 1 13 0xAD 1 1 14 0x55 1 1 15 0xA6 1 1 16 0xA6 1 1 17 0x55 1 1 18 0x55 1 1 19 0xAA 1 1 20 0x52 1 1 21 0x5A 1 1 22 0xAB 1 1 23 0xFD 1 1 24 0xCA 1 1 25 0x18 1 1 26 0xE7 1 1 27 0xF8 1 1 28 0xFC 1 1 29 0xFE 1 1 30 0xFF 1 1 31 0xFF 1 1 32 0xFF 1 1 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS SUPPLY CURRENT IDD OVER TEMPERATURE SUPPLY CURRENT IDD OVER PCLK FREQUENCY 20 12 -40C, FSEL=low 18 IDD - Supply Current - mA 16 IDD - Supply Current - mA 85C, FSEL=low 10 13 MHz FSEL = 0 14 12 10 26 MHz FSEL = 1 8 6 25C, FSEL=low 8 6 -40C, FSEL=high 85C, FSEL=high 4 25C, FSEL=high 4 2 2 0 -50 0 50 -10 10 30 TA - Free-Air Temperature - °C -30 70 0 90 5 10 20 15 f - Frequency - MHz Figure 18. 30 Figure 19. DIFFERENTIAL OUTPUT SWING VOD AS A FUNCTION DCLK INPUT FREQUENCY vs CYCLE-TO-CYCLE OUTPUT JITTER 140 335 VOD @ 85°C 330 120 325 Cycle-to-Cycle Output Jitter - ps VOD - Differential Output Swing - mV 25 320 315 310 VOD @ 25°C 305 300 295 VOD @ -40°C 290 100 80 60 FSEL = 1 FSEL = 0 40 20 285 FSEL = Low 0 280 0 5 30 15 20 25 10 f(PCLK) - Input Pixel Clock Frequency - MHz 0 5 10 15 20 f - Frequency - MHz 25 30 Figure 20. Figure 21. BUS HOLD LEAKAGE CURRENT SN65LVDS315 OUTPUT DATA AND CLOCK SIGNAL AT 208MBPS (MAXIMUM SPEED) 4 3.5 VDDIO = 3.6 V VI - Input Voltage - V 3 2.5 2 1.5 1 VDDIO = 1.8 V 0.5 0 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 Input Current - mA 0.04 0.06 0.08 0.1 Figure 22. Figure 23. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 23 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) SN65LVDS315 OUTPUT DATA AND CLOCK SIGNAL AT 208MBPS A. 24 The asymmetrical setup and hold time is optimized to meet OMAP processor input timing. Figure 24. SN65LVDS315 OUTPUT CLOCK AND DATA(A) A. Through pcb interconnect of 80-inch of FR4 at 208Mbps Figure 25. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 APPLICATION INFORMATION PREVENTING CONTROL INPUTS FROM INCREASED LEAKAGE CURRENTS To ensure the lowest possible leakage current during standby or power down, all inputs must be held static. Any kind of input switching will cause increased leakage current. Hold inputs TXEN and MODE either at VIH or VIL. The LVDS315 incorporates a bus-hold feature on the D[0:7] inputs, DCLK, VS, and HS. This feature ensures that the input-stage leakage current is minimized during times when the camera output is in a high impedance state. Inputs with the bus-hold feature can be left open without the need of an external pullup or pulldown. This feature minimizes the power consumption of standby and power down modes in particular. A Y >75 kW BUS Hold POWER SUPPLY DESIGN RECOMMENDATION For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. SN65LVDS315 DECOUPLING RECOMMENDATION The SN65LVDS315 was designed to operate reliably in a constricted environment with other digital switching ICs. In cell phone designs, the SN65LVDS315 often shares a power supply with various other ICs. The SN65LVDS315 can operate with power supply noise as specified in Recommend Device Operating Conditions. To minimize the power supply noise floor, provide good decoupling near the SN65LVDS315 power pins. The use of four ceramic capacitors (two 0.01 µF and two 0.1 µF) provides good performance. At the very least, it is recommended to install one 0.1 µF and one 0.01 µF capacitor near the SN65LVDS315. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be minimized. Placing the capacitor underneath the SN65LVDS315 on the bottom of the pcb is often a good choice. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 25 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 VGA CAMERA APPLICATION Figure 26 shows a possible implementation of a 10-Mpixel camera transfer with 30Hz frame refresh rate. The SN65LVDS315 interfaces to the OMAP2420, a TI application processor with integrated CSI receiver. The pixel clock rate is 11 MHz, assuming ≈10% blanking overhead. The application assumes 8-bit color resolution. FPC 0.1 mF 0.1 mF 1.8 V to 3.3 V Image Sensor 11 MHz D[0:7] DCLK CLK+ CLK- 88 MHz ccp_clkp ccp_clkn DOUT+ DOUT- 88 Mbps ccp_datap ccp_datan D[0:7] OMAP2420 8 HS, VS HS, VS cam_xclk MODE GND REFCLK I2C TXEN SN65LVDS315 2 1.8 V to 3.3 V I2C Pixel CLK 1.8 V GND 1.8 V GND VDD VDDPLLD VDDLVDS VDDPLLA 1.8 V Serial Interface 2 Figure 26. Typical VGA Display Application TYPICAL APPLICATION FREQUENCIES The SN65LVDS315 in display mode supports pixel clock frequencies from 7 MHz to 26 MHz (which translates to DCLK frequencies of 56 MHz to 208 MHz). Table 9 provides a few typical display resolution examples. The table also shows the assumed blanking overhead, which often times is smaller in the final application, resulting in a lower data rate. 26 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 SN65LVDS315 www.ti.com SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 8-Bit Camera Application Table 9. Typical Application Data Rates and Serial Lane Usage DISPLAY SCREEN RESOLUTION VISIBLE PIXEL COUNT CONTROL OVERHEAD FRAME REFRESH RATE DCLK PIXEL CLOCK FREQUENCY [MHz] DATA RATE ON D0 WITH LS=0 f(CLK) 640x480 (VGA) 307,200 14% 10 Hz 3.5 MHz 28 Mbps 28 MHz 640x480 (VGA) 307,200 2% 15 Hz 4.7 MHz 38 Mbps 38 MHz 640x480 (VGA) 307,200 10% 30 Hz 10.1 MHz 81 Mbps 81 MHz 3 Mpixel 3,000,000 10% 7 Hz 23.1 MHz 185 Mbps 185 MHz 4 Mpixel 4,000,000 10% 5 Hz 22.0 MHz 176 Mbps 176 MHz 5 Mpixel 5,000,000 10% 4 Hz 22.0 MHz 176 Mbps 176 MHz 6 Mpixel 6,000,000 10% 3 Hz 19.8 MHz 158 Mbps 158 MHz 8 Mpixel 8,000,000 10% 2 Hz 17.6 MHz 141 Mbps 141 MHz 10 Mpixel 10,000,000 10% 2 Hz 22.0 MHz 176 Mbps 176 MHz 12 Mpixel 12,000,000 10% 2 Hz 25.1 MHz 201 Mbps 201 MHz Calculation Example: VGA Camera Sensor The following calculation shows an example for a VGA camera with following parameter: Visible area = 640 column display resolution: 640 x 480 frame refresh rate: 30 fps vertical visible pixel: 480 lines vertical blanking: 10 lines horizontal visible pixel: 640 columns horizontal blanking: 5 columns Visible area =480 lines Vertical blanking horizontal blanking Visible area Entire Frame Calculation of the total number of pixel and Blanking overhead: visible area pixel count: 640 x 480 = 307,200 pixel total frame pixel count: (640+5) x (480+10) = 316,050 pixel blanking overhead: (316,050–307,200) div 307,200 = 2.8% The application requires following serial link parameters: pixel clk frequency: fDCLK = 316.050 x 30 Hz = 9.5 MHz DOUT serial data rate: dR = fDCLK x8 = 76 Mbps CLK output clock rate: fCLK = f(dR) = 76 MHz Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65LVDS315 27 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS315RGER ACTIVE VQFN RGE 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVDS315RGERG4 ACTIVE VQFN RGE 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVDS315RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVDS315RGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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