TI SN74LVTH16500DLR

SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
D Members of the Texas Instruments
D
D
D
D
D
D
D
D
D
D
SN54LVTH16500 . . . WD PACKAGE
SN74LVTH16500 . . . DGG OR DL PACKAGE
(TOP VIEW)
Widebus  Family
UBT  Transceivers Combine D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
description/ordering information
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
The ’LVTH16500 devices are 18-bit universal bus
transceivers designed for low-voltage (3.3-V) VCC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
ORDERING INFORMATION
SSOP − DL
−40°C
85°C
−40
C to 85
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP − DGG
Tube
SN74LVTH16500DL
Tape and reel
SN74LVTH16500DLR
Tape and reel
SN74LVTH16500DGGR
VFBGA − GQL
TOP-SIDE MARKING
LVTH16500
LVTH16500
SN74LVTH16500GQLR
VFBGA − ZQL (Pb-free)
Tape and reel
SN74LVTH16500ZQLR
LL500
−55°C to 125°C
CFP − WD
Tube
SNJ54LVTH16500WD
SNJ54LVTH16500WD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
! "#$%&'( $#()(! (*#+&)#( $%++'( )! #* ,%-.$)#( ")' +#"%$! $#(*#+& #
!,'$*$)#(! ,'+ ' '+&! #* '/)! (!+%&'(! !)(")+" 0)++)(1
+#"%$#( ,+#$'!!(2 "#'! (# ('$'!!)+.1 ($.%"' '!(2 #* )..
,)+)&''+!
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1
SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB is active high. When
OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
A1
LEAB
OEAB
GND
CLKAB
B1
B
B
A3
A2
GND
GND
B2
B3
C
C
A5
A4
B5
D
A7
A6
VCC
GND
B4
D
VCC
GND
B6
B7
E
F
G
H
J
E
A9
A8
B8
B9
F
A10
A11
B11
B10
G
A12
A13
GND
GND
B13
B12
H
A14
A15
A17
VCC
GND
B14
A16
VCC
GND
B15
J
B17
B16
K
A18
OEBA
LEBA
GND
CLKBA
B18
K
2
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SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
FUNCTION TABLE†
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
Z
L
X
X
X
H
H
X
L
L
H
H
X
H
H
H
L
↓
L
L
H
L
↓
H
H
L
H
X
H
B0‡
X
B0§
† A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
H
L
L
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
Pin numbers shown are for the DGG, DL, and WD packages.
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3
SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH16500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH16500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH16500 . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH16500 . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH16500
SN74LVTH16500
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
−24
−32
mA
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−55
High-level input voltage
2
2
0.8
Outputs enabled
V
0.8
10
10
−40
V
ns/V
µs/V
200
125
V
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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"'!2( ,)!' #* "'3'.#,&'( )+)$'+!$ ")) )(" #'+
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$)(2' #+ "!$#((%' '!' ,+#"%$! 0#% (#$'
4
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SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VCC = 2.7 V,
IOH = −8 mA
IOH = −24 mA
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
Control inputs
Ioff
II(hold)
A or B ports
MIN
SN74LVTH16500
TYP†
MAX
MIN
−1.2
VCC−0.2
2.4
−1.2
V
V
2
IOH = −32 mA
IOL = 100 µA
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
V
0.55
IOL = 64 mA
VI = VCC or GND
0.55
±1
VI = 5.5 V
VI = 5.5 V
10
10
20
20
VCC = 3.6 V
VI = VCC
VI = 0
1
1
VCC = 0,
VI or VO = 0 to 4.5 V
VI = 0.8 V
VCC = 3 V
UNIT
VCC−0.2
2.4
±1
VCC = 3.6 V,
VCC = 0 or 3.6 V,
II
A or B ports‡
SN54LVTH16500
TYP†
MAX
TEST CONDITIONS
−5
VI = 2 V
VI = 0 to 3.6 V
µA
−5
±100
75
75
−75
−75
µA
µA
IOZPU
VCC = 3.6 V§,
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE/OE = don’t care
±100∗
± 100
µA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE/OE = don’t care
±100∗
±100
µA
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
0.19
0.19
ICC
±500
Outputs high
Outputs low
Outputs disabled
∆ICC¶
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Cio
5
5
0.19
0.19
0.2
0.2
4
4
10
10
mA
mA
pF
pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused pins at VCC or GND
§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)3' #+
"'!2( ,)!' #* "'3'.#,&'( )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!2( 2#).! '/)! (!+%&'(! +'!'+3'! ' +2 #
$)(2' #+ "!$#((%' '!' ,+#"%$! 0#% (#$'
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5
SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16500
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
tsu
Clock frequency
Pulse duration
MIN
150
MAX
MIN
150
MAX
VCC = 2.7 V
MIN
150
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
3.3
A before CLKAB↓
3.1
3.1
2.9
2.9
B before CLKBA↓
3.1
3.1
2.9
2.9
CLK high
1.5
0.6
1.4
0.5
CLK low
3.1
2.5
2.9
2.3
A or B after CLK↓
0.4
0.4
0.4
0.4
A or B after LE↓
1.7
1.7
1.6
1.6
UNIT
MAX
150
3.3
Setup time
Hold time
VCC = 2.7 V
LE high
A or B before LE↓
th
MAX
SN74LVTH16500
VCC = 3.3 V
± 0.3 V
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16500
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
VCC = 2.7 V
MAX
150
B or A
A or B
LEBA or LEAB
A or B
CLKBA or
CLKAB
A or B
OEBA or OEAB
A or B
A or B
OEBA or OEAB
tPLZ
† All typical values are at VCC = 3.3 V, TA = 25°C.
SN74LVTH16500
MIN
MAX
150
MIN
VCC = 2.7 V
TYP†
MAX
150
MIN
150
MHz
3.9
4.1
1.3
2.8
3.7
4
1.2
3.9
4.1
1.3
2.6
3.7
4
1.4
5.5
5.9
1.5
3.8
5.1
5.7
1.4
5.5
5.9
1.5
3.8
5.1
5.7
1.2
5.3
6.1
1.3
3.6
5
5.9
1.2
5.3
6.1
1.3
3.5
5
5.9
1.2
5.1
5.8
1.3
3.6
4.8
5.5
1.2
5.1
5.8
1.3
3.6
4.8
5.5
1.6
6.1
6.6
1.7
4.5
5.8
6.3
1.6
6.1
6.6
1.7
4.1
5.8
6.3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
1.2
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)3' #+
"'!2( ,)!' #* "'3'.#,&'( )+)$'+!$ ")) )(" #'+
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$)(2' #+ "!$#((%' '!' ,+#"%$! 0#% (#$'
6
VCC = 3.3 V
± 0.3 V
ns
ns
ns
ns
ns
SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tPHL/tPLH
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
2.7 V
Timing Input
LOAD CIRCUIT
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
1.5 V
VOL
tPHL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPLZ
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
1.5 V
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVTH16500DGGRE4
ACTIVE
TSSOP
DGG
56
2000
74LVTH16500DLRG4
ACTIVE
SSOP
DL
56
SN74LVTH16500DGGR
ACTIVE
TSSOP
DGG
SN74LVTH16500DL
ACTIVE
SSOP
SN74LVTH16500DLG4
ACTIVE
SN74LVTH16500DLR
ACTIVE
SN74LVTH16500GQLR
NRND
SN74LVTH16500ZQLR
ACTIVE
Pb-Free
(RoHS)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-250C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
SNPB
Level-1-240C-UNLIM
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TBD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
26-Apr-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVTH16500DGGR
DGG
56
MLA
330
24
8.6
15.8
1.8
12
24
Q1
SN74LVTH16500DLR
DL
56
MLA
330
32
11.35
18.67
3.1
16
32
Q1
SN74LVTH16500GQLR
GQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
SN74LVTH16500ZQLR
ZQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LVTH16500DGGR
DGG
56
MLA
333.2
333.2
31.75
SN74LVTH16500DLR
DL
56
MLA
336.6
342.9
41.3
SN74LVTH16500GQLR
GQL
56
HIJ
346.0
346.0
33.0
SN74LVTH16500ZQLR
ZQL
56
HIJ
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2007
Pack Materials-Page 3
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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