SL74HC4046 Phase-Locked Loop High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain opamp DEM OUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 ORDERING INFORMATION (with leading-edge sensing logic) provides digital error signals PC2OUT SL74HC4046N Plastic and PCPOUT and maintains a 0 degree phase shift between SIGIN and SL74HC4046D SOIC COMPIN signals (duty cycle is immaterial). The linear VCO produces an TA = -55° to 125° C for all packages output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. • Low Power Consumption Characteristic of CMOS Device PIN ASSIGNMENT • Operating Speeds Similary to LS/ALSTTL • Wide Operating Voltage Range: 3.0 to 6.0 V • Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN) • Low Quiescent Current: 80 µA Maximum (VCO disabled) • High Noise Immunity Characteristic of CMOS Devices • Diode Protection on all Inputs Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage SLS System Logic Semiconductor SL74HC4046 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) VCO only 3.0 6.0 V VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC4046 [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V 25 °C to -55°C ≤85 °C ≤125 °C Unit VOUT= 0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V Maximum Low -Level Input Voltage DC Coupled SIGIN , COMPIN VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V Minimum High-Level Output Voltage PCPOUT, PCn OUT VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage DC Coupled SIGIN , COMPIN VIL VOH Test Conditions VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Guaranteed Limit Maximum Low-Level Output Voltage Qa -Qh PCPOUT, PCn OUT VIN=VIH or VIL IOUT ≤ 20 µA VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA V IIN Maximum Input Leakage Current SIGIN , COMPIN VIN=VCC or GND 2.0 3.0 4.5 6.0 ±3.0 ±7.0 ±18.0 ±30.0 ±4.0 ±9.0 ±23.0 ±38.0 ±5.0 ±11.0 ±27.0 ±45.0 µA IOZ Maximum Three-State Leakage Current PC2OUT Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3,5 and 14 at VCC Pin 9 at GND; Input Leacage at Pin 3 and 14 to be excluded VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC4046 [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 1) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH, t PHL Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 1) 2.0 4.5 6.0 340 68 58 425 85 72 510 102 87 ns tPLH, t PHL Maximum Propagation Delay , SIGIN/COMPIN to PC3OUT (Figure 1) 2.0 4.5 6.0 270 54 46 340 68 58 405 81 69 ns tPLZ, t PHZ Maximum Propagation Delay , SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 2 and 3) 2.0 4.5 6.0 200 40 34 250 50 43 300 60 51 ns tPZL, t PZH Maximum Propagation Delay , SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 2 and 3) 2.0 4.5 6.0 230 46 39 290 58 49 345 69 59 ns tTLH, t THL Maximum Output Transition Time (Figure 1) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns [VCO Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to-55°C ≤85°C ≤125°C Unit VIH Minimum High-Level Input Voltage INH VOUT= 0.1 V or VCC-0.1 V IOUT≤ 20 µA 3.0 4.5 6.0 2.1 3.15 4.2 2.1 3.15 4.2 2.1 3.15 4.2 V VIL Maximum Low -Level Input Voltage INH VOUT=0.1 V or VCC0.1 V IOUT ≤ 20 µA 3.0 4.5 6.0 0.90 1.35 1.8 0.90 1.35 1.8 0.90 1.35 1.8 V VOH Minimum High-Level Output Voltage VCOOUT VIN=VIH or VIL IOUT ≤ 20 µA 3.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 3.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum Low-Level Output Voltage VCOOUT VIN=VIH or VIL IOUT ≤ 20 µA VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA SLS System Logic Semiconductor V SL74HC4046 (continued) SLS System Logic Semiconductor SL74HC4046 [VCO Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) - continued VCC Symbol IIN VVCOIN R1 Test Conditions V 25 °C to -55°C ≤85°C ≤125°C Unit VIN =Vcc or GND 6.0 0.1 1.0 1.0 µA Parameter Maximum Input Leakage Current INH, VCOIN Min Max Min Max Min Max Operating Voltage INH= VIL Range at VCOIN over the range specified for R1; For linearity see Fig.13A, Parallel value of R1 and R2 should be >2.7 kΩ 3.0 4.5 6.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 V Resistor Range 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 kΩ 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 4.5 6.0 40 40 40 No Limit R2 C1 Guaranteed Limit Capacitor Range pF [VCO Section] AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter V Guaranteed Limit 25 °C to -55°C Min ∆f/T ≤85°C Max Min Max ≤125°C Min Unit Max Frequency Stability with Temperature Changes (Figures 11A,B,C) 3.0 4.5 6.0 VCO Center Frequency (Duty Factor = 50%) (Figures 12A,B,C) 3.0 4.5 6.0 ∆fVCO VCO Frequency Linearity 3.0 4.5 6.0 See Figures 13A,B % ∂VCO Duty Factor at VCOOUT 3.0 4.5 6.0 Typical 50% % fo SLS System Logic Semiconductor %/K 3 11 13 MHz SL74HC4046 [Demodulator Section] DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C Min Max 50 50 50 300 300 300 ≤85°C Min ≤125°C Max Min Unit Max RS Resistor Range At RS > 300 kΩ the Leakage Current can Influence VDEMOUT 3.0 4.5 6.0 kΩ VOFF Offset Voltage VCOIN to VDEM OUT VI = VVCOIN = 1/2 VCC; Values taken over RS Range 3.0 4.5 6.0 See Figure 10 mV RD Dynamic Output Resistance at DEM OUT VDEMOUT = 1/2 VCC 3.0 4.5 6.0 Typical 25 Ω Ω Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit SLS System Logic Semiconductor SL74HC4046 DETAILED CIRCUIT DESCRIPTION Voltage Controlled Oscillator/Demodulator Output The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 are selected to determine the center frequency of the VCO (see typical performance curves Figure 12). R2 can be used to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the VCO range is from 0 Hz. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a narrow lock range, large swings on the VCO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 5. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to change the opposite side of the capacitor. The output from the internal logic is then taken to VCO output (Pin4). The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance, the VCO input voltage is buffered through a unity gain Op-amp, to Demod Output. This Op-amp can drive loads of 50K ohms or more and provides no loading effects to the VCO input voltage (see Figure 10). An inhibit input is provided to allow disabling of the VCO and all Op-amps (see Figure 5). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op-amps, minimizing standby power consumption. The output of the VCO is a standard high speed CMOS output with an equivalent LS-TTL fan out of 10. The VCO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. Figure 5. Logic Diagram for VCO SLS System Logic Semiconductor SL74HC4046 Phase Comparators All three phase comparators have two inputs, SIGIN and COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard SL74HC input levels are required. Both input structures are shown in Figure 6. The outputs of these comparators are essentially standard SL74HC outputs (comparator 2 is TRI-STATEABLE). In normal operation VCC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. Figure 6. Logic Diagram for Phase Comparators Phase Comparator 1 This comparator is a simple XOR gate similar to the SL74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output waveforms are shown in Figure 7. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range.The capture range for phase detector 1 is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the VCO frequency range. To see how the detector operates, refer to Figure 7. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the VCO input voltage must increase and the phase difference between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V Figure 7. Typical Waveforms for PLL Using Phase Comparator 1 This requires the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is fmax , the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase. The XOR is more susceptible to locking onto harmonics of the SIGIN than the digital phase detector 2. For instance, a signal 2 times the VCO frequency results in the same output duty cycle as a signal equal to the VCO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and VCO range should be designed to prevent locking on to harmonics. 488 TECHNICAL DATA Phase Comparator 2 This detector is a digital memory network. It consists of four flip-flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with 0 phase difference between the VCO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIGIN is leading the COMPIN. This means that the VCO’s frequency must be increased to bring its leding edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of the COMPIN is detected, the output goes TRI-STATE holding the VCO input at the loop filter voltage. If the VCO still lags the SIGIN then the phase detector will again charge up the VCO input for the time between the leading edges of both waveforms. If the VCO leads the SIGIN then when the leading edge of the VCO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIGIN is detected at which time the output disables itself again. This has the effect of slowing down the VCO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the VCO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the VCO’s frequency. Conversely, if the VCO is running faster than the SIGIN, the output of the detector will be low most of the time and the VCO’s output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI-STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire VCO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only VCO leading edges, so the comparator output will stay low, forcing the VCO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN and will cause the output to go high until the VCO leding edge is see, potentially for an entire SIGIN period. This would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 6. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIGN IN and COMPIN’s as shown in Figure 9. When the SIGN IN leads the COMPIN, the flop is set. This will charge the loop filter and cause the VCO to speed up, bringing the comparator into phase with the SIGIN. The phase angle between SIGIN and COMPIN varies from 0° to 360° and is 180° at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the VCO .When no SIGIN is present the VCO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators tors should be compared to the requirement of the system design and the appropriate one should be used. Figure 8. Typical Waveforms for PLL Using Phase Comparator 2 Figure 9. Typical Waveforms for PLL Using Phase Comparator 3 489 SL74HC4046 Figure 10. Offset Voltage at Demodulator Output as a Function of VCOIN and RS Figure 11A. Frequency Stability versus Ambient Temperature: VCC = 3.0 V Figure 11B. Frequency Stability versus Ambient Temperature: VCC = 4.5 V Figure 11C. Frequency Stability versus Ambient Temperature: VCC = 6.0 V Figure 12A. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 12B. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) 490 IN74HC4046A Figure 12C. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 12D. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 13A. Frequency Linearity versus R1,C1 and VCC Figure 13B. Definition of VCO Frequency Linearity) 491