ETC CH7203

CH7203
CHRONTEL
MPEG to TV Encoder with 16-bit Input
Features
Description
•
•
•
•
•
The CH7203 video encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTSC or PAL video signals, the CH7203 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7203 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7203 generates a 40.5 or 33.9
MHz video decoder clock, 13.5 MHz and 27 MHz
video pixel clocks, and a 16.934 or 11.289 MHz audio
decoder clock. Timing signals from the PLLs are used
to generate the horizontal and vertical sync signals
which enable operating the CH7203 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
•
•
•
•
•
•
•
•
•
Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60
16-bit YCrCb (4:2:2) input format
Simultaneous composite/S-video outputs
Triple 9-bit video DACs
27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
Low-jitter phase-locked loop circuitry operates
using a low-cost 14.31818 MHz crystal
40.5 or 33.9 MHz video decoder clock output
16.934 or 11.289 MHz audio decoder clock output
13.5 MHz and 27 MHz video pixel clock outputs
Optimized luminance and chrominance internal
filters for NTSC and PAL
HSYNC* and VSYNC* outputs for
master mode operation
Sleep mode
CMOS technology in 44-pin PLCC
5V single-supply operation
MOD 0
MOD 1
FS
C RSEN*
CR S
VDD
AVDD
R SET
IREF
BL AN KING
H ,V SYNC
GEN ERATO R
Y[7 :0],
C[7:0 ]
M
U
X
Y
FILTER
I NTE RFACE
Σ
L INE AR
U
FILTER
H SYNC*
S TAT E
VSYNC*
M ACHI NE
PC LK
A CLK
DAC
Y
9
DAC
CVB S
9
DAC
C
16
INTE RP OLATO R
2XPC LK
DC LK
9
1/ 2
V
FILTER
PLL1
PLL2
M
U
X
OSC
XI
XO/FIN
Σ
X
M
U
X
X
B LA NKIN G
S IN + COSINE
COL O R-B URST
CO NT RO L
GENERATOR
GN D
A GN D
Figure 1: Functional Block Diagram
201-0000-031 Rev 2.0, 6/2/99
1
CHRONTEL
AVDD
AGND
XI
XO/FIN
VDD
ACLK
GND
2XPCLK
VDD
DCLK
GND
6
5
4
3
2
1
44
43
42
41
40
CH7203
CRSEN*
7
39
PCLK
FS
8
38
MOD0
MOD1
9
37
VSYNC*
CRS
10
36
VDD
C[7]
11
35
HSYNC*
C[6]
12
34
GND
C[5]
13
33
GND
C[4]
14
32
Y
C[3]
15
31
CVBS
C[2]
16
30
C
C[1]
17
29
AVDD
18
19
20
21
22
23
24
25
26
27
28
C[0]
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
AGND
RSET
CHRONTEL
CH7203
Figure 2: CH7203 Pinout Diagram
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CHRONTEL
CH7203
Table 1. Pin Descriptions
Pin
Type
S ymbol
Description
1
Out
ACLK
Audio Decoder Clock Output
16.934 MHz or 11.289 MHz clock output (selectable by FS) for
MPEG audio decoder operation. The output swing is 5V.
2, 36, 42
Power
VDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of the
CH7203.
3
In
XO/FIN
Crystal Output or External F REF Input 1
A 14.31818 MHz (± 50 ppm) parallel resonance crystal may be
attached between XO/FIN and XI. An external CMOS compatible
clock can be connected to XO/FIN as an alternative.
4
In
XI
Crystal Input 1
A 14.31818 MHz (± 50 ppm) parallel resonance crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.
5, 27
Power
AGND
Analog ground
These pins provide the ground reference for the analog section of
the CH7203. These pins MUST be connected to the system
ground to prevent latchup.
6,29
Power
AVDD
Analog Supply Voltage
These pins supply the 5V power to the analog section of the
CH7203.
7
In
CRSEN*
8
In
FS
Cr Select Enable. Internally pulled-up.
CRSEN*=0, Cr, Cb data sequence is specified by the CRS pin.
CRSEN*=1, Cr, Cb data sequence is specified by the CH7203’s
internal default condition: Horizontal count = even, data is Cb;
data is Cr otherwise. State of CRS is ignored when CRSEN*=1.
See Figure 6 on page 7.
Frequency Select. Internally pulled-up
FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz
9
In
MOD1
Mode bit 1 - Internally pulled-up
This input works in conjunction with the MOD0 input to select
NTSC, PAL, or Sleep mode functions. Refer to Table 3, “Video
Encoder Modes,” on page 6 for details.
10
In
CRS
Cr Select.
When CRSEN*=0, CRS specifies the CrCb data sequence. CRS
is an alternating signal. CRS=1 indicates that C[7:0] carry the Cr
data. C[7:0] carry the Cb data otherwise. See Figure 7 on page 8.
11 – 18
In
C[7:0]
Video Input
These pins accept the “CrCb” data of the YCrCb (4:2:2) digital
video format. The Cb & Cr data appear alternately. The sequence
of the Cb, Cr data is either predefined by the internal horizontal
counter (even = Cb, odd = Cr) or as specified by pin CRS (data is
Cr for CRS=1 and Cb otherwise. For more details, please refer to
the timing diagram shown in Figure 6 on page 7.
Cb & Cr have a nominal range of 16–240, with 128 equal to zero.
Note:
1. Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note AN-19, “Tuning Clock
Outputs.”
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CHRONTEL
CH7203
Table 2. Pin Descriptions (continued)
4
Pin
Type
Symbol
Description
19-26
In
Y[7:0]
Video Input
These pins accept the “Y” data of the YCrCb (4:2:2) digital video
format. For more details, please refer to the timing diagram
shown in Figure 7 on page 8. Y has a nominal range of 16-235.
28
In
RSET
Reference Resistor
A 360 Ω resistor with short and wide traces should be attached
between RSET and ground. No other connections should be
made to this pin.
30
Out
C
Chrominance Output
A 75 Ω termination resistor with short traces should be attached
between C and ground for optimum performance.
31
Out
CVBS
Composite Output
A 75 Ω termination resistor with short traces should be attached
between CVBS and ground for optimum performance.
32
Out
Y
Luminance Output
A 75 Ω termination resistor with short traces should be attached
between Y and ground for optimum performance.
33, 34, 40, 44
Power
GND
Digital Ground
These pins provide the ground reference for the digital section of
the CH7203. These pins MUST be connected to the system
ground through independent ground vias.
35
Out
HSYNC*
Horizontal Sync Output
The horizontal sync output is generated by the CH7203 for master
mode operation. HSYNC* is an active low signal with a 5V output
swing. For additional information, please refer to the timing
diagrams shown in Figures 5 and 6 on page 7.
37
Out
VSYNC*
Vertical Sync Output
The vertical sync output is generated by the CH7203 for master
mode operation. VSYNC* is an active low signal with a 5V output
swing. For additional information, please refer to the timing
diagrams shown in Figures 5 and 7 on page 7 and 8.
38
In
MOD0
Mode bit 0 - internally pulled-up
This input works in conjunction with the MOD1 input to select
NTSC, PAL, or Sleep Mode functions. Refer to Table 3, “Video
Encoder Modes,” on page 6 for details.
39
Out
PCLK
Video Pixel Clock Output
13.5 MHz clock output. The output swing is 5V.
41
Out
DCLK
MPEG Decoder Clock Output
40.5 MHz or 33.9 MHz clock output (selectable by FS). The output
swing is 5V.
43
Out
2XPCLK
Double Pixel Clock Output
27 MHz clock output. The output swing is 5V.
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CHRONTEL
CH7203
8
Y
11 - 18
32
C[7:0]
1
41
43
39
MPEG Decoder
and
System Controller
Y[7:0]
37
35
75 Ω
2XPCLK
PCLK
C
CRSEN
38
30
Ferrite Bead
1
75 Ω
VSYNC*
HSYNC*
CH7203
CRS
9
1
ACLK
DCLK
7
10
Ferrite Bead
S-Video
Connector
19-26
CVBS
31
Ferrite Bead
1
75 Ω
MOD1
Composite
Connector
8
MOD0
28
RSET
27 pF2
3
14.318
MHz
4
360 Ω
XO/FIN
FS
XI
8
JUMPER
27 pF2
Figure 3: CH7203 Interface Diagram
Note:
1.
2.
Please refer to the Optional Output Filter diagram below
The proper value of these capacitors depends on the crystal manufacturer’s specifications. Please refer to AN06 for the
details of the calculation.
47 pF
1.2uH
1.2uH
OUTPUT
Y, C, CVBS
75 Ω
150 pF
270 pF
Figure 4: Optional Output Filter
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CHRONTEL
CH7203
General Description
The CH7203 is a fully integrated solution for converting 16-bit YCrCb (4:2:2) digital video inputs into highquality NTSC or PAL video signals while generating all essential clock signals for MPEG playback. All
essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters,
NTSC/PAL encoder, DAC’s) are contained in the CH7203 making it an essential component of any low-cost
solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Interface Diagram on
page 5.
Functional Description
The encoded luminance (Y) and color-difference (U,V) are interpolated, and filtered through digital filters to
minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed to
composite and S-video outputs, and then they are converted by the three 9-bit DACs to analog outputs.
16-bit YCrCb (4:2:2) Input
Y data is input through the Y[7:0] inputs and CrCb data is multiplexed through the C[7:0] inputs. When
CRSEN* = 1, the Cr Select input, CRS, is ignored, and all even horizontal pixels are Cb data and all odd
horizontal pixels are Cr. Refer to Figure 6 on page 7 for the definition of “even” and “odd” pixels. When
CRSEN* = 0, the alternating CRS signal specifies the CrCb sequence. CRS = 1 indicates C[7:0] carries Cr
data, and CRS = 0 indicates C[7:0] carries Cb data.
Clock/Data/Synchronization Timing
The CH7203 not only works as an NTSC/PAL encoder, it also supplies the necessary clocks (1X pixel, 2X
pixel, video system, and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks
in the video system. For this reason, the CH7203 works only in the Master mode.
It is important to note the CH7203 does not have a “pixel clock” input pin. Therefore, the timing issues related
to video pixel data being supplied from, for example, the MPEG decoder, to the CH7203 (pins Y[7:0] and
C[7:0]) need to be clarified. Assume the pixel synchronization of a system is based on the 2X pixel clock
(2XPLCK). In this type of design, 2XPCLK is distributed across the entire video system, and it is also used to
latch the incoming data appearing at pins Y[7:0] and C[7:0]. Figure 7 on page 8 shows all timing referenced
to the 2XPCLK output signal (loaded with 50pF).
Video Encoder Modes
Combinations of the two signals MOD1 and MOD0 select the various power saving modes as shown below.
Table 3 • Video Encoder Modes
MOD1
MOD0
Video Encoder Mode
1
1
NTSC
1
0
PAL
0
1
PAL-60
0
0
Sleep mode (Encoder off,both PLLs running)
Frequency Select Modes
The frequency select input FS affects the DCLK and ACLK outputs as shown below:
FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0
DCLK = 33.9 MHz, ACLK = 11.289 MHz
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CHRONTEL
CH7203
Timing Diagrams
HSYNC*
t7
VSYNC*
O DD FI E LD
MA S T ER MODE
t7
VSYNC*
E VE N F IE LD
MAS T E R MODE
Figure 5: HSYNC* and VSYNC* Timing
2XPCLK
(out)
PCLK
(out)
First (Y,C) data latched in after HSYNC* goes low
Y
(in)
C
(in)
HSYNC*
(out)
Pixel[0]
Cb
Pixel[1]
Pixel[2]
Cr
Cb
Cr
t10
64 2XPCLK cycles
Figure 6: Cb, Cr Sequence Diagram
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CHRONTEL
CH7203
Data is latched into the device on the falling edge of 2XPCLK, when PCLK is low.
t1
t2
2XPCLK
PCLK
t6
Latch
t5
Latch
Latch
H/V Sync
Pixel Data
t3
t4
Figure 7: Clock/Data/Synchronization Timing Diagram
Note: Refer to Table 8 on page 14 for timing values
ST
STAR
ART
T
OF
OF
VS
VSYN
YNC
C
AN
ALOG
LOG
S tart AN
of A
fi el d F
1
FIELD
IELD 1
1
5 23
520
520
5 24
521
521
52 5
522
522
523
523
1
524
524
2
525
525
3
1
14
Pre -e qu al iz in g
pu lse ve rtica l
2
2
5
3
36
4
47
Ver ti ca l syn c
p ul se i nte rva l
6
69
5
58
10
7
7
8
811
12
9
9
P os t- eq ua li zin g
p ul se i nte rva l
L in e
ReAN
fereA
nLOG
ce
AN
A
LOG
ve rtic al
su bcar
rie r ph a se
F
IELD
2
coF
loIELD
r fi el d 12
t1 +V in terv al
2 61
258
258
26 2
259
259
26 3
260
260
26 4
261
261
2 65
262
262
26 6
263
263
2 67
264
264
2 68
265
265
2 69
266
266
27 0
267
267
2 71
268
268
272
269
269
27 3
270
270
2 74
271
271
275
272
272
START
OF
VSYNC
S ta rt of
fi el d 2
Re
fere
n ce
AN
ALOG
su
b -ca rrie1r p ha se
FIELD
t2 +V
co
lo r fi el d 2
52 3
520
5 24
521
52 5
522
1
523
S ta rt of
fi el d 3
2
524
3
525
14
25
36
7
4
85
10
7
9
6
811
912
Re fere
ANnAce
LOG
su b-Fca
rrie r ph a se
co lo rIELD
fie ld 3 2
t3 +V
2 61
258
26 2
259
263
260
26 4
261
2 65
262
26 6
263
26 7
264
26 8
265
2266
69
27 0
267
27 1
268
272
269
273
270
2 74
271
27 5
272
Sta rt o f
fie ld 4
R efe re nce
su b-c arr ie r ph as e
c ol or fie ld 4
Figure 8: Interlaced NTSC Timing Diagram
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CHRONTEL
CH7203
START
OF
VSYNC
62
620
0
621
622
623
624
625
ANAL
ALO
G
OG
FIELD 1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
99
10
10
ANAL
ALO
G
OG
FIELD 2
308
309
310
311
312
313
314
31
315
5
31
316
6
31
317
7
31
318
8
31
319
9
32
320
0
32
321
1
32
322
2
32
32
33
ANAL
ALO
G
OG
FIELD 3
62
620
0
621
622
623
624
625
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
99
10
10
ANAL
ALO
G
OG
FIELD 4
308
309
310
BU
UR
RST
ST
B
BLAN
LANK
KIN
G
B
ING
IN TE R VA L S
311
312
313
314
31
315
5
31
316
6
31
317
7
31
318
8
31
319
9
32
320
0
32
321
1
32
322
2
32
33
32
4
3
BU
UR
RST
ST P
PH
ASE
= RE
EF
ERE
EN
CE
E PH
PHASE = 135°° RELA
ELAT
IVE TO
B
HAS
E=
FE
NC
TIVE
TO U
PAL
AL SW
SWIT
ITC
CH
H= 0
0,
COM
N2
ENT
P
, +V C
OMPO
PON
1
BU
UR
RST
ST P
PH
ASE
= RE
EF
ERE
EN
CE
E PH
PHASE+ 90°° = 22
225
IV
E TO U
B
HAS
E=
FE
NC
5°° RELA
ELAT
TI
VE
PAL
AL SW
SWIT
ITC
CH
H= 1
1,
VC
CO
OM
MPO
PONENT
P
, -V
Figure 9: Interlaced PAL Timing Diagram
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CHRONTEL
CH7203
Color / Level
mA
V
Wh ite
Yellow
24.60
26.59
22.85
24.59
0.922
0.997
0.857
0.922
Cyan
Green
19.85
21.30
18.11
19.30
0.745
0.799
0.679
0.724
Magenta
Red
15.23
16.15
13.49
14.15
0.571
0.606
0.506
0.531
Blue
Black
Blank
10.49
11.00
8.74
9.00
7.49
7.58
0.393
0.413
0.327
0.338
0.281
0.284
Sync
0.50
0.00
0.019
0.000
COLOR BARS :
Note: 1 100% amplitude, 100% saturation color bars are shown
Note: 2 Vref = 1.235V, RSET = 360 Ω, 75 Ω doubly terminated load
Figure 10: NTSC Y (Luminance) Output Waveform
Color / Level
mA
V
Wh ite
Yellow
24.60
26.83
22.85
24.69
0.922
1.006
0.857
0.926
Cyan
Green
19.85
21.19
18.11
19.05
0.745
0.795
0.679
0.715
Magenta
Red
15.23
15.70
13.49
13.57
0.571
0.589
0.506
0.509
Blue
Black
Blank
Blank
10.49
10.21
8.74
8.08
7.49
0.393
0.383
0.327
0.303
0.281
Sync
0.50
0.00
0.019
0.000
COLOR BARS :
Note: 1 100% amplitude, 100% saturation color bars are shown
Note: 2 Vref = 1.235V, RSET = 360 Ω, 75 Ω doubly terminated load
Figure 11: PAL Y (Luminance) Video Output Waveform
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CHRONTEL
Color / Level
CH7203
mA
V
Cyan / Red
Green / Magenta
22.60
25.37
21.85
24.59
0.848
0.951
0.819
0.922
Yellow / Blue
19.61
22.16
0.735
0.831
Peak Burst
15.98
18.15
0.599
0.681
Blank
12.49
14.294
0.468
0.536
Peak Burst
8.99
10.44
0.337
0.391
COLOR BARS :
3.579545 MHz Color Burst
(9 cycles)
Yellow / Blue
5.37
6.43
0.201
0.241
Green / Magenta
Cyan / Red
3.12
4.00
2.37
3.21
0.117
0.150
0.089
0.121
Note: 1 100% amplitude, 100% saturation color bars are shown
Note: 2 Vref = 1.235V, RSET = 360Ω, 75 Ω doubly terminated load
Figure 12: NTSC C (Chrominance) Video Output Waveform
Color / Level
mA
V
Cyan / Red
Green / Magenta
22.60
27.06
21.85
26.22
0.848
1.015
0.819
0.983
Yellow / Blue
19.61
23.63
0.735
0.886
Peak Burst
16.23
19.21
0.609
0.720
Blank
12.49
15.24
0.468
0.572
Peak Burst
8.74
11.28
0.328
0.423
Yellow / Blue
5.37
6.85
0.201
0.257
Green / Magenta
Cyan / Red
3.12
4.27
2.37
3.43
0.117
0.160
0.089
0.129
COLOR BARS :
4.433619 MHz Color Burst
(10 cycles)
Note: 1 100% amplitude, 100% saturation color bars are shown
Note: 2 Vref = 1.235V, RSET = 360Ω, 75 Ω doubly terminated load
Figure 13: PAL C (Chrominance) Video Output Waveform
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CHRONTEL
BLACK
BLUE
0.997
1.026
RED
26.59
27.37
BLUE
White
COLOR BARS :
MAGENTA
1.271
1.217
RED
33.89
32.45
MAGENTA
Peak Chroma
GREEN
V
CYAN
mA
YELLOW
Color / Level
WHITE
CH7203
3.579545 MHz
Color Burst
(9 Cycles)
Peak Burst
Black
Blank
12.00
11.43
9.00
9.62
7.58
8.16
0.450
0.429
0.338
0.360
0.306
0.284
Peak Burst
4.32
3.72
0.162
0.139
Sync
0.50
0.00
0.019
0.000
Figure 14: Composite NTSC Video Output Waveform
33.89
33.08
1.271
1.240
White
27.37
26.83
1.026
1.006
COLOR BARS :
BLACK
Peak Chroma
GREEN
V
CYAN
mA
YELLOW
Color / Level
WHITE
Note: Vref = 1.235V, RSET = 360 Ω, 75Ω doubly terminated load
4.433619 MHz
Color Burst
(10 Cycles)
Peak Burst
12.00
12.04
0.450
0.452
Blank/Black
8.64
8.08
0.324
0.303
Peak Burst
4.58
4.12
0.171
0.154
Sync
0.50
0.00
0.019
0.000
Figure 15: Composite PAL Video Output Waveform
Note: Vref = 1.235V, RSET = 360 Ω, 75 Ω doubly terminated load
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CHRONTEL
CH7203
Electrical Specifications
Table 4 • Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
VDD relative to GND
- 0.5
7.0
V
Input voltage of all digital pins 1
GND - 0.5
VDD + 0.5
V
T SC
Analog output short circuit duration
Indefinite
Sec
Ambient operating temperature
- 55
125
°C
TAMB
TSTOR
Storage temperature
- 65
150
°C
TJ
Junction temperature
150
°C
TVPS
Vapor phase soldering (one minute)
220
°C
PMAX
Maximum power dissipation
TBD
W
Note:
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal
operating conditions is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
Table 5 • Recommended Operating Conditions
Symbol
AVDD
DVDD
TA
RL
Description
Analog supply voltage
Digital supply voltage
Ambient operating temperature
Output load to DAC outputs
Min
0
Typ
5.00
5.00
25
37.5
Max
Units
70
°C
Ω
Table 6 • Electrical Characteristics (Operating Conditions: TA = 0°C – 70°C, VDD = 5V ± 5%)
Symbol
Note:
Description
Min
Typ
Max
Unit
Video D/A resolution
9
9
9
Bits
Full scale output current
33.08
mA
Video level error
using internal reference
10
%
Total Current Consumption
135
mA
As applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified.
RSET = 360 Ω, and NTSC CCIR601 operation. Typical values are based on 25° C and +5V.
Table 7 • Digital Inputs / Outputs
Symbol
VOH
VOL
VIH
VIL
I PU
ILK
CDIN
CDOUT
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input internal pull-up current
Input leakage current
Input capacitance
Output capacitance
201-0000-031 Rev 2.0, 6/2/99
Test Condition @ TA = 25°C
IOH = - 400 µA
IOL = 3.2 mA
Min
2.4
Typ
2.0
GND - 0.5
5
-10
f = 1 MHz, VIN = 2.4V
7
10
Max
Units
V
0.4
V
VDD + 0.5
V
0.8
V
25
µA
10
µA
pF
pF
13
CHRONTEL
CH7203
Electrical Specifications (continued)
Table 8 • AC Characteristics
Symbol
Description
Min
Typ
Max
t1
2XPCLK
t2
2XPCLK high time
t3
Pixel/Sync setup time
6
ns
t4
Pixel/Sync hold time
3
ns
t5
Sync active delay time
3
ns
t6
Sync inactive delay time
t7
HSYNC* to VSYNC* delay
t10
HSYNC* pulse width
64 x t1
VSYNC* delay time
17
VSYNC* pulse width
2.0
Test
Conditions:
37
Units
14.8
30
ns
22.2
ns
17
ns
30
ns
ns
20
ns
Hor. lines
Unless otherwise specified, the testing conditions are the same as in Table 5, “Recommended Operating Conditions,”
on page 13. TTL input values are 0 – 3V, with input rise / fall times < 3 ns, measured between the VIL and VIH. Timing
reference points at 50% for non-TTL inputs and outputs. TTL reference points at 1.5V for inputs and outputs. Analog
output load < 10 pF.
Since the CH7203 does not have a pixel clock input, all input signal timing is chosen with respect to the output clock
timing of 2XPCLK and PCLK. PCLK can be used at the “Qualifying” clock for certain MPEG decoders.
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201-0000-031 Rev 2.0, 6/2/99
CHRONTEL
CH7203
ORDERING INFORMATION
Part number
CH7203-V
Package type
Number of pins
Voltage supply
PLCC
44
5V
Chrontel
2210 O’Toole Avenue
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
19 97 Ch rontel , Inc. All R igh ts Re served .
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201-0000-031 Rev 2.0, 6/2/99