TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 D D D D D D D DWP PACKAGE (TOP VIEW) Dedicated PWM Input Port Optimized for Reversible Operation of Motors Two Input Control Lines for Reduced Microcontroller Overhead Internal Current Shutdown of 5 A 40 V Load Dump Rating Integrated Fault Protection and Diagnostics CMOS Compatible Schmitt Trigger Inputs for High Noise Immunity GNDS VCC DIR VCC OUT1 OUT1 GND PWM GND GNDS description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 GNDS VCC STATUS2 VCC OUT2 OUT2 GND STATUS1 GND GNDS The TPIC0107B is a PWM control intelligent H-bridge designed specifically for dc motor applications. The device provides forward, reverse, and brake modes of operation. A logic supply voltage of 5 V is internally derived from VCC. The TPIC0107B has an extremely low rDS(on), 280 mΩ typical, to minimize system power dissipation. The direction control (DIR) and PWM control (PWM) inputs greatly simplify the microcontroller overhead requirement. The PWM input can be driven from a dedicated PWM port while the DIR input is driven as a simple low speed toggle. The TPIC0107B provides protection against over-voltage, over-current, over-temperature, and cross conduction faults. Fault diagnostics can be obtained by monitoring the STATUS1 and STATUS2 terminals and the two input control lines. STATUS1 is an open-drain output suitable for wired-or connection. STATUS2 is a push-pull output that provides a latched status output. Under-voltage protection ensures that the outputs, OUT1 and OUT2, will be disabled when VCC is less than the under-voltage detection voltage V(UVCC). The TPIC0107B is designed using TI’s LinBiCMOS process. LinBiCMOS allows the integration of low power CMOS structures, precision bipolar cells, and low impedance DMOS transistors. The TPIC0107B is offered in a 20-pin thermally enhanced small-outline package (DWP) and is characterized for operation over the operating case temperature of –40°C to 125°C. FUNCTION TABLE DIR PWM OUT1 OUT2 0 0 HS HS Brake, both HSDs turned on hard 0 1 HS LS Motor turns counter clockwise 1 0 HS HS Brake, both HSDs turned on hard 1 1 LS HS Motor turns clockwise MODE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 block diagram VCC OverCurrent Protection HSD PWM OverVoltage Detection Logic DIR STATUS1 STATUS2 DMOS Driver 5V Reg. Charge Pump (2 MHz) UnderVoltage Detection DMOS Driver OUT2 OUT1 OpenCircuit Detect OverTemperature Detection Load-Dump Protection DMOS Driver DMOS Driver OverCurrent Protection LSD GND Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DIR 3 I Direction control input GND 7, 9, 12, 14 I Power ground GNDS 1, 10, 11, 20 I Substrate ground OUT1 5, 6 O Half-H output. DMOS output OUT2 15, 16 O Half-H output. DMOS output PWM 8 I PWM control input STATUS1 13 O Status output 18 O Latched status output 2, 4, 17, 19 I Supply voltage STATUS2 VCC NOTE: It is mandatory that all four ground terminals plus at least one substrate terminal are connected to the system ground. Use all VCC and OUT terminals. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 schematics of inputs and outputs STATUS1 STATUS2 DIR/PWM absolute maximum ratings over operating case temperature range (unless otherwise noted)† Power supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 33 V Logic input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Load dump (for 400 ms, TC = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Status output voltage range, VO(status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Continuous power dissipation, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 125°C POWER RATING 25 W –0.2 W/°C 16 W 5W recommended operating conditions Supply voltage, VCC Operating case temperature, TC Switching frequency, fPWM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 6 18 UNIT –40 125 °C 2 kHz V 3 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 electrical characteristics over recommended operating case temperature range and VCC = 5 V to 6 V (unless otherwise noted) PARAMETER rDS( DS(on)) TEST CONDITIONS Static drain-source on-resistance ((per transistor)) I(BR) = 1 A MIN TYP MAX LSD TJ = 25°C TJ = 150°C 550 HSD TJ = 25°C TJ = 150°C 600 850 870 10 40 mΩ mΩ I(QCD) V(UVCC(OFF)) Open circuit detection current Under voltage detection on VCC, switch off voltage See Note 1 5 V V(UVCC(ON)) V(STL) Under voltage detection on VCC, switch on voltage See Note 1 5.2 V STATUS low output voltage 0.8 V V(ST2H) I(ST(OFF)) STATUS2 high output voltage IO = 100 µA, See Note 1 IO = 20 µA, See Note 1 STATUS output leakage current V(ST) = 5 V, See Note 1 VIL VIH Low level logic input voltage ∆VI IIH mA 5.4 V 5 µA –0.3 0.5 V High level logic input voltage 3.6 7 V Hysteresis of input voltage 0.3 High level logic input current VIH = 3.5 V 3 100 UNIT 2 V 10 50 µA NOTE 1: The device functions according to the function table for VCC between V(UVCC) and 5 V (no parameters specified). STATUS outputs are not defined for VCC less than V(UVCC). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 electrical characteristics over recommended operating case temperature and supply voltage ranges (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Static drain-source on-resistance (per transistor) IBR = 1 A TYP TJ = 25°C TJ = 150°C VCC = 6 V to 9 V VCC = 9 V to 18 V 400 TJ = 25°C VCC = 6 V to 9 V VCC = 9 V to 18 V 280 TJ = 150°C VCC = 6 V to 9 V VCC = 9 V to 18 V LSD rDS(on) DS( ) MIN VCC = 6 V to 9 V VCC = 9 V to 18 V HSD MAX 280 340 620 430 340 640 10 400 560 40 100 Open circuit detection current Static thermal shutdown temperature See Notes 3 and 4 140 TSDD Dynamic thermal shutdown temperature See Notes 3 and 5 160 ICS Current shutdown limit VCC = 6 V to 9 V VCC = 9 V to 18 V 4.8 7.5 5 7.5 I(CON) Continuous bridge current TJ = 125°C, Operating lifetime 10,000 hours, (see Figure 1) V(OVCC) V(STL) Over voltage detection on VCC V(ST2H) I(ST(OFF)) STATUS2 high output voltage IO = 100 µA IO = 20 µA STATUS output leakage current V(ST) = 5 V VIL VIH Low level logic input voltage High level logic input voltage ∆VI IIH Hysteresis of input voltage 0.3 mA °C 3.9 VIH = 3.5 V mΩ °C 27 High level logic input current mΩ 560 I(QCD) TSDS STATUS low output voltage UNIT 380 A 3 A 36 V 0.8 V 5.4 V 5 µA –0.3 0.8 V 3.6 7 V 2 V 10 50 µA NOTES: 2. The device functions according to the function table for VCC between 18 V and V(OVCC), but only up to a maximum supply voltage of 33 V (no parameters specified). Exposure beyond 18 V for extended periods may affect device reliability. 3. Exposure beyond absolute-maximum-rated condition of junction temperature may affect device reliability. 4. No temperature gradient between DMOS transistor and temperature sensor. 5. With temperature gradient between DMOS transistor and temperature sensor in a typical application (DMOS transistor as heat source). switching characteristics over recommended operating case temperature and supply voltage ranges (unless otherwise noted) PARAMETER tout(on) t( ) SR TEST CONDITIONS High-side driver turn-on time Low-side driver turn-on time Slew rate, low-to-high sinusoidal (δV/δt) Slew rate, high-to-low sinusoidal (δV/δt) td(QCD) Under current spike duration to trigger open circuit detection td(CS) Delay time for over current shutdown VDS( A DS(on))<1 V at 1 A, VCC = 13 13.2 2V 2V VCC = 13 13.2 V, IO = 1 A resistive load VCC = 5 V to 18 V MIN TYP MAX 100 100 UNIT µs 1 6 1 6 1 10 ms 10 25 µs MIN MAX UNIT 5 °C/W 97 °C/W 5 V/µs thermal resistance PARAMETER RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case thermal resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION Maximum continuous bridge current versus time based on 50 FITs at 100,000 hours operating life (90% confidence model) I (CON) – Continuous Bridge Current – A 10 TJ = 75°C TJ = 150°C 5 TJ = 100°C TJ = 125°C 0 0 10 20 30 40 50 60 70 80 90 100 t – Time × 1000-h Figure 1. Electromigration Reliability Data Example: Average continuous bridge current, ICON 6 Average junction temperature, TJ Operating lifetime of device based on electromigration 2A 125°C >20,000 h 3A 125°C >10,000 h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION operating wave forms DIR (Low) PWM STATUS1 STATUS2 OUT1 (High) OUT2 Open Circuit <1 ms (min.) Figure 2. Open Circuit DIR (Low) PWM STATUS1 STATUS2 ÓÓ ÓÓ ÓÓ ÓÓ OUT1 OUT2 ÓÓ ÓÓ ÓÓ ÓÓ ÓÓÓÓÓ ÓÓÓÓÓ ÓÓÓÓÓ ÓÓÓÓÓ Short Circuit ILIM Bridge Current Figure 3. Short Circuit (e.g., OUT2 to VCC) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION operating wave forms (continued) DIR (Low) PWM STATUS1 STATUS2 ÓÓÓÓÓÓ ÓÓÓÓÓÓ ÓÓÓÓÓÓ ÓÓÓÓÓÓ OUT1 OUT2 ÓÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓÓ Over Temperature Figure 4. Over Temperature DIR PWM STATUS1 (High) STATUS2 (High) OUT1 OUT2 Brake Brake Clockwise Rotation Brake CounterClockwise Rotation Figure 5. No Fault 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 PRINCIPLES OF OPERATION protective functions and diagnostics† over current/short circuit‡ The TPIC0107B detects shorts to VCC, ground, or across the load being driven, by comparing the VDS voltage drop across the DMOS outputs against the threshold voltage. The DMOS outputs of the TPIC0107B will be disabled and the fault flags will be generated 10 µs after an over-current or short-circuit fault is detected. This 10 µs delay is long enough to serve as a de-glitch filter for high current transients, yet short enough to prevent damage to the DMOS outputs. The DMOS outputs remain latched off until either DIR or PWM input is toggled. In cases where the outputs have a continuous short-to-ground with a current rise time faster than 0.5 A/µs, the over-current shutdown threshold will decrease to 3 A to reduce power dissipation. This reduction to 3 A is achieved since the DMOS outputs will not be fully enhanced when the over-current threshold is reached if the current rise time exceeds 0.5 A/µs. Over-current and/or short-circuit protection is provided up to VCC = 16.5 V and a junction temperature of 90°C. over temperature The TPIC0107B disables all DMOS outputs and the fault flags will be set when TJ ≥140°C (min.). The DMOS outputs remain latched off until either DIR or PWM input is toggled. under voltage The TPIC0107B disables all DMOS outputs when VCC ≤V(UVCC). The outputs will be re-enabled when VCC ≥V(UVCC). No fault flags are set when under-voltage lockout occurs. over voltage In order to protect the DMOS outputs from damage caused by excessive supply voltage, the TPIC0107B disables all outputs when VCC ≥V(OVCC). Once VCC ≤V(OVCC), either DIR or PWM input must be toggled to re-enable the DMOS outputs. cross conduction Monitoring circuitry for each transistor detects whether the particular transistor is active to prevent the HSD or LSD of the corresponding half H-bridge from conducting. open circuit During operation, the bridge current is controlled continuously. If the bridge current is >10 mA (min.) for a period >1 ms (min.), the fault flags are set. However, the output transistors will not be disabled. † All limits mentioned are typical values unless otherwise noted. ‡ If a short circuit occurs (i.e., the over-current detection circuitry is activated) at a supply voltage higher than 16.5 V and a junction temperature higher than 90°C, damage to the device may occur. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 PRINCIPLES OF OPERATION DIAGNOSTICS TABLE (see Note 6) DIR PWM OUT1 OUT2 STATUS1† STATUS2 Normal operation 0 0 1 1 0 1 0 1 HS HS HS LS HS LS HS HS 1 1 1 1 1 1 1 1 Open circuit between OUT1 and OUT2 0 0 1 1 0 1 0 1 HS HS HS LS HS LS HS HS 1 0 1 0 1 0 1 0 Short circuit from OUT1 to OUT2 (see Notes 7 and 8) 0 1 1 1 X X X X 0 0 0 0 Short circuit from OUT1 to GND (see Notes 7 and 8) 0 1 0 0 0 1 X X X X X X 0 0 0 0 0 0 Short circuit from OUT2 to GND (see Notes 7 and 8) 0 1 1 0 0 1 X X X X X X 0 0 0 0 0 0 Short circuit from OUT1 to VCC (see Notes 7 and 8) 1 1 X X 0 0 Short circuit from OUT2 to VCC (see Notes 7 and 8) 0 1 X X 0 0 Over temperature 0 0 1 1 0 1 0 1 Z Z Z Z Z Z Z Z 0 0 0 0 0 0 0 0 FLAG † When wired with a pull-up resistor SYMBOL VALUE 0 Logic low 1 Logic high HS High-side MOSFET conducting LS Low-side MOSFET conducting Z No output transistors conducting X Voltage level undefined NOTES: 6. All input combinations not stated result in STATUS output = 1. 7. STATUS1 active for a minimum of 3 µs. 8. STATUS2 active until an input is toggled. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 TYPICAL CHARACTERISTICS VCC = 9.18 V 300 200 100 0 –40 –20 20 40 60 80 100 TJ – Junction Temperature – °C 0 120 140 r DS(on) – Static Drain-Source On-Resistance – m Ω STATIC-DRAIN-SOURCE ON-RESISTANCE vs SUPPLY VOLTAGE 400 600 HSD, TJ = 125°C 500 LSD, TJ = 125°C 400 300 LSD, TJ = 25°C 200 HSD, TJ = 25°C 100 0 0 5 Figure 6 20 10 15 VCC – Supply Voltage – V 25 Figure 7 OUTPUT STAGE TURN-ON TIME vs JUNCTION TEMPERATURE 20 t out(on) – Output Stage Turn-On Time – µ s r DS(on) – Static Drain-Source On-Resistance – m Ω STATIC DRAIN-SOURCE ON-RESISTANCE vs JUNCTION TEMPERATURE 15 HSD, VCC = 13.2 V 10 LSD, VCC = 13.2 V 5 0 –40 –20 0 20 40 60 80 100 TJ – Junction Temperature – °C 120 140 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 APPLICATION INFORMATION 5V VCC 100 kΩ VCC DIR PWM OUT1 TPIC0107B STATUS1 M 100 nF 47 µF† OUT2 STATUS2 GND GNDS CONTROL DIAGNOSTIC Microcontroller † Necessary for isolating supply voltage or interruption (e.g., 47 µF). NOTE: If a STATUS output is not connected to the appropriate microcontroller input, it shall remain unconnected. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC0107B PWM CONTROL INTELLIGENT H-BRIDGE SLIS067 – NOVEMBER 1998 MECHANICAL DATA DWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 20-PIN SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 20 0.010 (0,25) M 11 Thermal Pad (See Note D) 0.419 (10,65) 0.400 (10,16) 0.299 (7,59) 0.010 (0,25) NOM 0.293 (7,45) Gage Plane 1 10 0.010 (0,25) A 0°– 8° 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.006 (0,15) 0.004 (0,10) 0.002 (0,05) PINS ** 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4147575/A 02/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated