SGUS030B – APRIL 2000 – REVISED MAY 2001 D Highest Performance Floating-Point Digital D D D D D Signal Processor (DSP) SMJ320C6701 – 7-, 6-ns Instruction Cycle Time – 140-, 167-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – Up to 1 GFLOPS Performance – Pin-Compatible With ’C6201 Fixed-Point DSP SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing Operating Temperature Ranges – Extended (W) –55°C to 115°C – Extended (S) –40°C to 90°C VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core – Eight Highly Independent Functional Units: – Four ALUs (Floating- and Fixed-Point) – Two ALUs (Fixed-Point) – Two Multipliers (Floating- and Fixed-Point) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Hardware Support for IEEE Single-Precision Instructions – Hardware Support for IEEE Double-Precision Instructions – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization D 1M-Bit On-Chip SRAM D D D D D D D D D D – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 429-Pin Ceramic Ball Grid Array (CBGA) Package (GLP Suffix) 0.18-µm/5-Level Metal Process – CMOS Technology 3.3-V I/Os, 1.9-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2001, Texas Instruments Incorporated ! " #$%! " &$'(# ! ) !%* )$#!" # ! "&%## !" &% !+% !%" %, " "!$%!" "! ) ) - !.* )$#! &#%""/ )%" ! %#%"" (. #($)% !%"!/ (( & %!%"* POST OFFICE BOX 1443 &)$#!" #&( ! ! 0112 (( & %!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!"2 &)$#! &#%""/ )%" ! %#%"" (. #($)% !%"!/ (( & %!%"* • HOUSTON, TEXAS 77251–1443 1 SGUS030B – APRIL 2000 – REVISED MAY 2001 GLP PACKAGE (BOTTOM VIEW) AA Y W V U T R P N M L K J H G F E D C B A 3 1 2 5 4 9 7 6 8 11 10 13 12 17 15 14 16 19 18 21 20 description The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 device characteristics Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the ’C6701 Processors CHARACTERISTICS DESCRIPTION Device Number SMJ320C6701 On-Chip Memory 512-Kbit Program Memory 512-Kbit Data Memory (organized as 2 blocks) Peripherals 2 Mutichannel Buffered Serial Ports (McBSP) 2 General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF) Cycle Time 7 ns at 140 MHz, and 6 ns at 167 MHz Package Type 27 mm × 27 mm, 429-Pin BGA (GLP) Nominal Voltage 1.9 V Core 3.3 V I/O functional and CPU block diagram ’C6701 Digital Signal Processor Program Bus SDRAM SBSRAM 32 SRAM External Memory Interface (EMIF) ROM/FLASH Internal Program Memory 1 Block Program/Cache (64K Bytes) Program Access/Cache Controller I/O Devices ’C67x CPU Instruction Fetch Timer 1 Instruction Dispatch 16 Host Port Interface (HPI) Data Bus DMA Buses Multichannel Buffered Serial Port 1 Control Registers Control Logic Instruction Decode Multichannel Buffered Serial Port 0 Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL Timer 0 Data Path B B Register File In-Circuit Emulation .D2 .M2† .S2† .L2† Interrupt Control .L1† .S1† .M1† .D1 Direct Memory Access Controller (DMA) (4 Channels) PLL (x1, x4) Data Path A A Register File PowerDown Logic Data Access Controller Test Internal Data Memory (64K Bytes) 2 Blocks of 8 Banks Each † These functional units execute floating-point instructions. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SGUS030B – APRIL 2000 – REVISED MAY 2001 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 CPU description (continued) ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ src1 .L1† src2 dst long dst long src LD1 32 MSB ST1 long src long dst dst .S1† src1 Data Path A 8 8 32 32 8 8 Á Á Á Á src2 dst src1 † .M1 src2 LD1 32 LSB DA1 DA2 LD2 32 LSB Á Á Á Á .D1 .D2 dst src1 src2 src2 src2 .S2† LD2 32 MSB ST2 Á Á long src long dst dst .L2† src2 src1 Register File A (A0–A15) 1X .M2† src1 dst Data Path B ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á 2X src2 src1 dst src1 dst long dst long src Á Á Á Á 8 Á Á Á Á Register File B (B0–B15) 8 32 32 8 Á Á Á Á 8 † These functional units execute floating-point instructions. Control Register File Figure 1. SMJ320C67x CPU Data Paths POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SGUS030B – APRIL 2000 – REVISED MAY 2001 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 Boot Mode BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 Little ENDIAN Big ENDIAN LENDIAN CLOCK/PLL PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF TMS TDO TDI TCK TRST EMU1 EMU0 IEEE Standard 1149.1 (JTAG) Emulation RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL HBE1 HBE0 Half-Word/Byte Select Figure 2. CPU and Peripheral Signals 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HAS HR/W HCS HDS1 HDS2 HRDY HINT SGUS030B – APRIL 2000 – REVISED MAY 2001 signal groups description (continued) 32 ED[31:0] Data CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 HOLD HOLDA Asynchronous Memory Control ARE AOE AWE ARDY Memory Map Space Select 20 Word Address SBSRAM Control SSADS SSOE SSWE SSCLK SDRAM Control SDA10 SDRAS SDCAS SDWE SDCLK Byte Enables HOLD/ HOLDA EMIF (External Memory Interface) TOUT1 Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Receive Receive CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Transmit Transmit CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions SIGNAL NAME NO. TYPE† DESCRIPTION CLOCK/PLL CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 CLKMODE0 C17 PLLFREQ3 C13 PLLFREQ2 G11 PLLFREQ1 PLLV‡ F11 D12 PLLG‡ Clock mode select I • Selects whether the output clock frequency = input clock freq x4 or x1 PLL frequency range (3, 2, and 1) I • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. PLL analog VCC connection for the low-pass filter G10 A§ A§ PLLF C12 A§ PLL low-pass filter connection to external components and a bypass capacitor TMS K19 I TDO R12 O/Z TDI R13 I JTAG test port data in (features an internal pull-up) TCK M20 I JTAG test port clock TRST N18 I JTAG test port reset (features an internal pull-down) EMU1 R20 I/O/Z EMU0 T18 I/O/Z RESET J20 I Device reset NMI K21 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 R16 I External interrupts interru ts • Edge-driven g (rising g edge) g O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interrupt interru t service fetch packet acket ordering I If high, selects little-endian byte/half-word addressing order within a word If low, selects big-endian addressing PLL analog GND connection for the low-pass filter JTAG EMULATION JTAG test port mode select (features an internal pull-up) JTAG test port data out Emulation pin 1, pull-up with a dedicated 20-kΩ resistor¶ Emulation pin 0, pull-up with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS EXT_INT6 P20 EXT_INT5 R15 EXT_INT4 R18 IACK R11 INUM3 T19 INUM2 T20 INUM1 T14 INUM0 T16 LITTLE ENDIAN/BIG ENDIAN LENDIAN G20 POWER DOWN STATUS PD D19 O Power-down mode 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect those pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION HOST PORT INTERFACE (HPI) HINT H2 O/Z HCNTL1 J6 I Host control – selects between control, address or data registers HCNTL0 H6 I Host control – selects between control, address or data registers HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order) HBE1 G6 I Host byte select within word or half-word HBE0 F6 I Host byte select within word or half-word HR/W D4 I Host read or write select HD15 D11 HD14 B11 HD13 A11 HD12 G9 HD11 D10 HD10 A10 HD9 C10 HD8 B9 HD7 F9 HD6 C9 HD5 A9 HD4 B8 HD3 D9 HD2 D8 HD1 B7 HD0 C7 I/O/Z Host interrupt (from DSP to host) ( sed for transfer of data, data address and control) Host port data (used HAS L6 I Host address strobe HCS C5 I Host chip select HDS1 C4 I Host data strobe 1 HDS2 K6 I Host data strobe 2 HRDY H3 O Host ready (from DSP to host) BOOTMODE4 B16 BOOTMODE3 G14 BOOT MODE BOOTMODE2 F15 BOOTMODE1 C18 I Boot mode BOOTMODE0 D17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 Y5 O/Z CE2 V3 O/Z Memory space enables CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address CE0 U2 O/Z • Only one asserted during any external data access BE3 R8 O/Z Byte enable control BE2 T3 O/Z • Decoded from the two lowest bits of the internal address BE1 T2 O/Z • Byte write enables for most types of memory BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EA21 L4 EA20 L3 EA19 J2 EMIF – ADDRESS EA18 J1 EA17 K1 EA16 K2 EA15 L2 EA14 L1 EA13 M1 EA12 M2 EA11 M6 EA10 N4 EA9 N1 EA8 N2 EA7 N6 EA6 P4 EA5 P3 EA4 P2 EA3 P1 O/Z E ternal address ((word External ord address) EA2 P6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – DATA ED31 U18 ED30 U20 ED29 T15 ED28 V18 ED27 V17 ED26 V16 ED25 T12 ED24 W17 ED23 T13 ED22 Y17 ED21 T11 ED20 Y16 ED19 W15 ED18 V14 ED17 Y15 ED16 R9 ED15 Y14 ED14 V13 ED13 AA13 ED12 T10 ED11 Y13 ED10 W12 ED9 Y12 ED8 Y11 ED7 V10 ED6 AA10 ED5 Y10 ED4 W10 ED3 Y9 ED2 AA9 ED1 Y8 ED0 W9 I/O/Z E ternal data External EMIF – ASYNCHRONOUS MEMORY CONTROL ARE R7 O/Z Asynchronous memory read enable AOE T7 O/Z Asynchronous memory output enable AWE V5 O/Z Asynchronous memory write enable ARDY R4 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – SYNCHRONOUS BURST SRAM CONTROL SSADS V8 O/Z SBSRAM address strobe SSOE W7 O/Z SBSRAM output enable SSWE Y7 O/Z SBSRAM write enable SSCLK AA8 O/Z SBSRAM clock EMIF – SYNCHRONOUS DRAM CONTROL SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command) SDRAS V6 O/Z SDRAM row address strobe SDCAS W5 O/Z SDRAM column address strobe SDWE T8 O/Z SDRAM write enable SDCLK T9 O/Z SDRAM clock EMIF – BUS ARBITRATION HOLD R6 I Hold request from the host HOLDA B15 O Hold request acknowledge to the host TOUT1 G2 O/Z TINP1 K3 I TOUT0 M18 O/Z TINP0 J18 I DMAC3 E18 DMAC2 F19 DMAC1 E20 DMAC0 G16 TIMERS Timer 1 or general-purpose output Timer 1 or general-purpose input Timer 0 or general-purpose output Timer 0 or general-purpose input DMA ACTION COMPLETE O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 F4 I CLKR1 H4 I/O/Z External clock source (as opposed to internal) Receive clock CLKX1 J4 I/O/Z Transmit clock DR1 E2 I Receive data DX1 G4 O/Z Transmit data FSR1 F3 I/O/Z Receive frame sync FSX1 F2 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K18 I CLKR0 L21 I/O/Z External clock source (as opposed to internal) Receive clock CLKX0 K20 I/O/Z Transmit clock DR0 J21 I Receive data DX0 M21 O/Z Transmit data FSR0 P16 I/O/Z Receive frame sync FSX0 N16 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 N21 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV1 K16 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV2 B13 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV3 B14 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV4 F13 I Reserved for testing, pull-down with a dedicated 20-kΩ resistor RSV5 C15 O Reserved (leave unconnected, do not connect to power or ground) RSV6 F7 I Reserved for testing, pull-up with a dedicated 20-kW resistor RSV7 D7 I Reserved for testing, pull-up with a dedicated 20-kW resistor RSV8 B5 I Reserved for testing, pull-up with a dedicated 20-kW resistor RSV9 F16 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS C14 C8 E19 E3 H11 H13 H9 J10 J12 J14 DVDD J19 S 3.3-V 3.3 V supply su ly voltage J3 J8 K11 K13 K15 K7 K9 L10 L12 L14 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) L8 M11 M13 M15 M7 M9 N10 N12 N14 DVDD N19 S 3.3-V 3.3 V supply su ly voltage S 1 9 V supply 1.9-V s ppl voltage oltage N3 N8 P11 P13 P9 U19 U3 W14 W8 A12 A13 B10 B12 B6 D15 D16 F10 F14 F8 CVDD G13 G7 G8 K4 M3 M4 A3 A5 A7 A16 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) A18 AA4 AA6 AA15 AA17 AA19 B2 B4 B19 C1 C3 C20 D2 D21 E1 E6 E8 CVDD E10 S 1 9 V supply 1.9-V s ppl voltage oltage E12 E14 E16 F5 F17 F21 G1 H5 H17 K5 K17 M5 M17 P5 P17 R21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) T1 T5 T17 U6 U8 U10 U12 U14 U16 U21 V1 V20 W2 W19 W21 Y3 Y18 Y20 CVDD AA11 S 1.9-V 1.9 V supply su ly voltage AA12 F20 G18 H16 H18 L18 L19 L20 N20 P18 P19 R10 R14 U4 V11 V12 V15 W13 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS C11 C16 C6 D5 G3 H10 H12 H14 H7 H8 J11 J13 J7 J9 K8 L7 L9 M8 N7 VSS R3 GND Ground pins ins A4 A6 A8 A15 A17 A19 AA3 AA5 AA7 AA14 AA16 AA18 B3 B18 B20 C2 C19 C21 D1 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) D20 E5 E7 E9 E11 E13 E15 E17 E21 F1 G5 G17 G21 H1 J5 J17 L5 VSS L17 GND Ground pins ins N5 N17 P21 R1 R5 R17 T21 U1 U5 U7 U9 U11 U13 U15 U17 V2 V21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) W1 W3 W20 Y2 Y4 Y19 F18 G19 H15 J15 J16 K10 K12 K14 L11 L13 L15 VSS M10 GND Ground pins ins M12 M14 N11 N13 N15 N9 P10 P12 P14 P15 P7 P8 R19 T4 W11 W16 W6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 SGUS030B – APRIL 2000 – REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION REMAINING UNCONNECTED PINS D13 D14 D18 D3 D6 F12 G12 G15 NC H19 H20 Unconnected pins H21 L16 M16 M19 V19 V4 W18 W4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 development support Texas Instruments (TI) offers an extensive line of development tools for the ’C6x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of ’C6x-based applications: Software-Development Tools: Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware-Development Tools: Extended development system (XDS) emulator (supports ’C6x multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies in the industry. To receive TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 2 for a complete listing of development-support tools for the ’C6x. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 2. SMJ320C6x Development-Support Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Software Ada 95 Compiler† Sun Solaris 2.3‡ AD0345AS8500RF - Single User AD0345BS8500RF - Multi-user C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07 C Compiler/Assembler/Linker/Assembly Optimizer SPARC Solaris TMDX3246555-07 Simulator Win32 TMDS3246851-07 Simulator SPARC Solaris TMDS3246551-07 Win32, Windows NT TMDX324016X-07 XDS510 Debugger/Emulation Software Hardware XDS510 Emulator§ PC XDS510WS Emulator¶ SCSI TMDS00510 TMDS00510WS Software/Hardware EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201 † Contact IRVINE Compiler Corporation (949) 250-1366 to order. ‡ NT support estimated availability 1Q00. § Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included. ¶ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable. XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 SGUS030B – APRIL 2000 – REVISED MAY 2001 device and development-support tool nomenclature To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320 devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical specifications SM Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SMJ Fully qualified production device processed to MIL-PRF-38535 Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product SMX devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLP), the temperature range, and the device speed range in megahertz (for example, 16 is 167 MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 device and development-support tool nomenclature (continued) SMJ 320 C 6701 GLP W 14 PREFIX SMX= Experimental device SMJ = MIL-PRF-38535, QML SM = Commercial processing DEVICE SPEED RANGE 14 = 140 MHz 16 = 167 MHz TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) S = –40°C to 90°C, extended temperature W = –55°C to 115°C, extended temperature DEVICE FAMILY 320 = SMJ320 family TECHNOLOGY C = CMOS PACKAGE TYPE† GLP = 429-pin ceramic BGA DEVICE ’6x DSP: † BGA = 6201B 6203 6701 Ball Grid Array Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701) documentation support Extensive documentation supports all SMJ320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the ’C6000 CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for ’C6x devices and includes application program examples. The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the ’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis. The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 SGUS030B – APRIL 2000 – REVISED MAY 2001 documentation support (continued) TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of devices. The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and APIs to analyze embedded real-time DSP applications. Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer development environment to build and debug embedded real-time DSP applications. Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated development environment and software tools. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the SMJ320 family, including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). clock PLL All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3, Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency = 20-30 MHz, maximum dB attenuation = 45-50 dB, and minimum dB attenuation above 30 MHz = 20 dB. Table 3. CLKOUT1 Frequency Ranges† PLLFREQ3 (C13) PLLFREQ2 (G11) PLLFREQ1 (F11) CLKOUT1 Frequency Range (MHz) 0 0 0 50–140 0 0 1 65–167 0 1 0 130–167 † Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 clock PLL (continued) Table 4. ’C6701 PLL Component Selection Table CLKIN RANGE (MHz) CLKMODE CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 (Ω) C1 (nF) C2 (pF) TYPICAL LOCK TIME (µs)‡ x4 12.5–41.7 50–167 25–83.5 60.4 27 560 75 ‡ Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. PLLFREQ3 PLLFREQ2 PLLFREQ1 3.3V (see Table 3) EMI Filter PLLV C3 10 mF C4 0.1 mF CLKMODE0 CLKMODE1 Internal to ’C6701 PLL PLLMULT PLLCLK CLKIN CLKIN 1 LOOP FILTER CPU Clock Frequency f(CPUCLOCK) CLKMODE1 CLKMODE0 PLL Multiply Factors 0 0 x1(BYPASS) 1 x f(CLKIN) 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 x4 4 x f(CLKIN) C2 C1 CPU CLOCK PLLG Available Multiply Factors PLLF 0 R1 NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the ’C6000 device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 SGUS030B – APRIL 2000 – REVISED MAY 2001 clock PLL (continued) PLLFREQ3 PLLFREQ2 PLLFREQ1 3.3V (see Table 3) PLLV CLKMODE0 CLKMODE1 Internal to ’C6701 PLLMULT PLL PLLCLK CLKIN CLKIN LOOP FILTER 1 CPU CLOCK PLLG PLLF 0 NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Operating case temperature range, TC S suffix device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 90_C W suffix device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 115_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage 1.81 1.9 1.99 V DVDD Supply voltage 3.14 3.30 3.46 V VSS VIH Supply ground 0 0 0 V VIL IOH Low-level input voltage 0.8 V High-level output current –12 mA IOL Low-level output current 12 mA TC Case temperature High-level input voltage 2.0 POST OFFICE BOX 1443 V S suffix device –40 90 W suffix device –55 115 • HOUSTON, TEXAS 77251–1443 _C 27 SGUS030B – APRIL 2000 – REVISED MAY 2001 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VOH VOL II IOZ TEST CONDITIONS High-level output voltage DVDD = MIN, Low-level output voltage Input current† DVDD = MIN, IOH = MAX IOL = MAX MIN TYP UNIT V VI = VSS to DVDD VO = DVDD or 0 V Off-state output current MAX 2.4 0.6 V ±10 uA ±10 uA IDD2V Supply current, CPU + CPU memory access‡ CVDD = NOM, CPU clock = 150 MHz 470 mA IDD2V Supply current, peripherals§ CVDD = NOM, CPU clock = 150 MHz 250 mA IDD3V Supply current, I/O pins¶ DVDD = NOM, CPU clock = 150 MHz 85 mA Ci Input capacitance *15 pF Co Output capacitance *15 pF * This parameter is not tested. † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle § Measured with average peripheral activity: 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs ¶ Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance. signal-transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SGUS030B – APRIL 2000 – REVISED MAY 2001 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN† (see Figure 8) ’C6701-14 CLKMODE = x4 NO. MIN 1 ’C6701-16 CLKMODE = x1 MAX MIN CLKMODE = x4 MAX MIN CLKMODE = x1 MAX MIN UNIT MAX tc(CLKIN) Cycle time, CLKIN 28.4 7.1 24 6 ns 2 tw(CLKINH) Pulse duration, CLKIN high *0.4C‡ *0.45C‡ *0.4C‡ *0.45C‡ ns 3 tw(CLKINL) Pulse duration, CLKIN low *0.4C‡ *0.45C‡ *0.4C‡ *0.45C‡ ns 4 tt(CLKIN) Transition time, CLKIN *5 *0.6 *5 † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. *This parameter is not tested. 1 *0.6 ns 4 2 CLKIN 3 4 Figure 8. CLKIN Timings switching characteristics for CLKOUT1‡§ (see Figure 9) ’C6701-14 ’C6701-16 NO NO. 1 2 3 PARAMETER CLKMODE = x4 MIN MAX MIN MAX *P – 0.7 *P + 0.7 *P – 0.7 *P + 0.7 ns Pulse duration, CLKOUT1 high *(P/2) – 0.5 *(P/2) + 0.5 *PH – 0.5 *PH + 0.5 ns Pulse duration, CLKOUT1 low *(P/2) – 0.5 *(P/2) + 0.5 *PL – 0.5 *PL + 0.5 ns *0.6 ns tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) 4 Transition time, CLKOUT1 ‡ P = 1/CPU clock frequency in nanoseconds (ns). § PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. *This parameter is not tested. *0.6 1 4 2 CLKOUT1 3 4 Figure 9. CLKOUT1 Timings 30 UNIT CLKMODE = x1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT2† (see Figure 10) NO. 1 2 3 4 ’C6701-14 ’C6701-16 PARAMETER UNIT MIN MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 *2P – 0.7 *2P + 0.7 ns Pulse duration, CLKOUT2 high *P – 0.7 *P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low *P – 0.7 *P + 0.7 ns *0.6 ns Transition time, CLKOUT2 † P = 1/CPU clock frequency in ns. *This parameter is not tested. 1 4 2 CLKOUT2 3 4 Figure 10. CLKOUT2 Timings SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 11) NO. 1 ’C6701-14 ’C6701-16 PARAMETER MIN MAX UNIT td(CKO1-SSCLK) td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge –0.8 3.4 ns 2 Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1.0 3.0 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge –1.5 2.5 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge –1.5 1.9 ns CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 SGUS030B – APRIL 2000 – REVISED MAY 2001 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 12 and Figure 13) ’C6701-14 ’C6701-16 NO. MIN 6 7 10 11 UNIT MAX tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high 4.8 ns Hold time, read EDx valid after CLKOUT1 high 1.5 ns tsu(ARDY-CKO1H) th(CKO1H-ARDY) Setup time, ARDY valid before CLKOUT1 high 3.5 ns Hold time, ARDY valid after CLKOUT1 high 1.5 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13) NO. 1 2 3 4 5 8 9 12 13 14 PARAMETER UNIT MIN MAX –1.0 4.5 ns 4.5 ns td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to EAx invalid –1.0 Delay time, CLKOUT1 high to AOE valid –1.0 4.5 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid –1.0 4.5 ns 4.5 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid –1.0 Delay time, CLKOUT1 high to AWE valid –1.0 Delay time, CLKOUT1 high to BEx valid –1.0 Delay time, CLKOUT1 high to EAx valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns 4.5 Delay time, CLKOUT1 high to EDx valid ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. 32 ’C6701-14 ’C6701-16 ns ns ns 4.5 ns SGUS030B – APRIL 2000 – REVISED MAY 2001 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 12. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 13. Asynchronous Memory Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14) NO NO. 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SSCLK high 2.6 2.5 ns Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 14 and Figure 15) NO NO. 1 PARAMETER ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, CEx valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high 0.5P – 1.6 0.5P – 1.6 ns Output hold time, BEx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high 0.5P – 1.7 0.5P – 1.7 ns Output hold time, EAx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.5 ns tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, SSADS valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, SSOE valid after SSCLK high 0.5P – 2.5 0.5P – 2.5 ns tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns 14 Output hold time, EDx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.5 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns 2 3 4 5 6 9 10 11 12 13 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 5 EA[21:2] 8 7 Q1 ED[31:0] 9 Q2 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 14. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 D3 14 D4 5 EA[21:2] 13 ED[31:0] D1 D2 9 10 15 16 SSADS SSOE SSWE Figure 15. SBSRAM Write Timing (Full-Rate SSCLK) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16) NO NO. 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SSCLK high 3.8 3.8 ns Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 16 and Figure 17) NO NO. 1 PARAMETER ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, CEx valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, BEx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, EAx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, SSADS valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, SSOE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 14 Output hold time, EDx invalid after SSCLK high 0.5P – 2.3 0.5P – 2.2 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 2 3 4 5 6 9 10 11 12 13 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 9 Q3 Q4 10 SSADS 11 12 SSOE SDWE Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 ED[31:0] Q1 Q2 Q3 Q4 6 13 14 9 10 15 16 SSADS SSOE SSWE Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 18) NO NO. 7 8 tsu(EDV-SDCLKH) th(SDCLKH-EDV) ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SDCLK high 2 2 ns Hold time, read EDx valid after SDCLK high 3 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 18–Figure 23) NO NO. 1 PARAMETER tosu(CEV-SDCLKH) toh(SDCLKH-CEV) Output setup time, CEx valid before SDCLK high tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) Output setup time, BEx valid before SDCLK high Output setup time, EAx valid before SDCLK high 6 tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) 9 tosu(SDCAS-SDCLKH) 10 11 toh(SDCLKH-SDCAS) tosu(EDV-SDCLKH) 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 2 3 4 5 ’C6701-14 ’C6701-16 MIN MIN MAX MAX UNIT 1.5P – 5 1.5P – 4 ns 0.5P – 1.9 0.5P – 1.5 ns 1.5P – 5 1.5P – 4 ns 0.5P – 1.9 0.5P – 1.5 ns 1.5P – 5 1.5P – 4 ns Output hold time, EAx invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, SDCAS valid before SDCLK high 1.5P – 5 1.5P – 4 ns Output hold time, SDCAS valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, EDx valid before SDCLK high 1.5P – 5 1.5P – 4 ns 0.5P – 1.9 0.5P – 1.5 ns 1.5P – 5 1.5P – 4 ns 0.5P – 1.9 0.5P – 1.5 ns 1.5P – 5 1.5P – 4 ns 0.5P – 1.9 0.5P – 1.5 ns 1.5P – 5 1.5P – 4 ns Output hold time, CEx valid after SDCLK high Output hold time, BEx invalid after SDCLK high 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS SDCAS SDWE Figure 18. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK 1 2 CEx 3 4 BE1 BE[3:0] 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS SDCAS SDWE Figure 19. Three SDRAM Write Commands POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS SDCAS SDWE Figure 20. SDRAM ACTV Command DCAB SDCLK 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS 13 SDWE Figure 21. SDRAM DCAB Command 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 14 SGUS030B – APRIL 2000 – REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS SDWE Figure 22. SDRAM REFR Command MRS SDCLK 1 2 5 6 CEx BE[3:0] MRS Value EA[15:2] ED[31:0] SDA10 17 18 9 10 13 14 SDRAS SDCAS SDWE Figure 23. SDRAM MRS Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 SGUS030B – APRIL 2000 – REVISED MAY 2001 HOLD/HOLDA TIMING timing requirements for the hold/hold acknowledge cycles† (see Figure 24) ’C6701-14 ’C6701-16 NO. MIN 1 2 tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) Setup time, HOLD high before CLKOUT1 high 5 Hold time, HOLD low after CLKOUT1 high 2 UNIT MAX ns ns † HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. switching characteristics for the hold/hold acknowledge cycles‡ (see Figure 24) NO. ’C6701-14 ’C6701-16 PARAMETER MIN 3 4 5 6 7 8 tR(HOLDL-EMHZ) tR(EMHZ-HOLDAL) Response time, HOLD low to EMIF high impedance tR(HOLDH-HOLDAH) td(CKO1H-HOLDAL) Response time, HOLD high to HOLDA high td(CKO1H-BHZ) td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus high impedance¶ Delay time, CLKOUT1 high to EMIF Bus low impedance¶ UNIT MAX § ns 2P ns 7P ns 1 8 ns *1 *8 ns 4P Response time, EMIF high impedance to HOLDA low 4P Delay time, CLKOUT1 high to HOLDA valid *1 *12 ns tR(HOLDH-BLZ) Response time, HOLD high to EMIF Bus low impedance¶ 3P 6P ns ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. *This parameter is not tested. 9 DSP Owns Bus External Requester DSP Owns Bus 5 9 4 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus† ’C6701 Ext Req ’C6701 † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 24. HOLD/HOLDA Timing 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 RESET TIMING timing requirements for reset (see Figure 25) ’C6701-14 ’C6701-16 NO. MIN 1 tw(RESET) Width of the RESET pulse (PLL stable)† UNIT MAX CLKOUT1 cycles *10 *250 µs † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. *This parameter is not tested. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. Width of the RESET pulse (PLL needs to sync up)‡ switching characteristics during reset§ (see Figure 25) NO. ’C6701-14 ’C6701-16 PARAMETER MIN 2 tR(RESET) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK invalid td(CKO1H-SSCKIV) td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK invalid td(CKO1H-LOWIV) td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group invalid td(CKO1H-HIGHIV) td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group invalid td(CKO1H-ZHZ) td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group high impedance 4 5 6 7 8 9 10 11 12 13 14 § Low group consists of: High group consists of: Z group consists of: *–1 ns *10 *–1 Delay time, CLKOUT1 high to SDCLK valid *10 *10 ns ns *10 *–1 Delay time, CLKOUT1 high to high group valid ns ns *–1 Delay time, CLKOUT1 high to low group valid ns ns *–1 Delay time, CLKOUT1 high to SSCLK valid Delay time, CLKOUT1 high to Z group valid CLKOUT1 cycles *1 Delay time, CLKOUT1 high to CLKOUT2 valid UNIT MAX ns ns *10 *–1 ns ns *10 ns IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HRDY and HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. *This parameter is not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 SGUS030B – APRIL 2000 – REVISED MAY 2001 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 CLKOUT2 SDCLK SSCLK LOW GROUP† HIGH GROUP† Z GROUP† † Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HRDY and HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. Figure 25. Reset Timing 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 EXTERNAL INTERRUPT/RESET TIMING timing requirements for interrupt response cycles†‡ (see Figure 26) ’C6701-14 ’C6701-16 NO. MIN 2 3 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low *2P Width of the interrupt pulse high *2P UNIT MAX ns ns † Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. *This parameter is not tested. switching characteristics during interrupt response cycles§ (see Figure 26) NO. ’C6701-14 ’C6701-16 PARAMETER MIN 1 Response time, EXT_INTx high to IACK high 4 tR(EINTH-IACKH) td(CKO2L-IACKV) 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid UNIT MAX 9P Delay time, CLKOUT2 low to IACK valid –0.5P 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. ns 13 – 0.5P ns 10 – 0.5P ns –0.5P ns 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 26. Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 SGUS030B – APRIL 2000 – REVISED MAY 2001 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) ’C6701-14 ’C6701-16 NO. MIN 1 2 3 4 10 11 12 tsu(SEL-HSTBL) th(HSTBL-SEL) Setup time, select signals§ valid before HSTROBE low Hold time, select signals§ valid after HSTROBE low tw(HSTBL) tw(HSTBH) tsu(SEL-HASL) th(HASL-SEL) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) 19 UNIT MAX 4 ns 2 ns Pulse duration, HSTROBE low *2P ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals§ valid before HAS low *2P ns 4 ns Hold time, select signals§ valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 3 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. *1 ns Setup time, HAS low before HSTROBE low *2 ns Hold time, HAS low after HSTROBE low *2 ns *This parameter is not tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. PARAMETER ’C6701-14 ’C6701-16 MIN 5 6 7 8 9 15 16 17 td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HCS to HRDY¶ toh(HSTBL-HDLZ) td(HDV-HRDYL) Output hold time, HD low impedance after HSTROBE low for an HPI read toh(HSTBH-HDV) td(HSTBH-HDHZ) Output hold time, HD valid after HSTROBE high td(HSTBL-HDV) td(HSTBH-HRDYH) Delay time, HSTROBE low to HRDY high# Delay time, HD valid to HRDY low UNIT MAX 1 12 ns 1 12 ns *4 ns *P – 3 *P + 3 ns 3 12 ns *3 *12 ns Delay time, HSTROBE low to HD valid 3 12 ns Delay time, HSTROBE high to HRDY high|| 1 12 ns Delay time, HSTROBE high to HD high impedance *This parameter is not tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† HCS 15 9 7 15 9 16 HD[15:0] (output) 1st half-word 5 2nd half-word 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 27. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE† 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 6 8 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 28. HPI Read Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 SGUS030B – APRIL 2000 – REVISED MAY 2001 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 4 14 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st half-word 5 17 2nd half-word 5 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE† 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HAS Used) 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 31) ’C6701-14 ’C6701-16 NO. MIN 2 3 tc(CKRX) tw(CKRX) UNIT MAX Cycle time, CLKR/X CLKR/X ext *2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext *P – 1 ns 5 tsu(FRH-CKRL) Set p time, Setup time external e ternal FSR high before CLKR low lo 6 th(CKRL-FRH) Hold time, time external e ternal FSR high after CLKR low lo 7 tsu(DRV-CKRL) Set p time Setup time, DR valid alid before CLKR lo low 8 th(CKRL-DRV) time DR valid after CLKR low Hold time, 10 tsu(FXH-CKXL) Set p time, Setup time external e ternal FSX high before CLKX low lo 11 th(CKXL-FXH) Hold time, time external e ternal FSX high after CLKX low lo CLKR int *13 CLKR ext 4 CLKR int *7 CLKR ext 4 CLKR int 10 CLKR ext 1 CLKR int 4 CLKR ext 4 CLKX int *13 CLKX ext 4 CLKX int *7 CLKX ext 3 ns ns ns ns ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. *This parameter is not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡§ (see Figure 31) NO. ’C6701-14 ’C6701-16 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 3 15 1 td(CKSH-CKRXH) 2 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X int 2P 3 Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶ C + 1¶ ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –4 4 ns CLKX int –4 5 CLKX ext *3 *16 CLKX int *–3 *2 CLKX ext *2 *9 CLKX int –2 4 CLKX ext 3 16 9 td(CKXH-FXV) Dela time, Delay time CLKX high to internal FSX valid alid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance im edance following last data bit from CLKX high 13 td(CKXH-DXV) time CLKX high to DX valid. valid Delay time, 14 td(FXH-DXV) Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode. ns ns FSX int *–2 *4 FSX ext *2 *10 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero *This parameter is not tested. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 31. McBSP Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 32) ’C6701-14 ’C6701-16 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high *4 ns Hold time, FSR high after CLKS high *4 ns *This parameter is not tested. CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X(needs resync) Figure 32. FSR Timing When GSYNC = 1 52 UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) ’C6701-14 ’C6701-16 NO NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 MIN MAX 2 – 3P ns 5 Hold time, DR valid after CLKX low 4 5 + 6P ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) ’C6701-14 ’C6701-16 NO NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T–4 T+4 L–4 L+4 –4 4 *L – 2 *L + 3 MIN MAX ns ns 3P + 1 5P + 17 ns ns *P + 4 *3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 34) ’C6701-14 ’C6701-16 NO NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MIN 12 2 – 3P 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. 54 Hold time, DR valid after CLKX high MAX UNIT SLAVE POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 34) ’C6701-14 ’C6701-16 NO NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 1 6 UNIT SLAVE MIN MAX L–4 L+4 MIN MAX ns T–4 T+4 ns –4 4 3P + 1 5P + 17 ns *–2 *4 *3P + 4 *5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid *H – 2 *H + 3 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) ’C6701-14 ’C6701-16 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 MIN MAX 2 – 3P ns 5 Hold time, DR valid after CLKX high 4 5 + 6P ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) ’C6701-14 ’C6701-16 NO NO. PARAMETER MASTER§ MIN 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 MAX T–4 T+4 H–4 H+4 –4 4 *H – 2 *H + 3 8 UNIT SLAVE MIN MAX ns ns 3P + 1 5P + 17 ns ns *P + 4 *3P + 17 ns td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) ’C6701-14 ’C6701-16 NO NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low MAX UNIT SLAVE MIN 12 2 – 3P 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 SGUS030B – APRIL 2000 – REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) ’C6701-14 ’C6701-16 NO NO. PARAMETER MASTER§ 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 1 6 UNIT SLAVE MIN MAX H–4 H+4 MIN MAX ns T–4 T+4 ns –4 4 3P + 1 5P + 17 ns *–2 *4 *3P + 4 *5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid *L – 2 *L + 3 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS030B – APRIL 2000 – REVISED MAY 2001 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 37) NO. 1 ’C6701-14 ’C6701-16 PARAMETER td(CKO1H-DMACV) UNIT MIN MAX 2 11 Delay time, CLKOUT1 high to DMAC valid ns CLKOUT1 1 1 DMAC[0:3] Figure 37. DMAC Timing timing requirements for timer inputs (see Figure 38)† ’C6701-14 ’C6701-16 NO. MIN 1 tw(TINPH) Pulse duration, TINP high † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. UNIT MAX 2P ns switching characteristics for timer outputs (see Figure 38) NO. 2 ’C6701-14 ’C6701-16 PARAMETER td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid UNIT MIN MAX 1 10 ns CLKOUT1 1 TINP 2 2 TOUT Figure 38. Timer Timing switching characteristics for power-down outputs (see Figure 39) NO. 1 ’C6701-14 ’C6701-16 PARAMETER td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid UNIT MIN MAX 1 9 ns CLKOUT1 1 1 PD Figure 39. Power-Down Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 SGUS030B – APRIL 2000 – REVISED MAY 2001 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 40) ’C6701-14 ’C6701-16 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics for JTAG test port (see Figure 40) NO. ’C6701-14 ’C6701-16 PARAMETER 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid *This parameter is not tested. MIN MAX *–3 *15 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 40. JTAG Test-Port Timing 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT ns SGUS030B – APRIL 2000 – REVISED MAY 2001 MECHANICAL DATA GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY 27,20 SQ 26,80 25,40 TYP 1,27 AA Y W V U T R P N M L K J H G F E D C B A 1,27 1 3 2 1,22 1,00 5 4 9 7 6 8 10 11 13 15 17 19 21 12 14 16 18 20 3,30 MAX Seating Plane 0,90 0,60 NOTES: A. B. C. D. ∅ 0,10 M 0,70 0,50 0,15 4164732/A 08/98 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-156 Flip chip application only thermal resistance characteristics (S-CBGA package) °C/W Air Flow 3.0 N/A Junction-to-Case, measured to the top of the package lid 7.3 N/A Junction-to-Ambient 14.5 0 11.8 150 fpm 11.1 250 fpm 10.2 500 fpm 6.2 N/A NO 1 Junction-to-Case, measured to the bottom of solder ball 2 RΘJC RΘJC 3 RΘJA RΘJMA Junction-to-Moving-Air Junction to Moving Air 4 5 6 7 RΘJB Junction-to-Board, measured by soldering a thermocouple to one of the middle traces on the board at the edge of the package POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9866101QXA ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC 5962-9866101VXA ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) 5962-9866102VXA ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC SM320C6701GLPS16 ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC SM320C6701GLPW14 ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC SMJ320C6701GLPW14 ACTIVE FC/CSP GLP 429 1 None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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