TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 D D D D D D D DW OR PW PACKAGE (TOP VIEW) 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time vs Power Consumption 1 µs in Fast Mode 3.5 µs in Slow Mode 8-Bit µController Compatible Interface Differential Nonlinearity . . . <0.5 LSB Typ Voltage Output Range . . . 2x the Reference Voltage Monotonic Over Temperature D2 D3 D4 D5 D6 D7 A1 A0 SPD DVDD 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 D1 D0 CS WE LDAC PWR AGND OUT REF AVDD applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices description The TLV5633 is a 12-bit voltage output digital-to-analog converter (DAC) with an 8-bit microcontroller compatible parallel interface. The 8 LSBs, the 4 MSBs, and 5 control bits are written using three different addresses. Developed for a wide range of supply voltages, the TLV5633 can be operated from 2.7 V to 5.5 V. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class A (slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5633 simplifies overall system design. Because of its ability to source up to 1 mA, the internal reference can also be used as a system reference. The settling time and the reference voltage can be chosen by a control register. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC (DW) TSSOP (PW) 0°C to 70°C TLV5633CDW TLV5633CPW – 40°C to 85°C TLV5633IDW TLV5633IPW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 functional block diagram REF AGND DVDD AVDD PGA With Output Enable Voltage Bandgap SPD PWR Powerdown and Speed Control Power-On Reset 5 2 A(0,1) Interface Control CS WE x2 2 5-Bit Control Latch 4 4-Bit DAC MSW Holding Latch 4 8 8-Bit DAC LSW Holding Latch 8 12 12-Bit DAC Register 12 D(0–7) LDAC Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION A1, A0 7, 8 I Address input AGND 14 P Ground AVDD CS 11 P Positive power supply (analog part) 18 I Chip select. Digital input active low, used to enable/disable inputs D0 – D1 19, 20 I Data input D2 – D7 1–6 I Data input DVDD 10 P Positive power supply (digital part) LDAC 16 I Load DAC. Digital input active low, used to load DAC output OUT 13 O DAC analog voltage output PWR 15 I Power down. Digital input active low REF 12 I/O SPD 9 I Speed select. Digital input WE 17 I Write enable. Digital input active low, used to latch data 2 Analog reference voltage input/output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OUT TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (DVDD, AVDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage difference range, AVDD – DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2.8 V to 2.8 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5633C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5633I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage voltage, DVDD, AVDD MIN NOM MAX 5-V operation 4.5 5 5.5 V 3-V operation 2.7 3 3.3 V 0 0 0 V 2 V Supply voltage difference, ∆VDD = AVDD – DVDD Power on reset voltage, POR 0.55 High-level digital input voltage, VIH 2 Low-level digital input voltage, VIL DVDD 0 Reference voltage, Vref to REF terminal (5-V supply), See Note 1 AGND 2.048 Reference voltage, Vref to REF terminal (3-V supply), See Note 1 AGND 1.024 Load resistance, RL Operating free-air free air temperature, temperature TA V 0.8 V AVDD –1.5 AVDD – 1.5 V 2 Load capacitance, CL TLV5633I V kΩ 100 TLV5633C UNIT 0 70 – 40 85 pF °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ AVDD/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN REF on AVDD = 5 V,, DVDD = 5 V IDD Power supply current No load, All inputs = AGND or DVDD, DAC latch = 0x800 REF off REF on AVDD = 3 V,, DVDD = 3 V REF off TYP MAX Fast 2.3 2.8 mA Slow 1.3 1.6 mA Fast 1.9 2.4 mA Slow 0.9 1.2 mA Fast 2.1 2.6 mA Slow 1.2 1.5 mA Fast 1.8 2.3 mA 0.9 1.1 mA 0.01 1 µA Slow Power down supply current PSRR Power supply rejection ratio Zero scale, external reference, See Note 2 –60 Full scale, external reference, See Note 3 –60 UNIT dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by: PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax] 3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN TYP Resolution MAX 12 UNIT bits INL Integral nonlinearity, end point adjusted RL = 10 kΩ, CL = 100 pF, See Note 4 ± 1.2 ±3 LSB DNL Differential nonlinearity RL = 10 kΩ, CL = 100 pF, See Note 5 ± 0.3 ± 0.5 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 ± 12 20 mV ppm/°C ± 0.3 % full scale V EG TC Gain error temperature coefficient See Note 9 20 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text). 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/2Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO TEST CONDITIONS Output voltage RL = 10 kΩ Output load regulation accuracy 4 TYP MAX AVDD–0.4 VO = 4.096 V, 2.048 V, POST OFFICE BOX 655303 MIN RL = 2 kΩ • DALLAS, TEXAS 75265 ± 0.29 UNIT V % full scale V TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (Continued) reference pin configured as output (REF) PARAMETER Vref(OUTL) Vref(OUTH) Low reference voltage Iref(source) Iref(sink) Output source current PSRR Power supply rejection ratio TEST CONDITIONS High reference voltage AVDD = DVDD > 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 1 Output sink current –1 V mA mA –48 dB reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 Input resistance Reference input bandwidth REF = 0.2 0 2 Vpp + 1.024 1 024 V dc 10 kHz H i di t ti f Harmonic distortion, reference in ut input REF = 1 Vpp + 2.048 V dc, AVDD = 5 V 50 kHz 100 kHz Reference feedthrough V MΩ 5 pF 900 Slow 500 Fast –87 Slow –77 Fast –74 Slow –61 Fast UNIT 10 Fast REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) MAX AVDD–1.5 kHz dB dB –66 dB – 80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current CI Input capacitance TEST CONDITIONS VI = DVDD VI = 0 V Low-level digital input current MIN TYP 1 • DALLAS, TEXAS 75265 UNIT µA µA –1 8 POST OFFICE BOX 655303 MAX pF 5 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 operating characteristics over recommended operating free-air temperature range, Vref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, See Note 11 CL = 100 pF,, ts(CC) (CC) time code to code Output settling time, RL = 10 kΩ,, See Note 12 CL = 100 pF,, SR Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy DIN = 0 to 1, CS = VDD fCLK = 100 kHz, MIN TYP MAX Fast 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 6 10 Slow 1.2 1.7 Signal-to-noise ratio 73 78 SINAD Signal-to-noise + distortion 61 67 THD Total harmonic distortion SFDR Spurious free dynamic range fs = 480 kSPS,, fB = 20 kHz,, fout = 1 kHz,, RL = 10 kΩ,, CL = 100 pF –69 63 µs µs V/µs 5 SNR UNIT nV–S –62 dB 74 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF or 0xFDF to 0x020 respectively. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS–WE) tsu(D) Setup time, CS low before negative WE edge 15 ns Setup time, data ready before positive WE edge 10 ns tsu(A) th(DA) Setup time, addresses ready before positive WE edge 20 ns Hold time, data and addresses held valid after positive WE edge 5 ns tsu(WE-LD) twH(WE) Setup time, positive WE edge before LDAC low 5 ns Pulse duration, WE high 20 ns tw(LD) Pulse duration, LDAC low 23 ns 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 PARAMETER MEASUREMENT INFORMATION D(0–7) X A(0,1) X Data X Address X tsu(D) tsu(A) CS th(DA) twH(WE) tsu(CS-WE) WE tw(LD) tsu(WE-LD) LDAC Figure 1. Timing Diagram D(0–7) X MSW A(0,1) X 0 X X LSW X 1 X CS WE LDAC Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 PARAMETER MEASUREMENT INFORMATION D(0–7) X MSW A(0,1) X 0 X X LSW 1 X Control X 3 X X CS WE LDAC Figure 3. Example of a Complete Write Cycle (MSW, LSW, Control) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY ERROR 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 512 1024 1536 2048 2560 3072 3584 4096 3584 4096 Digital Code Figure 4 INL – Intergral Nonlinearity – LSB INTEGRAL NONLINEARITY ERROR 3 2 1 0 –1 –2 –3 0 512 1024 1536 2048 2560 3072 Digital Code Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 TYPICAL CHARACTERISTICS MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT 4.08 2.04 AVDD = 3 V, Vref = Int. 1 V, Input Code = 0xFFF 2.0395 4.079 VO – Output Voltage – V 2.039 VO – Output Voltage – V AVDD = 5 V, Vref = Int. 2 V, Input Code = 0xFFF 4.0795 Fast Mode, Source 4.0785 Fast Mode, Source 2.0385 2.038 4.078 4.0775 2.0375 2.037 Slow Mode, Source 4.077 Slow Mode, Source 2.0365 4.0765 2.036 4.076 4.0755 2.0355 0 0.5 1 1.5 2 2.5 3 3.5 4 0 4.5 0.5 1 Load Current – mA Figure 6 4.5 0.25 Fast Mode, Sink Fast Mode, Sink 0.2 VO – Output Voltage – V 0.2 VO – Output Voltage – V 4 MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT 0.25 0.15 0.1 Slow Mode, Sink 0.15 0.1 Slow Mode, Sink 0.05 0.05 AVDD = 3 V, Vref = Int. 1 V, Input Code = 0x000 AVDD = 5 V, Vref = Int. 2 V, Input Code = 0x000 0 0 0.5 1 1.5 2 2.5 3 Load Current – mA 3.5 4 4.5 0 0.5 Figure 8 10 3.5 Figure 7 MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT 0 1.5 2 2.5 3 Load Current – mA 1 1.5 2 2.5 3 Load Current – mA Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3.5 4 4.5 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD+N – Total Harmonic Distortion and Noise – dB –10 AVDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 –80 Fast Mode –90 –100 100 10000 1000 100000 0 –10 AVDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 –80 Fast Mode –90 –100 100 10000 1000 f – Frequency – Hz f – Frequency – Hz Figure 10 Figure 11 100000 POWER DOWN SUPPLY CURRENT vs TIME 1 0.9 0.8 I DD – Supply Current – mA THD – Total Harmonic Distortion – dB 0 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 t – Time – µs 70 80 90 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION general function The TLV5633 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE 0 1000 [V] Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). parallel interface The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register depends on the address bits A1 and A0. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving LDAC low. Two more asynchronous inputs, SPD and PWR control the settling times and the power-down mode: SPD: PWR: Speed control Power control 1 → fast mode 1 → normal operation 0 → slow mode 0 → power down It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the control register. The following tables list the possible combinations of control signals and control bits. 12 PIN BIT SPD SPD 0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast MODE PIN BIT PWR PWD 0 0 0 1 Down 1 0 Normal 1 1 Down PIN BIT LDAC RLDAC 0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent POST OFFICE BOX 655303 POWER Down LATCH • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION data format The TLV5633 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0. ADDRESS BITS A1 A0 REGISTER 0 0 DAC LSW holding 0 1 DAC MSW holding 1 0 Reserved 1 1 Control The following table lists the meaning of the bits within the control register. D7 D6 D5 D4 D3 D2 D1 D0 X X† X X† X X† REF1 0† REF0 0† RLDAC 0† PWR 0† SPD 0† † Default values X: don’t care SPD: Speed control bit PWR: Power control bit RLDAC: Load DAC latch 1 → fast mode 1 → power down 1 → latch transparent 0 → slow mode 0 → normal operation 0 → DAC latch controlled by LDAC pin REF1 and REF0 determine the reference source and the reference voltage. REFERENCE BITS REF1 REF0 REFERENCE 0 0 External 0 1 2.048 V 1 0 1.024 V 1 1 External If an external reference voltage is applied to the REF pin, external reference must be selected. layout considerations To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD. Figure 13 shows how to lay out the power planes for the TLV5633. As a general rule, digital and analog signals should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in parallel. The two positive power planes ( AVDD and DVDD) should be connected together at one point with a ferrite bead. A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-µF tantalum capacitor between AVDD and GND placed as close as possible to the supply pins are recommended for optimal performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION layout considerations (continued) DVDD AVDD Figure 13. TLV5633 Board Layout linearity, offset, and gain error using single end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (Single Supply) 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage. TLV5633 interfaced to an Intel MCS51 controller The circuit in Figure 15 shows how to interface the TLV5633 to an Intel MCS51 microcontroller. The address bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which is connected to a latch at port 0. An address decoder is required to generate the chip select signal for the TLV5633. In this example, a simple 3-to-8 decoder (74AC138) is used for the interface as shown in Figure 15. The DAC is memory mapped at addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations (0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to generate the chip select signals for the entire system. The data pins and the WE pin of the TLV5633 can be connected directly to the multiplexed address and data bus and the WR signal of the controller. The application uses the TLV5633 device’s internal reference at 2.048 V. The LDAC pin is connected to P3.5 and is used to update the DAC after both data bytes have been written. 8xC51 8 P2 A(15–8) 16 8 8 P0 AD(7–0) AD(7–0) 74AC138 74AC373 8 D(7–0) Q(7–0) A2 A3 A4 A 8 Y(7–0) CS(7–0) B C DVDD TLV5633 ALE LE A(15–0) OE A15 DVDD G1 G2A G2B 2 G2A SPD A(1–0) D(7–0) PWR CS OUT WE WR P3.5 RL LDAC To Other Devices Requiring Voltage Reference REF Figure 15. TLV5633 Interfaced to an Intel MCS51 Controller MCS is a registered trademark of Intel Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION software In the following example, the code generates a waveform at 20 KSPS with 32 samples stored in a table within the program memory space of the microcontroller. The waveform data is located in the program memory space at segment SINTBL beginning with the MSW of the first 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (the table is not shown in the code example). The program consists of two parts: D D A main routine, which is executed after reset and which initializes the timer and the interrupt system of the microcontroller. An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC. ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; File: WAVE.A51 ; Function: wave generation with TLV5633 ; Processors: 80C51 family (running at 12MHz) ; Software: ASM51 assembler, Keil BL51 code–banking linker ; (C) 1999 Texas Instruments ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Program function declaration ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– NAME WAVE MAIN ISR WAVTBL VAR1 STACK SEGMENT SEGMENT SEGMENT SEGMENT SEGMENT CODE CODE CODE DATA IDATA ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code start at address 0, jump to start ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– CSEG AT 0 LJMP start ; Execution starts at address 0 on power–up. ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code in the timer0 interrupt vector ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Define program variables ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– RSEG VAR1 rolling_ptr: DS 1 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Interrupt service routine for timer 0 interrupts ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– RSEG ISR timer0isr: PUSH PSW PUSH ACC ; ; ; ; ; The signal to be output on the dac is stored in a table as 32 samples of msb, lsb pairs (64 bytes). The pointer, rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on each interrupt (at the end of this routine). MOV DPTR, #wavetable ; set DPTR to the start of the table MOV MOV MOVC MOVX R0, #001H A,rolling_ptr A,@A+DPTR @R0, A ; ; ; ; R0 selects DAC MSW ACC loaded with the pointer into the wave table get msb from the table write DAC MSW MOV MOV INC MOVC MOVX R0, #000H A,rolling_ptr A A,@A+DPTR @R0, A ; ; ; ; ; R0 selects DAC LSW move rolling pointer back in to ACC increment ACC holding the rolling pointer which is the lsb of this sample, now in ACC write DAC LSW MOV INC INC ANL MOV A,rolling_ptr A A A,#003FH rolling_ptr,A ; load ACC with rolling pointer again ; increment the ACC twice, to get next sample CLR SETB T1 T1 ; set LDACB = 0 (update DAC) ; set LDACB = 1 POP POP ACC PSW ; wrap back round to 0 if >64 ; move value held in ACC back to the rolling pointer RETI ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Set up stack ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– RSEG STACK DS 10h ; 16 Byte Stack! ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Main Program ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– RSEG MAIN start: MOV SP,#STACK–1 ; first set Stack Pointer CLR MOV MOV MOV A rolling_ptr,A ; set rolling pointer to 0 TMOD,#002H ; set timer 0 to mode 2 – auto–reload TH0,#0CEH ; set timer 2 re–load value for 20 kHz interrupts MOV P2, #080H ; set A15 of address bus high to ’memory map’ ; device up beyond used address space POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION SETB T1 MOV MOV R0, #003H A, #011H MOVX @R0, A ; ; ; ; ; ; ; ; ; SETB SETB SETB ET0 EA TR0 ; enable timer 0 interrupts ; enable all interrupts ; start timer 0 always: SJMP RET ; set LDACB = 1 (on P3.5) TLV5633 setup R0 selects control register LOAD ACC with control register value: REF1=1, REF0=0 –> 2.048V internal reference RLDAC=0 –> use LDACB pin to control DAC PD=0 –> DAC enabled SPD=1 –> FAST mode write control word: write DAC control word always ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Table of 32 wave samples used as DAC data ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– RSEG WAVTBL wavetable: ;...insert 32 samples here... .END 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (SINAD) Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) DIM 4040000 / D 02/98 NOTES: A. B. C. D. 20 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190 – MARCH 1999 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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