74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
DB, DW, OR NT PACKAGE
(TOP VIEW)
Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OE
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs are set to the logic levels set up at the D inputs.
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC11374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
L
H
X
Q0
L
↓
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
EN
C1
1
1D
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
2
24
13
23
C1
1D
1
22
C1
1D
2
21
C1
1D
3
20
C1
1D
4
17
C1
1D
9
16
C1
1D
10
15
C1
1D
11
14
C1
1D
12
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1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
Low-level input voltage
MIN
NOM
MAX
3
5
5.5
3.85
0.9
1.35
0
0
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 3 V
VCC = 4.5 V
POST OFFICE BOX 655303
VCC
VCC
V
V
–4
–24
VCC = 5.5 V
VCC = 3 V
–24
VCC = 4.5 V
VCC = 5.5 V
Data
24
0
10
OE
0
5
–40
85
• DALLAS, TEXAS 75265
V
1.65
Output voltage
Dt/Dv
V
3.15
Input voltage
Low-level output current
V
2.1
VCC = 4.5 V
VCC = 5.5 V
High-level output current
UNIT
mA
12
mA
24
ns/V
°C
3
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 mA
VOH
IOH = –4 mA
IOH = –24
24 mA
IOH = –75 mA{
IOL = 12 mA
IOL = 24 mA
IOL = 75 mA{
IOZ
II
VO = VCC or GND
VI = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
MIN
TA = 25°C
TYP
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
4.5 V
3.94
3.8
5.5 V
4.94
4.8
5.5 V
IOL = 50 mA
VOL
VCC
UNIT
V
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
IO = 0
MAX
V
1.65
5.5 V
±0.5
±5
mA
5.5 V
±0.1
±1
mA
8
80
mA
5.5 V
5V
4
pF
Co
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
Clock frequency
tsu
th
0
Pulse duration
CLK low or high
75
MIN
MAX
UNIT
0
75
MHz
6.5
6.5
ns
Setup time, data before CLK↑
2.5
2.5
ns
Hold time, data after CLK↑
4.5
4.5
ns
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
4
fclock
tw
Clock frequency
tsu
th
0
Pulse duration
CLK low or high
95
MIN
MAX
UNIT
0
95
MHz
5
5
ns
Setup time, data before CLK↑
2.5
2.5
ns
Hold time, data after CLK↑
3.5
3.5
ns
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74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
Any Q
OE
Any Q
OE
Any Q
MIN
TA = 25°C
TYP
MAX
MIN
MAX
75
90
1.5
9.5
12.5
1.5
75
14.2
1.5
9
12.6
1.5
14
1.5
8
10.9
1.5
12.3
1.5
8
11.1
1.5
12.3
1.5
10
12.1
1.5
12.5
1.5
8
10.7
1.5
11.6
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
Any Q
OE
Any Q
OE
Any Q
TA = 25°C
MIN
TYP
MAX
MIN
MAX
95
110
95
1.5
6.5
9
1.5
10.2
1.5
5.5
9.1
1.5
10.1
1.5
5.5
8
1.5
9.1
1.5
5.5
8.4
1.5
9.4
1.5
9
11
1.5
11.2
1.5
6
8.6
1.5
9.2
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
flip flop
Power dissipation capacitance per flip-flop
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL = 50 pF
f =1 MHz
TYP
75
66
UNIT
pF
5
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
Timing Input
0V
tw
50%
50%
th
tsu
VCC
Input
VCC
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VCC
Input
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
Output
Control
(low-level
enabling)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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