PDM41256 256K Static RAM 32K x 8-Bit Features Description ■ High-speed access times Com’l: 7, 8, 10, 12, and 15 ns Ind’l: 8, 10, 12, and 15 ns The PDM41256 is a high-performance CMOS static RAM organized as 32,768 x 8 bits. This product is produced in Paradigm’s proprietary CMOS technology which offers the designer the highest speed parts. Writing to this device is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. ■ Low power operation (typical) - PDM41256SA Active: 400 mW Standby: 150 mW - PDM41256LA Active: 350 mW Standby: 25 mW ■ Single +5V (±10%) power supply ■ TTL-compatible inputs and outputs ■ Packages Plastic SOJ (300 mil) - TSO Plastic TSOP - T The PDM41256 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41256 comes in two versions, the standard power version PDM41256SA and a low power version the PDM41256LA. The two versions are functionally the same and only differ in their power consumption. The PDM41256 is available in a 28-pin plastic TSOP and a 28-pin 300-mil plastic SOJ. Functional Block Diagram 1 2 3 4 5 6 7 8 9 10 11 12 Rev. 2.0 - 7/17/96 3-33 PDM41256 SOJ Pin Configurations Pin Description TSOP Name Description A14-A0 Address Inputs I/O7-I/O0 Data Inputs/Outputs OE Output Enable Input WE Write Enable Input CE Chip Enable Input VCC Power (+5V) VSS Ground Truth Table OE WE CE I/O MODE X X H Hi-Z Standby L H L DOUT Read X L L DIN Write H H L Hi-Z Output Disable NOTE: 1. H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol Rating Com’l. Ind. Unit VTERM Terminal Voltage with Respect to Vss –0.5 to +7.0 –0.5 to +7.0 V TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions 3-34 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V VSS Supply Voltage 0 0 0 V Commercial Ambient Temperature 0 25 70 °C Industrial Ambient Temperature –40 25 85 °C Rev. 2.0 - 7/17/96 PDM41256 DC Electrical Characteristics (VCC = 5.0V ± 10%) PSM41256SA PSM41256LA Min. Max. Min. Max. Unit Symbol Parameter Test Conditions ILI Input Leakage Current VCC = MAX., VIN = Vss to VCC Com’l/ Ind. –5 5 –5 5 µA ILO Output Leakage Current VCC= MAX., CE = VIH, VOUT = Vss to VCC Com’l/ Ind. –5 5 –5 5 µA VIL Input Low Voltage –0.5(1) 0.8 –0.5(1) 0.8 V VIH Input High Voltage 2.2 6.0 2.2 6.0 V VOL Output Low Voltage IOL=8 mA, VCC = Min. IOL = 10 mA, VCC = Min. — — 0.4 0.5 — — 0.4 0.5 V VOH Output High Voltage IOH = –4 mA, VCC = Min. 2.4 — 2.4 — V 1 2 3 4 NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns. Power Supply Characteristics -7 Symbol Parameter ICC ISB ISB1 -8 Power Com’l. Com’l. -10 -12 -15 Ind. Com’l. Ind. Com’l. Ind. Com’l. Ind. Units Operating Current CE = VIL SA 210 200 210 190 200 180 190 170 180 mA f = fMAX = 1/tRC VCC = Max IOUT = 0 mA LA 190 180 190 170 180 160 170 150 160 mA Standby Current CE = VIH SA 90 80 80 70 70 60 60 50 50 mA f = fMAX = 1/tRC VCC = Max LA 90 80 80 70 70 60 60 50 50 mA Full Standby Current CE ≥ VCC – 0.2V SA 20 20 20 20 20 20 20 20 20 mA f=0 VCC = Max VIN ≥ VCC – 0.2V or ≤ 0.2V LA 5 5 10 5 10 5 10 5 10 mA 5 6 7 8 9 SHADED AREA = PRELIMINARY DATA NOTE:All values are maximum guaranteed values. Capacitance(1) (TA = +25°C, f = 1.0 MHz) Symbol Parameter Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance 8 pF 10 11 NOTE: 1. This parameter is determined by device characterization but is not production tested. 12 Rev. 2.0 - 7/17/96 3-35 PDM41256 AC Test Conditions Input pulse levels VSS to 3.0V Input rise and fall times 3 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 Figure 1. Output Load Equivalent Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Figure 3. 3-36 Rev. 2.0 - 7/17/96 PDM41256 Read Cycle No. 1(1) 1 2 3 4 Read Cycle No. 2(2) 5 6 7 AC Electrical Characteristics --7(6) Description READ Cycle Sym --8(6) -10(6) -12 -15 READ cycle time tRC Address access time tAA 7 8 10 12 15 ns Chip enable access time tACE 7 8 10 12 15 ns Output hold from address change Chip enable to output in low Z(3, 4, 5) Chip disable to output in high Chip enable to power up Z(3, 4, 5) time(4) 7 8 10 12 15 ns tOH 3 3 3 3 3 ns tLZCE 5 5 5 5 5 ns tHZCE tPU 8 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5 0 6 0 6 0 6 0 6 0 ns tPD 7 8 10 12 15 ns Output enable access time tAOE 5 5 5 6 8 ns Output enable to output in low Z(4, 5) tLZOE Output disable to output in high Z(4, 5) tHZOE 0 5 0 6 0 6 0 6 10 ns Chip disable to power down time(4) 0 9 11 ns 6 ns 12 SHADED AREA = PRELIMINARY DATA. Notes referenced are after Data Retention Table. Rev. 2.0 - 7/17/96 3-37 PDM41256 Write Cycle No. 1 (Write Enable Controlled) Write Cycle No. 2 (Chip Enable Controlled) AC Electrical Characteristics -7(6) Description -8(6) -10(6) -12 -15 WRITE Cycle Sym WRITE cycle time tWC 7 8 10 12 15 ns Chip enable to end of write tCW 7 8 10 10 12 ns Address valid to end of write tAW 7 8 10 10 12 ns Address setup time tAS 0 0 0 0 0 ns Address hold from end of write tAH 0 0 0 0 0 ns Write pulse width tWP 7 8 10 10 11 ns Data setup time tDS 6 7 7 7 7 ns Data hold time tDH 0 0 0 0 0 ns (4, 5) tLZWE 0 0 0 0 0 ns Z(4, 5) tHZWE Write disable to output in low Z Write enable to output in high Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3 3 3 3 3 ns SHADED AREA = PRELIMINARY DATA. 3-38 Rev. 2.0 - 7/17/96 PDM41256 Low VCC Data Retention Waveform 1 2 3 4 Data Retention Electrical Characteristics (LA Version Only) Symbol Parameter VDR VCC for Retention Data ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR(4) Operation Recovery Time Test Conditions CE ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or ≤ 0.2V Min. Typ. Max. Unit 2 — — V VCC = 2V — 95 500 µA VCC = 3V — 350 750 µA 0 — — ns tRC — — ns NOTES: (For three previous Electrical Characteristics tables) 1. The device is continuously selected. Chip Enable is held in its active state. 2. The address is valid prior to or coincident with the latest occuring Chip Enable. 3. At any given temperature and voltage condition, tHZCE is less than tLZCE. 4. This parameter is sampled. 5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage 6. Vcc = 5V ± 5%. 5 6 7 8 9 10 11 12 Rev. 2.0 - 7/17/96 3-39 PDM41256 Ordering Information 3-40 Rev. 2.0 - 7/17/96