ETC SSD1852T2R1

TABLE OF CONTENTS
1
GENERAL DESCRIPTION ................................................................................................................ 1
2
FEATURES ........................................................................................................................................ 2
3
ORDERING INFORMATION.............................................................................................................. 2
4
BLOCK DIAGRAM............................................................................................................................. 3
5
DIE PAD ARRANGEMENT................................................................................................................ 4
6
PIN DESCRIPTION ............................................................................................................................ 8
6.1
RES ............................................................................................................................................ 8
6.2
PS0 & PS1 .................................................................................................................................. 8
6.3
CS .............................................................................................................................................. 8
6.4
D/ C ............................................................................................................................................. 8
6.5
R/ W ( WR ) .................................................................................................................................. 8
6.6
E( RD ) ......................................................................................................................................... 8
6.7
D0~D7 .......................................................................................................................................... 8
6.8
INTRS ......................................................................................................................................... 8
6.9
REF ............................................................................................................................................. 9
6.10
VDD .............................................................................................................................................. 9
6.11
VSS ............................................................................................................................................... 9
6.12
VCI................................................................................................................................................ 9
6.13
VCC .............................................................................................................................................. 9
6.14
C1P,C2P,C3P,C4P,C5P,C1N and C2N ................................................................................................ 9
6.15
VL6 ............................................................................................................................................... 9
6.16
VR ................................................................................................................................................ 9
6.17
VEXT ............................................................................................................................................. 9
6.18
VL5, VL4, VL3, and VL2 .................................................................................................................. 9
vi
6.19
ROW0~ROW127 ...................................................................................................................... 10
6.20
ICONS....................................................................................................................................... 10
6.21
SEG0~SEG127......................................................................................................................... 10
6.22
OSC1 ........................................................................................................................................ 10
6.23
TEST0~TEST13........................................................................................................................ 10
6.24
TEST_IN0 ................................................................................................................................. 10
6.25
NC ............................................................................................................................................. 10
7
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 11
7.1
Command Decoder and Command Interface....................................................................... 11
7.2
MPU Parallel 6800-series Interface........................................................................................ 11
7.3
MPU Parallel 8080-series interface........................................................................................ 11
7.4
MPU Serial 4-wire Interface.................................................................................................... 11
7.5
MPU Serial 3-wire Interface.................................................................................................... 11
7.6
Modes of operation ................................................................................................................. 12
7.7
Oscillator Circuit ..................................................................................................................... 12
7.8
LCD Driving voltage Generator and Regulator .................................................................... 13
7.8.1 3X, 4X, 5X and 6X DC-DC voltage converter..................................................................... 13
7.8.2 Voltage Regulator................................................................................................................ 13
7.8.3 Contrast Control (Voltages referenced to VSS)................................................................. 13
7.8.4 Bias Divider.......................................................................................................................... 14
7.8.5 Bias Ratio Selection circuitry ............................................................................................ 14
7.8.6 Self adjust temperature compensation circuitry ............................................................. 14
7.9
Graphic Display Data RAM (GDDRAM)................................................................................. 15
7.10
Reset Circuit ............................................................................................................................ 15
7.11
Display Data Latch .................................................................................................................. 16
7.12
HV Buffer Cell (Level Shifter)................................................................................................. 16
7.13
Level Selector.......................................................................................................................... 16
vii
7.14
LCD Panel Driving Waveform ................................................................................................ 16
8
COMMAND TABLE.......................................................................................................................... 19
9
COMMAND DESCRIPTIONS .......................................................................................................... 25
9.1
Set Lower Column Address ................................................................................................... 25
9.2
Set Upper Column Address ................................................................................................... 25
9.3
Set Internal Regulator Resistor Ratio ................................................................................... 25
9.4
Set Power Control Register ................................................................................................... 25
9.5
Set Display Start Line ............................................................................................................. 25
9.6
Set Display Offset ................................................................................................................... 25
9.7
Set Multiplex Ratio .................................................................................................................. 25
9.8
Set N-line Inversion ................................................................................................................ 25
9.9
Set LCD Bias............................................................................................................................ 25
9.10
Set DC-DC Converter Factor.................................................................................................. 26
9.11
Set Contrast Control Register ............................................................................................... 26
9.12
Set Gray Scale Mode (White/Light Gray/Dark Gray/Black) ................................................. 26
9.13
Set PWM and FRC ................................................................................................................... 27
9.14
Set Segment Re-map .............................................................................................................. 27
9.15
Set Icon Enable ....................................................................................................................... 27
9.16
Set Entire Display On/Off ....................................................................................................... 27
9.17
Set Normal/Inverse Display.................................................................................................... 27
9.18
Set Power Save Mode............................................................................................................. 27
9.19
Start Internal Oscillator .......................................................................................................... 27
9.20
Set Display On/Off .................................................................................................................. 27
9.21
Set Page Address ................................................................................................................... 27
9.22
Set COM Output Scan Direction ............................................................................................ 27
9.23
Set Modify-Read ...................................................................................................................... 27
9.24
Exit Power-save Mode ............................................................................................................ 28
viii
9.25
Software Reset ........................................................................................................................ 28
9.26
Exit N-line Inversion ............................................................................................................... 28
9.27
Set Display Data Length......................................................................................................... 28
9.28
Exit Modify-read ...................................................................................................................... 28
9.29
Set TC value............................................................................................................................. 29
9.30
Enable internal oscillator resistor ......................................................................................... 29
9.31
Enable Frame Frequency setting .......................................................................................... 29
9.32
Set COM Scan Sequence ....................................................................................................... 29
9.33
Set Frame Frequency setting................................................................................................. 29
9.34
OTP setting and programming .............................................................................................. 30
Step 1. Find OTP offset .................................................................................................................. 30
Step 2. OTP programming ............................................................................................................. 31
9.35
Enable DMA mode .................................................................................................................. 34
9.36
Set Start/End Column and Page address in DMA mode ..................................................... 34
9.37
Lock/Unlock Interface............................................................................................................. 35
10
MAXIMUM RATINGS ....................................................................................................................... 36
11
DC CHARACTERISTICS ................................................................................................................. 36
12
AC CHARACTERISTICS ................................................................................................................. 39
13
APPLICATION EXAMPLES ............................................................................................................ 45
14
APPENDIX ....................................................................................................................................... 46
14.1
TAB Drawing............................................................................................................................ 46
ix
TABLE OF FIGURES
Figure 1 - Block Diagram .............................................................................................................................. 3
Figure 2 - Die Pad Assignment ..................................................................................................................... 4
Figure 3 - Display Data Read Back Procedure – Insertion of Dummy Read.............................................. 12
Figure 4 - Oscillator..................................................................................................................................... 12
Figure 5 - DC-DC Converter Configurations ............................................................................................... 13
Figure 6 - Voltage Regulator Output for Different Gain/Contrast Settings (VDD = 2.775V; VCI = 3V; DC-DC
o
level = 6X; TC2 = -0.125%/ C)............................................................................................................. 14
Figure 7 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 70H. ....... 17
Figure 8 - LCD Driving Waveform for Displaying “0” (0 line inversion) ....................................................... 18
Figure 9 - Sequence for setting frame frequency ....................................................................................... 29
Figure 10 - Sequence for setting the DMA mode. ...................................................................................... 34
Figure 11 - Sequence for disable the DMA mode....................................................................................... 34
Figure 12 - OTP programming circuitry....................................................................................................... 31
Figure 13 - Flow chart of OTP programming Procedure............................................................................. 32
o
Figure 14 Relationship between Frame Frequency and Oscillator resistor (TA=25 C, VDD=2.775V) ......... 40
Figure 15 - 6800-Series MPU Parallel Interface Characteristics (PS0=H; PS1=H).................................... 41
Figure 16 - 8080-Series MPU Parallel Interface Characteristics (PS0 = H, PS1 = L) ................................ 42
Figure 17 - 3-wires Serial Interface Characteristics (PS0 = L, PS1 = L) .................................................... 43
Figure 18 - 4-wire Serial Interface Timing Characteristics (PS0 = L, PS1 = H).......................................... 44
Figure 19 - Typical Application.................................................................................................................... 45
Figure 20 - SSD1852T TAB Drawing 1....................................................................................................... 46
Figure 21 - SSD1852T TAB Drawing 2....................................................................................................... 47
Figure 22 - SSD1852T2 TAB Drawing 1..................................................................................................... 48
Figure 23 - SSD1852T2 TAB Drawing 2..................................................................................................... 49
LIST OF TABLES
Table 1 - Ordering Information ...................................................................................................................... 2
Table 2 - SSD1852 Bump Die Pad Coordinates........................................................................................... 5
Table 3 - Command Table (D/C# = 0, R/W#(WR#) = 0, E/(RD#) = 1)........................................................ 19
Table 4 - Extended Command Table .......................................................................................................... 22
Table 5 - Maximum Ratings (Voltage Reference to VSS) ............................................................................ 36
Table 6 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V,
TA = -30 to +85°C)................................................................................................................................ 36
Table 7 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V,
TA = 25°C) ............................................................................................................................................ 39
Table 8 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 1.8, TA = -30 to +85°C)
............................................................................................................................................................. 41
Table 9 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.7V, TA = -30 to +85°C)
............................................................................................................................................................. 42
Table 10 - 3-wires Serial Interface Timing Characteristics (VDD - VSS = 1.8V, TA = -30 to +85°C) ............. 43
Table 11 - 4-wires Serial Interface Timing Characteristics (VDD - VSS = 2.7V, TA = -30 to +85°C) ............. 44
x
SOLOMON SYSTECH LIMITED
SEMICONDUCTOR TECHNICAL DATA
SSD1852
Advance Information
LCD Segment / Common Driver
With Controller
CMOS
1
General Description
SSD1852 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic
display system. It consists of 257 high voltage driving output pins for driving 128 Segments, 128
Commons and an ICON line.
SSD1852 displays data directly from its internal 128x129x2 bits Graphic Display Data RAM
(GDDRAM). Data/Commands are sent from general MCU through a hardware selectable
6800/8080series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface.
SSD1852 embeds a DC-DC Converter, an LCD Voltage Regulator, an On-Chip Bias Divider
and an On-Chip Oscillator, which reduce the number of external components. With the special
design on minimizing power consumption and die/package layout, SSD1852 is suitable for any
portable battery-driven applications requiring a long operation period and compact size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copyright  2003 SOLOMON Systech Limited
Rev 1.0
01/2003
2
FEATURES
128 x 128 Dot-matrix 4-gray levels display driver with an icon line
Single supply operation, 1.8 V – 3.3 V
Minimum +8.0V LCD driving output voltage
Maximum +15.0V LCD driving output voltage
Low current sleep mode
On-chip voltage generator or external LCD driving power supply selectable
On-chip oscillator with external resistor
On-chip bias divider
On-chip 128x129x2bits graphic display data RAM
3X/4X/5X/6X DC–DC converter
Programmable multiplex ratio in dot-matrix display area from 16Mux ~ 129Mux
Programmable bias ratio from 1/5 ~ 1/12
8-bit 6800-series & 8-bit 8080-series parallel interface
Serial peripheral interface
Re-mapping of row & column drivers
Vertical scrolling
Display offset control
64 level internal contrast control
External contrast control
o
Programmable LCD driving voltage temperature coefficients from TC0 (-0.05%/ C) to
o
TC7 (-0.25%/ C)
One time programmable (OTP) capability for VL6 adjustment
Programmable COM output sequence
Direct memory access mode
Selectable internal/external oscillator resistor
Available in gold bump die and TAB (Tape Automated Bonding) Package
3
ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part
Number
SSD1852Z
SSD1852TR1
SSD1852T2R1
SSD1852
Rev 1.0
01/2003
Seg
Com
Default Bias
Package Form
128
128
128
128 + 1
100
128
1/12
1/12
1/12
Gold Bump Die
TAB
TAB
2
SOLOMON
4
BLOCK DIAGRAM
ICONS
ROW0 ~
ROW127
SEG0 ~ SEG 127
HV Buffer Cell Level Shifter
Level Selector
VL6
VL5
VL4
VL3
VL2
VSS
Display Data Latch
VR
Display
Timing
Generator
OSC1
LCD Driving
Voltage
Generator
3X / 4X / 5X /
6X DC/DC
Converter,
Voltage
Regulator,
Bias Divider,
Contrast
Control,
Temperature
Compensation
Oscillator
GDDRAM
128 X 129 X 2 Bits
TEST0
:
TEST13
VCC
C1P
C2P
C3P
C4P
C5P
C2N
REF
INTRS
VCI
VEXT
TEST_IN0
Command Decoder
VDD
VSS
Command Interface
RES PS0
PS1
CS
D/ C
Parallel / Serial Interface
E
R/W
( WR ) ( RD )
D7 D6 D5
(SDA)(SCK)
D4
D3
D2
D1 D 0
Figure 1 - Block Diagram
3
SSD1852
Rev 1.0
01/2003
SOLOMON
5
DIE PAD ARRANGEMENT
Note:
1.
Center : -4518,-342
Center : -4706,320
2.
3.
4.
25
Diagram showing the face of the
die.
Coordinates are reference to
center of the chip.
Unit of coordinates and Size of all
alignment marks are in µm.
All alignment keys do not contain
gold bump.
25
25
25
25
100
25
100
y
(0,0)
25
25
25
25
x
100
50
100
75
18
Center 4683,320
Center : 4518,-342
100
100
Die Size: 10.49 mm x 1.72mm
Die Thickness: 533±25µm
Bump Height: Typical 18µm
Bump co-planarity <3µm (within die)
Figure 2 - Die Pad Assignment
SSD1852
Rev 1.0
01/2003
4
SOLOMON
Table 2 - SSD1852 Bump Die Pad Coordinates
Signal
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ROW124
ROW125
ROW126
ROW127
ICONS
TEST8
TEST9
TEST0
TEST1
TEST2
TEST3
TEST4
VDD
TEST_IN0
VSS
PS0
VDD
PS1
VSS
CS
CS
RES
VDD
D/C
D/C
R / W ( WR )
VSS
E( RD )
VDD
D0
D1
D2
D3
D4
D5
D6
D6
D7
D7
D7
D7
VDD
VDD
VDD
VDD
VCI
VCI
VCI
VCI
VCI
5
SSD1852
X-pos
-4763.1
-4700.1
-4650.1
-4600.1
-4550.1
-4457.9
-4381.7
-4305.5
-4229.3
-4153.1
-4076.9
-4000.7
-3924.5
-3848.3
-3772.1
-3695.9
-3619.7
-3543.5
-3467.3
-3391.1
-3314.9
-3238.7
-3162.5
-3086.3
-3010.1
-2933.9
-2857.7
-2781.5
-2705.3
-2629.1
-2552.9
-2476.7
-2400.5
-2324.3
-2248.1
-2171.9
-2095.7
-2019.5
-1943.3
-1867.1
-1790.9
-1714.7
-1638.5
-1562.3
-1486.1
-1409.9
-1333.7
-1257.5
-1181.3
-1105.1
Rev 1.0
01/2003
Y-pos
-705.0
-705.0
-705.0
-705.0
-705.0
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
Pad #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Signal
VCI
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
C5P
C5P
C5P
C3P
C3P
C3P
C3P
C1N
C1N
C1N
C1N
C1P
C1P
C1P
C1P
C2P
C2P
C2P
C2P
C2N
C2N
C2N
C2N
C4P
C4P
C4P
C4P
VDD
REF
VSS
VEXT
VDD
INTRS
VSS
VSS
VL2
VL2
VL2
VL2
VL3
VL3
X-pos
-1028.9
-952.7
-876.5
-800.3
-724.1
-647.9
-571.7
-495.5
-419.3
-343.1
-266.9
-190.7
-114.5
-38.3
37.9
114.1
190.3
266.5
342.7
418.9
495.1
571.3
647.5
723.7
799.9
876.1
952.3
1028.5
1104.7
1180.9
1257.1
1333.3
1409.5
1485.7
1561.9
1638.1
1714.3
1790.5
1866.7
1942.9
2019.1
2095.3
2171.5
2247.7
2323.9
2400.1
2476.3
2552.5
2628.7
2704.9
Y-pos
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
Pad #
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Signal
VL3
VL3
VL4
VL4
VL4
VL4
VL5
VL5
VL5
VL5
VL6
VL6
VL6
VL6
VR
VR
TEST11
TEST12
TEST13
OSC1
TEST5
TEST6
TEST10
TEST7
ROW63
ROW62
ROW61
ROW60
ROW59
ROW58
ROW57
ROW56
ROW55
ROW54
ROW53
ROW52
ROW51
ROW50
ROW49
ROW48
ROW47
ROW46
ROW45
ROW44
ROW43
ROW42
ROW41
ROW40
ROW39
ROW38
X-pos
2781.1
2857.3
2933.5
3009.7
3085.9
3162.1
3238.3
3314.5
3390.7
3466.9
3543.1
3619.3
3695.5
3771.7
3847.9
3924.1
4000.3
4076.5
4152.7
4228.9
4305.1
4381.3
4457.5
4544.9
4599.9
4649.9
4699.9
4762.9
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
SOLOMON
Y-pos
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-702.8
-705.0
-705.0
-705.0
-705.0
-705.0
-713.0
-650.0
-600.0
-550.0
-500.0
-450.0
-400.0
-350.0
-300.0
-250.0
-200.0
-150.0
-100.0
-50.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
Pad #
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Signal
ROW37
ROW36
ROW35
ROW34
ROW33
ROW32
ROW31
ROW30
ROW29
ROW28
ROW27
ROW26
ROW25
ROW24
ROW23
ROW22
ROW21
ROW20
ROW19
ROW18
ROW17
ROW16
ROW15
ROW14
ROW13
ROW12
ROW11
ROW10
ROW9
ROW8
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
ICONS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SSD1852
X-pos
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
5094.1
4762.9
4699.9
4649.9
4599.9
4549.9
4499.9
4449.9
4399.9
4349.9
4299.9
4249.9
4199.9
4149.9
4099.9
4049.9
3999.9
3949.9
3899.9
3849.9
3799.9
3749.9
3699.9
3649.9
3599.9
3549.9
3499.9
3449.9
3399.9
3349.9
3299.9
3249.9
3199.9
3149.9
3099.9
3049.9
2999.9
2949.9
2899.9
2849.9
2799.9
2749.9
2699.9
2649.9
Y-pos
Pad #
400.0
450.0
500.0
550.0
600.0
650.0
713.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Rev 1.0
01/2003
Signal
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
X-pos
2599.9
2549.9
2499.9
2449.9
2399.9
2349.9
2299.9
2249.9
2199.9
2149.9
2099.9
2049.9
1999.9
1949.9
1899.9
1849.9
1799.9
1749.9
1699.9
1649.9
1599.9
1549.9
1499.9
1449.9
1399.9
1349.9
1299.9
1249.9
1199.9
1149.9
1099.9
1049.9
999.9
949.9
899.9
849.9
799.9
749.9
699.9
649.9
599.9
549.9
499.9
449.9
399.9
349.9
299.9
249.9
199.9
149.9
Y-pos
Pad #
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Signal
X-pos
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
99.9
49.9
-0.1
-50.1
-100.1
-150.1
-200.1
-250.1
-300.1
-350.1
-400.1
-450.1
-500.1
-550.1
-600.1
-650.1
-700.1
-750.1
-800.1
-850.1
-900.1
-950.1
-1000.1
-1050.1
-1100.1
-1150.1
-1200.1
-1250.1
-1300.1
-1350.1
-1400.1
-1450.1
-1500.1
-1550.1
-1600.1
-1650.1
-1700.1
-1750.1
-1800.1
-1850.1
-1900.1
-1950.1
-2000.1
-2050.1
-2100.1
-2150.1
-2200.1
-2250.1
-2300.1
-2350.1
Y-pos
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
6
SOLOMON
Pad #
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
Signal
X-pos
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
ROW64
ROW65
ROW66
ROW67
ROW68
ROW69
ROW70
ROW71
ROW72
ROW73
ROW74
ROW75
ROW76
ROW77
ROW78
ROW79
ROW80
ROW81
ROW82
ROW83
ROW84
ROW85
ROW86
ROW87
ROW88
ROW89
ROW90
ROW91
ROW92
ROW93
ROW94
ROW95
ROW96
-2400.1
-2450.1
-2500.1
-2550.1
-2600.1
-2650.1
-2700.1
-2750.1
-2800.1
-2850.1
-2900.1
-2950.1
-3000.1
-3050.1
-3100.1
-3150.1
-3200.1
-3250.1
-3300.1
-3350.1
-3400.1
-3450.1
-3500.1
-3550.1
-3600.1
-3650.1
-3700.1
-3750.1
-3800.1
-3850.1
-3900.1
-3950.1
-4000.1
-4050.1
-4100.1
-4150.1
-4200.1
-4250.1
-4300.1
-4350.1
-4400.1
-4450.1
-4500.1
-4550.1
-4600.1
-4650.1
-4700.1
-4763.1
-5094.3
-5094.3
Y-pos
Pad #
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
705.0
713.0
650.0
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
Signal
X-pos
Y-pos
ROW97
ROW98
ROW99
ROW100
ROW101
ROW102
ROW103
ROW104
ROW105
ROW106
ROW107
ROW108
ROW109
ROW110
ROW111
ROW112
ROW113
ROW114
ROW115
ROW116
ROW117
ROW118
ROW119
ROW120
ROW121
ROW122
ROW123
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
-5094.3
600.0
550.0
500.0
450.0
400.0
350.0
300.0
250.0
200.0
150.0
100.0
50.0
0.0
-50.0
-100.0
-150.0
-200.0
-250.0
-300.0
-350.0
-400.0
-450.0
-500.0
-550.0
-600.0
-650.0
-713.0
Bump size :
Size
X
Y
Pad
1
2~5
6~123
124~127
128
129
130~156
349
59
33
50
33
59
65
65
348
1
157
158
159~347
348
349
350~376
377
65
59
33
59
65
65
65
59
65
65
65
59
33
59
158
y
die
face
377
65
65
60
65
65
59
33
Size
X
Y
Pad
x
157
129
128
Remarks: TEST0~TEST13 and TEST_IN0 pins are used for internal test. TEST0~TEST13 should be left
open. TEST_IN0 should be connected to VSS.
7
SSD1852
Rev 1.0
01/2003
SOLOMON
6
PIN DESCRIPTION
6.1
RES
This pin is reset signal input. When the pin is low, initialization of the chip is executed.
6.2
PS0 & PS1
These two pins determine the interface protocol between the driver and MCU. Refer to the
following table.
PS0
L
L
H
H
6.3
PS1
L
H
L
H
Interface
3-wire SPI (write only)
4-wire SPI (write only)
8080 parallel interface (read and write allowed)
6800 parallel interface (read and write allowed)
CS
This pin is chip select input. The chip is enabled for display data/command transfer only when
CS is low.
6.4
D/ C
This input pin is to identify display data/command cycle. When the pin is high, the data written to
the driver will be written into display RAM. When the pin is low, the data will be interpreted as
command. This pin must be connected to VSS when 3-lines SPI interface is used.
6.5
R/ W ( WR )
This pin is a microprocessor interface signal. When interfacing 6800-series microprocessor, the
signal indicates read mode when high and write mode when low. When interfacing 8080microprocessor, the data write operation is initiated when R/ W( WR ) is low and the chip is
selected.
6.6
E( RD )
This pin is microprocessor interface signal. When interfacing 6800-series microprocessor, the
data operation is initiated when E( RD ) is high and the chip is selected. When interfacing 8080microprocessor, the data read operation is initiated when E( RD ) is low and the chip is selected.
6.7
D0~D7
These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus.
When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input
SCK.
6.8
INTRS
This pin is an input pin to enable the internal resistors network for the voltage regulator when
INTRS is high. When external regulator is used, this pin must be connected to VSS, and external
resistors R2/R1 should be connected to VL6, VR and VSS.
SSD1852
Rev 1.0
01/2003
8
SOLOMON
6.9
REF
This pin is an input pin to enable the internal reference voltage used for the internal regulator.
When it is high, an internal reference voltage source will be used. When it is low, an external
reference voltage source must be provided in VEXT pin if internal regulator is used.
6.10 VDD
Power supply pin.
6.11 VSS
Ground.
6.12 VCI
Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to
the multiple factor (3X, 4X, 5X or 6X) times VCI with respect to VSS.
Note: voltage at this input pin must be larger than or equal to VDD.
6.13 VCC
This is the most positive voltage supply pin of the chip. It can be supplied externally or
generated by the internal DC-DC converter.
When using internal DC-DC converter as generator, voltage at this pin is for internal reference
only. It CANNOT be used for driving external circuitry.
6.14 C1P,C2P,C3P,C4P,C5P,C1N and C2N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected among
these pins.
6.15 VL6
This pin is the most positive LCD driving voltage. It can be supplied externally or generated by
the internal regulator.
6.16 VR
This pin is an input of the internal voltage regulator. When the internal resistors network for the
voltage regulator is disabled (INTRS is pulled low), external resistors should be connected
between VSS and VR, and VR and VL6, respectively.
6.17 VEXT
This pin is an input to provide an external voltage reference for the internal voltage regulator
when REF pin is pulled L. When internal reference is selected (REF is pulled high), the VEXT pin
should be left open (No connection).
6.18 VL5, VL4, VL3, and VL2
LCD driving voltages. They can be supplied externally or generated by the internal bias divider.
They have the following relationship:
VL6 > VL5 > VL4 > VL3 > VL2 > VSS
VL5
VL4
VL3
VL2
9
SSD1852
1:a bias
(a-1)/a*VL6
(a-2)/a*VL6
2/a*VL6
1/a*VL6
Rev 1.0
01/2003
SOLOMON
6.19 ROW0~ROW127
These pins provide the row driving signals ROW0 – ROW127 to the LCD panel.
6.20 ICONS
This pin is the special icon line ROW signal output.
6.21 SEG0~SEG127
These pins provide the LCD column driving signals. Their voltage level is VSS during sleep
mode and standby mode.
6.22 OSC1
This pin connects to on-chip oscillator when external resistor connected between OSC1 and
VDD. By sending a start oscillator ON command, the on-chip oscillator will operate and its
frequency is controlled by the external resistor.
6.23 TEST0~TEST13
These pins are used for internal test and should NOT be connected to any signal pins nor
shorted together. They should be left open.
6.24 TEST_IN0
This pin is used for internal only and should be connected to VSS.
6.25 NC
The No connection pin should NOT be connected to any signal pins nor shorted to other NC
pins. It should be left open in application.
SSD1852
Rev 1.0
01/2003
10
SOLOMON
7
FUNCTIONAL BLOCK DESCRIPTIONS
7.1
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data
is directed to this module based upon the input of the D/ C pin. If D/ C is high, data is written to
Graphic Display Data RAM (GDDRAM). If D/ C is low, the input at D0-D7 is interpreted as a
Command and it will be decoded and written to the corresponding command register.
Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset
pulse of about 10us, all internal circuitry will be back to its initial status. Refer to Command
Description section for more information.
7.2
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/ W( WR ), D/ C ,
E( RD ) and CS . R/ W( WR ) input High indicates a read operation from the Graphic Display Data
RAM (GDDRAM) or the status register. R/ W( WR ) input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the status of D/ C input. The
E( RD ) and CS input serves as data latch signal (clock) when they are high and low
respectively. Refer to Figure 15 of parallel timing characteristics for Parallel Interface Timing
Diagram of 6800-series microprocessors for details.
In order to match the operating frequency of display RAM with that of the microprocessor,
pipeline processing is internally performed which requires the insertion of a dummy read before
the first actual display data read. This is shown in Figure 3.
7.3
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/ W( WR ), E( RD ),
D/ C and CS . The CS input serves as data latch signal (clock) when it is low. D/ C determines
the D0~D7 a display data or status register read. WR and RD inputs indicate a write or read
cycle when CS is low. Refer to Figure 16 of parallel timing characteristics for Parallel Interface
Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display
data read.
7.4
MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . SDA is
shifted into an 8-bit shift register on every rising edge of SCK in the order of D7, D6,... D0. D/ C is
sampled on every eighth clock cycles and the data byte in the shift register is written to the
Display Data RAM or command register in the same clock cycle. No extra clock cycle or
command is required to end the transmission.
7.5
MPU Serial 3-wire Interface
Operation is similar to 4-wire serial interface while D/ C is not been used. The Set Display
Data Length command is used to indicate a specified number display data byte (1-256) to be
transmitted. Next byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in
the serial communication, a hardware reset pulse at RES pin is required to initialize the chip for
re-synchronization.
11
SSD1852
Rev 1.0
01/2003
SOLOMON
7.6
Modes of operation
6800 parallel
Yes
Yes
Status only
Yes
Data Read
Data Write
Command Read
Command Write
8080 parallel
Yes
Yes
Status only
Yes
Serial
No
Yes
No
Yes
D/C
WR
RD
D0~D7
N
n
write column address
dummy read
data read1
n+1
data read2
n+2
data read 3
n+3
data read4
Figure 3 - Display Data Read Back Procedure – Insertion of Dummy Read
7.7
Oscillator Circuit
This module is an On-chip low power oscillator circuitry with external resistor (Figure 4).
The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in
the Display Timing Generator block
VDD
OSC1
oscillator
Circuit
OSC
Figure 4 - Oscillator
SSD1852
Rev 1.0
01/2003
12
SOLOMON
7.8
LCD Driving voltage Generator and Regulator
This module generates the LCD voltage needed for display output. It takes a single supply
input and generates necessary bias voltages. It consists of:
7.8.1
3X, 4X, 5X and 6X DC-DC voltage converter
Please refer to Figure 5.
VSS
VCC
C5P
C3P
C1N
C1P
C2P
C2N
C4P
+
+
+
-
VSS
VCC
C5P
C3P
C1N
C1P
C2P
C2N
C4P
+
+
+
+
-
4X Boost
3X Boost
VSS
VCC
C5P
C3P
C1N
C1P
C2P
C2N
C4P
+
+
+
+
+
5X Boost
VSS
VCC
C5P
C3P
C1N
C1P
C2P
C2N
C4P
+
+
+
+
-
+
-
+
6X Boost
Remarks: capacitor = 1.0 ~ 4.7uF
Figure 5 - DC-DC Converter Configurations
7.8.2 Voltage Regulator
The feedback gain control for LCD driving contrast curves can be selected by INTRS pin
to either internal (INTRS pin = H) or external (INTRS pin = L). If internal resistor network is
enabled, eight settings can be selected through software command. If external control is
selected, external resistors are required to be connected between VSS and VR (R1), and
between VR and VL6 (R2). See application circuit diagrams for detail connections.
7.8.3 Contrast Control (Voltages referenced to VSS)
Software control of the 64-contrast voltage levels at each voltage regulator feedback
gains. The equations of calculating the LCD driving voltage are given as the following,
 R
V L 6 = 1 + 2
 R1

 *Vout

 63 − α 
V out = 1 −
 * V ref
210


13
SSD1852
Rev 1.0
01/2003
, where Vref = 1.4V
SOLOMON
VL6 Vs Contrast
16
14
IR0
12
IR1
IR2
VL6[V]
10
IR3
IR4
8
IR5
IR6
IR7
6
4
2
Contrast[0~63]
0
0
10
20
30
40
50
60
70
Figure 6 - Voltage Regulator Output for Different Gain/Contrast Settings (VDD = 2.775V; VCI = 3V;
o
DC-DC level = 6X; TC2 = -0.125%/ C)
7.8.4 Bias Divider
If the output op-amp buffer option in Set Power Control Register command is enabled,
this circuit block will divide the regulator output (VL6) to give the LCD driving levels (VL2 VL5).
A low power consumption circuit design in this bias divider saves most of the display
current comparing to traditional design.
7.8.5 Bias Ratio Selection circuitry
Software control of 1/5 to 1/12 bias ratio is to match the characteristic of LCD panel.
7.8.6 Self adjust temperature compensation circuitry
Provide 8 different compensation grade selections to satisfy the various liquid crystal
temperature grades. The grading can be selected by software control. Default temperature
o
coefficient (TC) value is -0.125%/ C.
SSD1852
Rev 1.0
01/2003
14
SOLOMON
7.9
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The
size of the RAM is 128 x 129 x 2 = 33024 bits. Figure 7 is a description of the GDDRAM
address map.
For mechanical flexibility, re-mapping on both Segment and Common outputs are
provided.
For vertical scrolling of display, an internal register storing the display start line can be
set to control the portion of the RAM data mapped to the display. Figure 7 shows the case in
which the display start line register is set at 70H.
For those GDDRAM out of the display common range, they could still be accessed, for
either preparation of vertical scrolling data or even for the system usage.
7.10 Reset Circuit
This block includes Power On Reset circuitry and the hardware reset pin, RES . Both of
these have the same reset function. Once RES receives a negative reset pulse, all internal
circuitry will start to initialize. Minimum pulse width for completing the reset sequence is 10us.
Status of the chip after reset is given by:
Register
Page address
Column address
Display ON/OFF
Display Start Line
Display Offset
Mux Ratio
Normal/Reverse Display
N-line Inversion
Entire Display
DC-DC booster
Internal Resistor Ratio
Contrast
LCD Bias Ratio
Scan direction of COM
Segment Re-map
Internal oscillator
Power save mode
Data display length
FRC, PWM Mode
White Palette
Light Gray Palette
Dark Gray Palette
Black Palette
Temperature coefficient
Icon display
Power control
Scan sequence of COM
DMA mode
15
SSD1852
Rev 1.0
01/2003
Default Value
0
0
0
0
0
80H
0
0
0
0
0
20H
7
0
0
0
0
0
0
(0, 0, 0, 0)
(0, 0, 0, 0)
(9, 9, 9, 9)
(9, 9, 9, 9)
2
0
0,0,0
0
0
Descriptions
Display OFF
GDDRAM page 0,D0
COM0 is mapped to ROW0
128 Mux
Normal Display
No N-line Inversion
Entire Display is OFF
3X booster is selected
Gain = 3.45 (IR0)
1/12 Bias Ratio
Normal Scan direction
Segment re-map is disabled
Internal oscillator is OFF
Power save mode is OFF
4FRC, 9PWM
o
PTC2 (-0.125%/ C)
Icon display line is OFF
Booster, regulator & divider are both disabled
Normal Scan sequence
Disable DMA mode
SOLOMON
7.11 Display Data Latch
This block is a series of latches carrying the display signal information. These latches
hold the data, which will be fed to HV Buffer Cell and Level Selector to output the required
voltage levels. The number of latches are 128+129= 257
7.12 HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter that translates the low voltage output signal to the
required driving voltage. The output is shifted out with an internal FRM clock that comes from
the Display Timing Generator. The voltage levels are given by the level selector which is
synchronized with the internal M signal.
7.13 Level Selector
Level Selector is a control of the display synchronization. Display voltage can be
separated into two sets and used with different cycles. Synchronization is important since it
selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the ROW or
SEG LCD waveform.
7.14 LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected
to a LCD panel. The waveforms are shown in Figure 8 illustrating the desired multiplex scheme
with N-line Inversion feature disabled (default).
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16
SOLOMON
(MSB)
First Byte
(LSB)
Second Byte
0
Page 1
0
0
0
……………
……………
……………
……………
01
7E
02
7D
03
7C
………..
………..
7C
03
7D
02
7E
01
7F
00
SEG2
SEG3
………..
SEG124
SEG125
SEG126
SEG127
SEG Outputs
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM111
COM110
COM109
COM108
COM107
COM106
COM105
COM104
COM103
COM102
COM101
COM100
COM99
COM98
COM97
COM96
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
ICONS
COM127
COM126
COM125
COM124
COM123
COM122
COM121
COM120
COM119
COM118
COM117
COM116
COM115
COM114
COM113
COM112
ICONS
F8
F9
FA
FB
FC
FD
FE
FF
Internal Column Address
SEG Re-map = 0 00
SEG Re-map = 1 7F
SEG1
………..
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
SEG0
00
01
02
03
04
05
06
07
D 0
………..
D 1
………..
D 2
………..
D 3
………..
Page 14 1 1 1 0
D 4
………..
D 5
………..
D 6
………..
D 7
………..
D 0
………..
D 1
………..
D 2
………..
D 3
………..
Page 15 1 1 1 1
D 4
………..
D 5
………..
D 6
………..
D 7
………..
………..
Page 16 * - - - - D 0
(*) Page address is set to 16, if only ICON control register is set to '1' (A3Hex)
Re-mapped
……………
0
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
……………
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
……………
Page 0
D
D
D
D
0
D
D
D
D
D
D
D
D
1
D
D
D
D
Normal
……………
Line
Address
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
Page Address
D3 D2 D2 D0
Remarks: Column address will be incremented automatically after writing MSB and LSB.
Figure 7 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 70H
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SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
TIME SLOT
1 2 3 4 5 6 7 8 9
...
*
N 1 2 3 4 5 6 7 8 9
...
*
N 1 2 3 4 5 6 7 8 9
...
*
N 1 2 3 4 5 6 7 8 9
...
*
N
VL6
VL5
VL4
COM0
VL3
VL2
VSS
VL6
VL5
VL4
COM1
VL3
VL2
VSS
VL6
VL5
VL4
SEG0
VL3
VL2
VSS
VL6
VL5
VL4
SEG1
VL3
VL2
VSS
* Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 128 on POR.
Figure 8 - LCD Driving Waveform for Displaying “0” (0 line inversion)
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SOLOMON
8
COMMAND TABLE
Table 3 - Command Table (D/ C = 0, R/ W( WR ) = 0, E( RD ) = 1)
Bit Pattern
0000 C3C2C1C0
Command
Set Lower Column
Address
Set Upper Column
Address
Set Internal Regulator
Resistor Ratio
0001 0C6C5C4
0010 0R2R1R0
0010 1VC VR VF
Set Power Control
Register
0100 00XX
XL6L5L4 L3L2L1L0
Set Display Start Line
0100 01XX
XC6C5C4 C3C2C1C0
Set Display Offset
0100 10XX
D7D6D5D4 D3D2D1D0
Set Multiplex Ratio
(Partial Display)
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Description
Set the lower nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
Set the upper nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
The internal regulator gain (1+R2/R1) Vout increases as
R2R1R0 is increased from 000b to 111b. The factor,
1+R2/R1, is given by:
R2R1R0 = 000: 3.45 (POR)
R2R1R0 = 001: 4.50
R2R1R0 = 010: 5.55
R2R1R0 = 011: 6.60
R2R1R0 = 100: 7.65
R2R1R0 = 101: 8.70
R2R1R0 = 110: 9.75
R2R1R0 = 111: 10.8
VC=0: turn OFF the internal voltage booster (POR)
VC=1: turn ON the internal voltage booster
VR=0: turn OFF the internal regulator (POR)
VR=1: turn ON the internal regulator
VF=0: turn OFF the output op-amp buffer (POR)
VF=1: turn ON the output op-amp buffer
The second command specifies the row address pointer
(0-127) of the RAM data to be displayed in COM0. This
command has no effect on ICONS. The pointer is set to 0
after reset.
The second command specifies the mapping of first
display line (COM0) to one of ROW0~127. This command
has no effect on ICONS. COM0 is mapped to ROW0 after
reset.
The second command specifies the number of lines,
excluding ICONS, to be displayed. With Icon is disabled
(POR), duties 1/16~1/128 could be selected. With Icon
enabled, the available duty ratios are 1/ 17~ 1/129.
Mux(icon disable) Mux(icon enable)
D7 – D0
0000000
invalid
invalid
…
00001111
invalid
invalid
00010000
16
17
00010001
17
18
…
10000000
128
129
10000001
invalid
invalid
10000010
invalid
invalid
…
11111111
invalid
invalid
SOLOMON
Bit Pattern
0100 11XX
XXXN4 N3N2N1N0
Command
Set N-line Inversion
0101 0B2B1B0
Set LCD Bias
0110 01B1B0
Set DC-DC Control
Register
1000 0001
XXC5C4 C3C2C1C0
1000 1000
Set Contrast Level
WB3WB2WB1WB0 WA3WA2WA1WA0
1000 1001
WD3WD2WD1WD0 WC3WC2WC1WC0
1000 1010
LB3LB2LB1LB0 LA3LA2LA1LA0
1000 1011
LD3LD2LD1LD0 LC3LC2LC1LC0
1000 1100
DB3DB2DB1DB0 DA3DA2DA1DA0
1000 1101
DD3DD2DD1DD0 DC3DC2DC1DC0
1000 1110
BB3BB2BB1BB0 BA3BA2BA1BA0
1000 1111
BD3BD2BD1BD0 BC3BC2BC1BC0
1001 0 FRC PWM1 PWM0
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Rev 1.0
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Set White Mode,
nd
st
Frame 2 & Frame 1
Set White Mode,
th
rd
Frame 4 , Frame 3
Set Light Gray Mode,
nd
st
Frame 2 & Frame 1
Set Light Gray Mode,
th
rd
Frame 4 & Frame 3
Set Dark Gray Mode,
nd
st
Frame 2 & Frame 1
Set Dark Gray Mode,
th
rd
Frame 4 & Frame 3
Set Dark Mode,
nd
st
Frame 2 & Frame 1
Set Dark Mode,
th
rd
Frame 4 & Frame 3
Set PWM and FRC
Description
The second command sets the n-line inversion register
from 3 to 33 lines to reduce display crosstalk. Register
values from 00001b to 11111b are mapped to 3 lines to 33
lines respectively. Value 00000b disables the N-line
inversion, which is the POR value.
To avoid a fix polarity at some lines, it should be noted that
the total number of mux (including the icon line) should
NOT be a multiple of the lines of inversion (n).
n-line inversion
N4 – N0
00000
Exit n-line inversion
00001
3 lines
00010
4 lines
…
11101
31 lines
11110
32 lines
11111
33 lines
Sets the LCD bias from 1/5 ~ 1/12 according to B2B1B0:
000: 1/5 bias
001: 1/6 bias
010: 1/7 bias
011: 1/8 bias
100: 1/9 bias
101: 1/10 bias
110: 1/11 bias
111: 1/12 bias (POR)
Set the DC-DC multiplying factor from 3X to 6X
B1B0:
00: 3X (POR)
01: 4X
10: 5X
11: 6X
The second command sets one of the 64 contrast levels.
The darkness increase as the contrast level increase.
Set gray scale mode and register. These are two-byte
commands used to specify the contrast levels for the gray
scale, 4 levels available.
After power on reset :
WA0~3 = WB0~3 = WC0~3 = WD0~3 = 0000
LA0~3 = LB0~3 = LC0~3 = LD0~3 = 0000
DA0~3 = DB0~3 = DC0~3 = DD0~3 = 1111
BA0~3 = BB0~3 = BC0~3 = BD0~3 = 1111
Memory Content
1st Byte
2nd Byte
0
0
1
1
0
1
0
1
Gray Scale Mode
White
Light Gray
Dark Gray
Dark
Set PWM and FRC for gray-scale operation.
FRC = 0 : 4-frame (POR)
FRC = 1 : 3-frame
PWM = 00 & 01 : 9-levels (POR)
PWM = 10 : 12-levels
PWM = 11 : 15-levels
20
SOLOMON
Bit Pattern
1010 000S0
Command
Set Segment Re-map
1010 001C0
Set Icon Enable
1010 010E0
Set Entire Display
On/Off
1010 011R0
Set Normal/Inverse
Display
1010 100P
Set Power Save Mode
1010 1011
Start Internal
Oscillator
1010 111D0
Set Display On/Off
1011 P3P2P1P0
Set Page Address
1100 S0XXX
1110 0000
1110 0001
1110 0010
Set COM Output Scan
Direction
Set Modify-read
Exit Power-save Mode
Software Reset
1110 0100
1110 1000
D7D6D5D4 D3D2D1D0
Exit N-line Inversion
Set Display Data
Length
1110 1110
Exit Modify-read
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Description
S0=0: column address 00H is mapped to SEG0 (POR)
S0=1: column address 7FH is mapped to SEG0
C0=0: Disable icon row (Mux = 16 to 128, POR)
C0=1: Enable icon row (Mux = 17 to 129) & set the page
address to 16.
E0=0: Normal display (display according to RAM contents,
POR)
E0=1: All pixels are ON regardless of the RAM contents
*Note: This command will override the effect of “Set
Normal/Invert Display”
R0=0: Normal display (display according to RAM contents,
POR)
R0=1: Invert display (ON and OFF pixels are inverted)
*Note: This command will not affect the display of the icon
lines
Enter sleep mode when P = 1. Normal mode when P=0.
Sleep Mode:
Oscillator: OFF
LCD Power Supply: OFF
COM/SEG Outputs: VSS
This command starts the internal oscillator. Note that the
oscillator is OFF after reset, so this instruction must be
executed for initialization
Turn the display on and off without modifying the content
of the RAM. (0: off, 1: on)
This command has priority over Entire Display On/Off and
Invert Display On/Off. Commands are accepted while the
display is off, but the visual state of the display does not
change.
Select the page of display RAM to be addressed. Pages 015 are valid.
Set the COM (row) scanning direction.
(0: COM0 →COM127, 1: COM127 →COM0)
Set modify-read mode
Return the driver/controller from the sleep mode.
Reset some functions of the driver/controller. See Reset
Section below for more details.
Release the driver/controller from N-line inversion mode.
This command is used in 3-line SPI mode (without D/C#
line) to specify that the controller is about to send display
data to the display RAM. Eight bits are used to specify the
number of bytes to be sent (1 to 256 bytes). The second
command received after the display data is transmitted is
assumed to be command data.
Release modify-read mode
SOLOMON
Table 4 – Extended Command Table
Bit Pattern
1111 0001
0000 1T2T1T0
Command
Set TC value
1111 1000
X0111 0000
Enable internal
oscillator resistor
1111 1011
0000 X0000
Enable Frame
Frequency setting
1111 1100
C1C000 0000
Set the COM Scan
Sequence
Description
This command set the Temperature Coefficient
T2T1T0:
000: -0.05%
001: -0.085%
010: -0.125% (POR)
011: -0.16%
100: -0.18%
101: -0.21%
110: -0.23%
111: -0.25%
This command enable/disable internal oscillator.
X0 = 0 : use external oscillator resistor
X0 = 1 : use internal oscillator resistor (520kΩ)
This command is used to enable the frame frequency
setting.
X0 = 0 : Disable Frame frequency Setting
X0 = 1 : Enable Frame Frequency Setting
This command is used to select the COM Scan Sequence
and Direction.
C1 C0
0 0
0 1
1 0
1 1
OTP setting and set
frame frequency
1000 0010
0 F2F1F0 X3X2X1X0
ROW : 0
1…..15 16...62 63 64
65..111 112..126 127
COM : 0
1…..15 16...62 63 64
65..111 112..126 127 (POR)
COM : 127 126..112 63..17 16 111 110..64
15…1
0
COM : 127 125..97
95.. 3
1 126 124..32
30…2
0
COM : 126 124..96
94..2
0 127 125..33
31…3
1
This command set the offset value of contrast and frame
frequency
X3X2X1X0
0000 : original contrast
0001 : original contrast + 1 step
0010 : original contrast + 2 steps
0011 : original contrast + 3 steps
0100 : original contrast + 4 steps
0101 : original contrast + 5 steps
0110 : original contrast + 6 steps
0111 : original contrast + 7 steps
1000 : original contrast - 8 steps
1001 : original contrast - 7 steps
1010 : original contrast - 6 steps
1011 : original contrast - 5 steps
1100 : original contrast - 4 steps
1101 : original contrast - 3 steps
1110 : original contrast - 2 steps
1111 : original contrast - 1 step
Frame Frequency
F2F1F0
000
90 (POR)
001
95
010
100
011
106
100
76
101
80
110
83
111
87
Remarks: Set frame frequency command is available when
enable the internal oscillator resistor and frame frequency
setting
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SOLOMON
Bit Pattern
1000 0011
Command
OTP programming
1111 0100
0000 0X010
1000 0100
0A6A5A4 A3A2A1A0
0000 B3B2B1B0
0C6C5C4 C3C2C1C0
0000 D3D2D1D0
Enable DMA mode
1111 1101
0001 0X010
Lock / Unlock
Interface
Set Start/End Column
and Page address in
DMA mode
Description
This command start program LCD driver with OTP offset
value. This command only execute once. No effect on the
second run. Detail of OTP programming procedure on
page 30.
This command enable /disable the Direct Memory Access
mode .
This command set the start column address (A6~A0), end
column address (C6~C0), start page address (B3~B0) and
end page address (D3~D0) in DMA mode. The page and
column address should be follow the below rule.
Max value
Min. value
0000000
C6~C0
A6~A0
0000
D3~D0
B3~B0
A6~A0
1111111
C6~C0
D3~D0
B3~B0
1111
Remarks: this command is available only when DMA mode
is enabled.
X0= 0 : Lock the IC. The driver ignores all command and
data written, except the unlock command or pin reset.
X0 = 1 : Unlock the IC. The driver accepts any command
and data written.
Read Status Byte (D/ C = 0, R/ W( WR ) = 1, E( RD ) = 1)
An 8 bits status byte will be placed onto the data bus when a read operation is performed if D/ C is low. The status
byte is defined as follows:
Bit Pattern
Command
Description
BUSY
BUSY ON RES MF2 MF1 MF0 DS1 Read Display Status
0: Chip is idle
DS0
1: Chip is executing instruction
ON
0: Display is OFF
1: Display is ON
RES
0: Chip is idle
1: Chip is executing reset
MF2- MF0 : 010
DS1, DS0 : Display size
Data Read / Write (D/ C = 1, R/ W( WR ) = 1, E( RD ) = 1)
To read data from the GDDRAM, input High to R/ W( WR ) pin and D/ C pin for 6800-series parallel mode,
Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In
normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a
dummy read is required before the first data is read. See Figure 3 in Functional Description.
To write data to the GDDRAM, input Low to R/ W( WR ) pin and High to D/ C pin for 6800-series parallel mode. For
serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one
automatically after each data write. The address will be reset to 0 in execution of next data read/write operation when
it is 127.
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SOLOMON
Address Increment Table (Automatic)
Comment
Address Increment
R/ W( WR )
D/ C
0
0
0
1
1
1
0
1
Write
Command
Read Status
Write Data
Read Data
No
No
Yes
Yes
Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is also
affected. It will be reset to 0 in next data read/write operation is executed when it is 127.
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24
SOLOMON
9
COMMAND DESCRIPTIONS
9.1
Set Lower Column Address
This command specifies the lower nibble of the 7-bit column address of the display data
RAM. The column address will be incremented by each data access after it is pre-set by the
MCU and returning to 0 once overflow (>127)
9.2
Set Upper Column Address
This command specifies the higher nibble of the 7-bit column address of the display data
RAM. The column address will be incremented by each set of data (LSB & MSB) access after it
is pre-set by the MCU and returning to 0 once overflow (>127).
9.3
Set Internal Regulator Resistor Ratio
This command is to enable any one of the eight internal resistor (INTRS) settings for
different regulator gains when using internal regulator resistor network (INTRS pin pulled high).
The Contrast Control Voltage Range curves are given in the Figure 6.
9.4
Set Power Control Register
This command turns on/off the various power circuits associated with the chip.
9.5
Set Display Start Line
This command is to set Display Start Line register and to determine starting address of
display RAM. When starting address equals to 0, D0 of Page 0 is mapped to COM0. When it is
equal to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 127 are
assigned to Page 0 to 15.
9.6
Set Display Offset
The second command specifies the mapping of display start line (COM0 if display start
line register equals to 0) to one of ROW0-127. This command has no effect on ICONS. COM0
is mapped to ROW0 after reset.
9.7
Set Multiplex Ratio
This command switches default 128 multiplex mode to any multiplex from 16 to 128, if
Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will
be mapped to 17 to 129. The chip pads ROW0-ROW127 will be switched to corresponding
COM signal output.
9.8
Set N-line Inversion
Number of line inversion is set by this command for reducing cross-talk noise. 3 to 33-line
inversion operations could be selected. At POR, this operation is disabled. It should be noted
that the total number of mux (including the icon line) should NOT be a multiple of the inversion
number (N). Or else, some lines will not change their polarity during frame change.
9.9
Set LCD Bias
This command is used to select a suitable bias ratio (1/5 to 1/12) required for driving the
particular LCD panel in use. The POR default 1/12 bias.
25
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SOLOMON
9.10 Set DC-DC Converter Factor
Internal DC-DC converter factor is set by this command. 3X to 6X multiplying factors
could be selected.
9.11 Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing VL6 of the LCD drive
voltage provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) contrast control
register. It is a compound commands.
9.12 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black)
Command 88(hex) to 8F(hex) are used to specify the four gray levels’ pulse width at the
four possible frames. The four gray levels are called white, light gray, dark gray and black. Each
level is defined by 4 registers for 4 consecutive frames. For example, WA is a 4-bit register to
st
nd
define the pulse width of the 1 frame in White mode. WB is a register for 2 frame in White
mode etc. Each command specifies two registers.
For 4 FRC,
Memory Content
st
nd
1 Byte
2
FRAME
Gray Mode
Byte
st
nd
rd
th
1
2
3
4
0
0
White
WA
WB
WC
WD
0
1
Light Gray
LA
LB
LC
LD
1
0
Dark Gray
DA
DB
DC
DD
1
1
Black
BA
BB
BC
BD
st
nd
For 3 FRC,
Memory Content
st
nd
1 Byte
2
FRAME
Gray Mode
Byte
rd
1
2
3
th
4 (No use)
0
0
White
WA
WB
WC
WD (XX)
0
1
Light Gray
LA
LB
LC
LD (XX)
1
0
Dark Gray
DA
DB
DC
DC (XX)
1
1
Black
BA
BB
BC
BC (XX)
Example for pure PWM mode:
No. of level
15-levels
12-levels
9-levels
LCD panel
display
MSB
LSB
MSB
RAM Content
LSB
MSB
LSB
MSB
LSB
Dark Mode
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
F,F,F,F
C,C,C,C
9,9,9,9
0
0
0
Gray Scale mode and Register (3/4 FRC)
Dark Gray
Light Gray
White Mode
Mode
Mode
A,A,A,A
5,5,5,5
0,0,0,0
8,8,8,8
4,4,4,4
0,0,0,0
6,6,6,6
3,3,3,3
0,0,0,0
Example for pure FRC mode:
No. of Frame
3-FRC
4-FRC
LCD panel
display
SSD1852
MSB
LSB
MSB
RAM Content
LSB
MSB
LSB
MSB
LSB
Dark Mode
1
1
1
1
1
1
0
0
1
1
0
0
0
0
F,F,F,F
F,F,F,F
Rev 1.0
01/2003
0
0
Gray Scale mode and Register (15PWM)
Dark Gray
Light Gray
White Mode
Mode
Mode
F,F,0,0
F,0,0,0
0,0,0,0
F,F,F,0
F,0,0,0
0,0,0,0
26
SOLOMON
9.13 Set PWM and FRC
This command is used to select the number of frames used in frame rate control, and the
number of levels in the pulse width modulation.
9.14 Set Segment Re-map
This command changes the mapping between the display data column address and
segment driver. It allows flexibility in layout during LCD module assembly. Refer to Figure 7.
9.15 Set Icon Enable
This command enable/disable the Icon display. When Icon display is enabled and page
address is set to Page 16. This is only one way to set the page address to 16. Therefore, when
writing data for the icon, ICONS control register ON instruction would be used to set the page
address to 16.
9.16 Set Entire Display On/Off
This command forces the entire display, including the icon row, to be “ON” regardless of
the contents of the display data RAM. This command has priority over normal/invert display. To
execute this command, Set Display On command must be sent in advance.
9.17 Set Normal/Inverse Display
This command sets the display to be either normal/inverse. In normal display, a RAM
data of 1 indicates an “ON” pixel. While in invert display, a RAM data of 0 indicates an “ON”
pixel. The icon line is not affected by this command.
9.18 Set Power Save Mode
This command is used to force the chip to enter Sleep Mode.
9.19 Start Internal Oscillator
After POR, the internal oscillator is OFF. It should be turned ON by sending this
command to the chip.
9.20 Set Display On/Off
This command turns the display on/off, by the value of the LSB.
9.21 Set Page Address
This command positions the page address to 0 to 15 possible positions in GDDRAM.
Refer to figure 7.
Set Page Address command cannot be used to set the page address to “16”. Use ICON
control register ON/OFF command to set the page address to “16”.
9.22 Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD
module assembly.
9.23 Set Modify-Read
This command stops the automatic increment of the column address after read display
data. The column address is still automatic increment due to write display data.
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9.24 Exit Power-save Mode
This command releases the chip from either Standby or Sleep Mode and return to normal
operation.
9.25 Software Reset
When the RESET instruction is issued, the following parameters are initialized:
Register
Default Value
Descriptions
Page address
0
Column address
0
Display Start Line
0
GDDRAM page 0,D0
Internal Resistor Ratio
0
Gain = 3.45(IR0)
Contrast
20H
Data display length
0
FRC, PWM Mode
0
4FRC, 9PWM
White Palette
(0, 0, 0, 0)
Light Gray Palette
(0, 0, 0, 0)
Dark Gray Palette
(9, 9, 9, 9)
Black Palette
(9, 9, 9, 9)
9.26 Exit N-line Inversion
This command releases the chip from N-line inversion mode. The driving waveform will
be inverted once per frame after issuing this command.
9.27 Set Display Data Length
This two-byte command only valid when 3-wire SPI configuration is set by H/W input
(PS0=PS1=L). The second 8-bit is used to a number of display data byte (1-256) to be
transmitted. The next byte after the display data string is handled as a command.
9.28 Exit Modify-read
This command releases the modify-read mode and the column address return to its initial
value (before the set modify-read mode is set).
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EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features, on top
of general ones, designed for the chip.
9.29 Set TC value
This command is to set 1 out of 8 different temperature coefficients in order to match
various liquid crystal temperature grades.
9.30 Enable internal oscillator resistor
This command is used to enable/disable the internal oscillator. The value of the internal
oscillator resistor is 520kΩ.
9.31 Enable Frame Frequency setting
This command is used to enable/disable set frame frequency. The frame frequency can
be tuned when enable internal oscillator resistor and frame frequency setting.
Enable internal oscillator resistor (0xF8; 0XF0)
Enable Frame Frequency setting (0xFB; 0X08)
Set the Frame Frequency (0x82; 0x00~0x70)
Accept the
frame
frequency?
NO
Yes
END
Figure 9 – Sequence for setting frame frequency
9.32 Set COM Scan Sequence
This command is used to select one of four sets of COM Scan sequence.
9.33 Set Frame Frequency setting
This command specifies the frame frequency so as to minimize the flickering due to the
ac main frequency. The frequency is set to 90Hz(typical) at 128 mux after enabled internal
oscillator resistor.
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9.34 OTP setting and programming
OTP (One Time Programming) is a method to adjust VL6. In order to eliminate the
variations of LCD module in term of contrast level, OTP can be used to achieve the best
contrast of every LCD modules.
OTP setting and programming should include two major steps of (1) Find the OTP offset and
(2) OTP programming as following,
Step 1. Find OTP offset
(1)
(2)
(3)
(4)
(5)
Hardware Reset (sending an active low reset pulse to RES pin)
Send original initialization routines
Set and display any test patterns
Adjust the contrast value (0x81, 0x00~0x3F) until there is the best visual contrast
OTP setting steps = Contrast value of the best visual contrast - Contrast value of original
initialization
Example 1:
Contrast value of original initialization = 0x20
Contrast value of the best original initialization = 0x24
OTP offset value = 0x24 - 0x20 = +4
OTP setting command should be (0x82, 0x04)
Example 2:
Contrast value of original initialization = 0x20
Contrast value of the best original initialization = 0x1B
OTP setting = 0x1B - 0x20 = -5
OTP setting command should be (0x82, 0x0B)
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SOLOMON
Step 2. OTP programming
(6) Hardware Reset (sending an active low reset pulse to RES pin)
(7) Enable Oscillator (0xAB) and Exit Sleep Mode (0xE1)
(8) Connect an external VL6 (see diagram below)
(9) Send OTP setting commands that we find in step 1 (0x82, 0x00~0x0F)
(10)Send OTP programming command (0x83)
(11)Wait at least 2 seconds
(12)Hardware Reset
Verify the result by repeating step 1. (2) – (3)
(8)
SSD1852
VL6
R
+ C
-
14.5-15.5V
GND
GND
(1) & (6) & (12)
RES
Note: R = 1K ~ 10k ohm
C = 1u ~ 4.7u F
Figure 10 – OTP programming circuitry
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Start
Step 2
Step 1
i) Hardware reset
ii) Enable oscillator
i) Hardware reset
ii) Send original initialization
routines
iii) Set and display any test
patterns
Connect an external
voltage (14.5~15.5V)
on VL6 pins
Adjust the
contrast level
to the best
visual level
Accept the
contrast level
on panel?
Yes
OTP setting steps =
Adjusted contrast
value – Original
contrast value
No
i) Send OTP setting
commands
ii) Send OTP programming
command
iii) Wait > 2 sec
iv) Hardware reset
i) Send original initialization
routines
ii) Set and display any test
patterns
iii) Inspect the contrast
END
Figure 11 – Flow chart of OTP programming Procedure
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OTP Example program
Find the OTP offset:
1.
2.
Hardware reset by sending an active low reset pulse to RES pin
COMMAND(0XAB);
\\Enable oscillator;
COMMAND(0X2F);
\\ turn on the internal voltage booster, internal regulator and output op-amp buffer; Select booster
level.
3.
COMMAND(0X48)
\\ Set Duty ratio
COMMAND(0X80)
\\ 128Mux
COMMAND(0X93)
\\ Set 15 PWM & 4FRC
COMMAND(0X88); COMMAND(0X00) \\ Set white mode
COMMAND(0X89); COMMAND(0X00)
COMMAND(0X8A); COMMAND(0X55) \\ Set light gray mode
COMMAND(0X8B); COMMAND(0X55)
COMMAND(0X8C); COMMAND(0XAA) \\ Set dark gray mode
COMMAND(0X8D); COMMAND(0XAA)
COMMAND(0X8E); COMMAND(0XFF) \\ Set dark mode
COMMAND(0X8F); COMMAND(0XFF)
4.
5.
6.
COMMAND(0X57)
\\ Set Biasing ratio (1/12 BIAS)
COMMAND(0X81)
\\Set target gain and contrast.
COMMAND(0X30)
\\ contrast = 48
COMMAND(0X27)
\\ IR7 => gain = 10.8
\\ Set target display contents
COMMAND(0XB0)
\\ set page address
COMMAND(0x00)
\\ set lower nibble column address
COMMAND(0X10)
\\ set higher nibble column address
DATA(…)
\\ write target content to GDDRAM
COMMAND(0XAF)
\\ Display ON
OTP offset calculation… target OTP offset value is +3
OTP programming:
7.
Hardware reset by sending an active low reset pulse to RES pin
8.
COMMAND(0XAB)
\\ Enable Oscillator
9.
COMMAND(0X82)
\\ Set OTP offset value to +3 (0011)
COMMAND(0X03)
\\ 0000 X3X2X1X0 , where X3X2X1X0 is the OTP offset value
10.
Connect a external VL6 (14.5V~15.5V)
11.
COMMAND(0X83)
12.
Wait at least 2 seconds for programming wait time.
\\ Send the OTP programming command.
Verify the result:
13.
33
After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel.
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9.35 Enable DMA mode
This command enables the DMA mode. The column address will be incremented by each
data access returning to pre-set start column address once overflow (> end column address).
The page address will be incremented by column address overflow. The start column address,
end column address, start page address and end page address should set to 0,127,0,15
respectively before disable DMA mode.
9.36 Set Start/End Column and Page address in DMA mode
This command set the column and page address parameter in DMA mode. The page
address and column address should set to start page address and start column address after
set start/end column and page address.
Enable DMA mode (F4H, 05H)
Set Start/End Column and Page address
e.g. 84H, 10H, 01H, 60H, 0CH
(start column address = 16, start page address = 1,
end column address = 96, end page address = 12)
Set page and column address
e.g. B1H, 11H, 00H
(page address = 1, column address = 16)
Available write the data to GDDRAM
Figure 12 - Sequence for setting the DMA mode.
Reset Start/End Column and Page address
e.g. 84H, 00H, 00H, 7FH, 0FH
(start column address = 0, start page address = 0,
end column address = 127, end page address = 15)
Disable DMA mode (F4H, 01H)
Figure 13 - Sequence for disable the DMA mode.
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9.37 Lock/Unlock Interface
After sending the lock command, the interface will be disabled until the unlock command
is received. The lock command is suggested whenever the LCD driver will not be accessed for
some period. This can minimize incorrect data or command written due to noisy interface.
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10 MAXIMUM RATINGS
Table 5 - Maximum Ratings (Voltage Reference to VSS)
Symbol
VDD
VCC
VCI
Vin
I
TA
Tstg
Parameter
Value
Supply voltage
Booster Supply Voltage
Input Voltage
Current Drain Per Pin Excluding VDD
and VSS
Operating Temperature
Storage Temperature Range
Unit
-0.3 to 4.0
-0.3 to 15
-0.3 to 4.0
-0.3 to VDD + 0.3
V
V
V
V
25
mA
-30 to +85
-40 to +85
o
o
C
C
* Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation should be restricted to the limits
in the Electrical Characteristics tables or Pin Description section.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions to be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it is
recommended that Vin and Vout be
constrained to the range VSS < or = (Vin or
VOUT) < or = VDD. Reliability of operation is
enhanced if unused input are connected to
an appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open. This device may be light sensitive.
Caution should be taken to avoid exposure of
this device to any light source during normal
operation. This device is not radiation
protected.
11 DC CHARACTERISTICS
Table 6 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V,
TA = -30 to +85°C)
Symbol
VDD
VCI
IAC
Parameter
Logic Circuit Supply Voltage
Range
Voltage Generator Circuit Supply
Voltage Range
Access Mode Supply Current
Drain (VDD & VCI Pins)
Test Condition
(Absolute value referenced to VSS)
VDD = 2.7V, Voltage Generator On,
6X Converter Endabled,
Write accessing, Tcyc = 3.3MHz,
Osc. Freq.=200kHz, Display On.
Min
Typ
Max
Unit
1.8
2.7
3.3
V
VDD
2.7
3.3
V
1
1.2
2
mA
150
300
400
µA
IDP1
Display Mode Supply Current
Drain (VDD & VCI Pins)
VDD = 2.7V, VCC = 16.2V,
Voltage Generator On,
6X Converter Endabled, Divider
Enabled, Read/Write Halt,
Osc. Freq.=155kHz, Display On,
VL6=13V (w/o panel loading)
IDP2
Display Mode Supply Current
Drain (VDD Pins)
VDD = 2.7V, External VL6 = 13V,
Voltage Generator Off, Divider
Enabled, Read/Write Halt,
Osc. Freq.=155kHz, Display On, VL6
= 13V.
10
15
30
µA
Standby Mode Supply Current
Drain (VDD Pins)
VDD = 2.7V, LCD Driving Waveform
Off, Osc. Freq. 155KHz, Read/Write
halt.
5
15
40
µA
Sleep Mode Supply Current Drain
(VDD Pins)
LCD Driving Voltage Generator
Output (VCC Pin)
VDD = 2.7V, LCD Driving Waveform
Off, Oscillator Off, Read/Write halt.
Display On, Voltage Generator
Enabled, DC/DC Converter Enabled,
Osc. Freq. = 155KHz, Regulator
Enabled, Divider Enabled.
0
0.1
1
µA
5.4
16.2
18
V
DC-DC Converter Efficiency
ICC < 80uA
95
98
100
%
LCD Driving Voltage Input (VCCPin)
Voltage Generator Disabled.
-
15
V
ISB
ISLEEP
VCC
VLCD
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Symbol
VREF
Test Condition
Internal Reference Voltage Source
Disable (REF pin pulled Low),
External Reference voltage input to
VEXT pin [VREF = VEXT *(1.4/2.1)].
Internal Reference Voltage
Min
Typ
Max
Unit
2.06
2.1
2.14
V
1.32
1.33
1.37
1.35
1.34
1.36
1.36
1.38
0.8*VDD
1.35
1.36
1.40
1.38
1.37
1.39
1.39
1.41
-
1.38
1.39
1.43
1.41
1.40
1.42
1.42
1.44
VDD
V
V
V
V
V
V
V
VOH1
Output High voltage (D0-D7)
Internal Reference Voltage Source
Enabled (REF pin pulled High), VEXT
pin NC; (TA=25oC)
TC0 = -0.05%/oC
TC1 = -0.085%/oC
TC2 = -0.125%/oC (POR)
TC3 = -0.16%/oC
TC4 = -0.18%/oC
TC5 = -0.21%/oC
TC6 = -0.23%/oC
TC7 = -0.25%/oC
Iout = +500µA
VOL1
Output Low Voltage (D0-D7)
Iout = -500µA
0.0
-
0.2*VDD
V
VL6
LCD Driving Voltage Source (VL6
Pin)
Regulator Enabled (VL6 voltage
depends on Int/Ext Contrast Control)
VDD
-
VCC-0.5
V
VL6
LCD Driving Voltage Source (VL6
Pin)
Input high voltage
(RES#, PS0, PS1, CS, D/C#,
R/W#, D0-D7, REF, INTRS)
Input Low voltage
(RES#, PS0, PS1, CS, D/C#, R/W,
D0-D7, REF, INTRS)
LCD Display Voltage Output
(VL6, VL5, VL4, VL3, VL2 Pins)
Regulator Disable
-
Floating
-
V
0.8*VDD
-
VDD
V
0.0
-
0.2*VDD
V
Bias Divider Enabled, 1:a bias ratio,
a=5~12 .
-
VL6
(a-1)/a*VL6
(a-2)/a*VL6
2/a*VL6
1/a*VL6
-
V
V
V
V
V
VL5
VL4
VL3
VL2
VSS
50
-
VCC
VL6
VL5
VL4
VL3
-
V
V
V
V
V
µA
-
-
-50
µA
-1
-
1
µA
1
µA
5
7.5
pF
-
+2%
%
VIH1
VIL1
VL6
VL5
VL4
VL3
VL2
VL6
VL5
VL4
VL3
VL2
IOH
LCD Display Voltage Input
(VL6, VL5, VL4, VL3, VL2 Pins)
Voltage reference to VSS, External
Voltage Generator, Type A and Type
B Bias Divider Disabled
Output High Current Source(D0-D7)
Output Voltage = VDD-0.4V
IOL
Output Low Current Drain (D0-D7)
Output Voltage = 0.4V
IOZ
Output Tri-state Current Drain
Source (D0-D7)
Input Current
(RES#, PS0, PS1,CS#, E(RD#),
D/C#,R/W#(WR#), D0~D7, REF,
INTRS)
Input Capacitance
(all logic pins)
IIL/IIH
CIN
∆VL6
37
Parameter
External Reference Voltage Input
SSD1852
Variation of VL6 Output (1.8V <
VDD < 3.3V)
Rev 1.0
01/2003
-1
Regulator Enabled, Internal Contrast
Control Enabled, Set Contrast
Control Register = 0
-2%
SOLOMON
V
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Temperature Coefficient
Compensation
Flat Temperature Coefficient
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
Temperature Coefficient 1*
Temperature Coefficient 2* [POR]
Temperature Coefficient 3*
Temperature Coefficient 4*
Temperature Coefficient 5*
Temperature Coefficient 6*
Temperature Coefficient 7*
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
0
-0.075
-0.115
-0.15
-0.175
-0.20
-0.22
-0.24
-0.05
-0.085
-0.125
-0.16
-0.18
-0.21
-0.23
-0.25
-0.06
-0.095
-0.135
-0.175
-0.19
-0.22
-0.24
-0.26
*The formula for the temperature coefficient is:
0
TC (% / C ) =
SSD1852
V ref at 50 0 C − V ref at 0 0 C
0
0
50 C − 0 C
Rev 1.0
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*
1
*100%
V ref at 25 0 C
38
SOLOMON
%/oC
%/oC
%/oC
%/oC
%/oC
%/oC
%/oC
%/oC
12 AC CHARACTERISTICS
Table 7 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V,
TA = 25°C)
Symbol
FOSC
FFRM
Parameter
Oscillation Frequency of Display
Timing Generator
Frame Frequency
Test Condition
Internal Oscillator Enabled
Set 128 x 128, Icon Line
Disabled, 15 PWM, oscillator
resistor = 680kΩ,
VDD=2.775V
Internal Oscillator resistor
Enabled, set 128 x 128, Icon
Line Disabled, 15 PWM,
VDD=2.775V, Frame frequency
setting (F2F1F0=000)
Display ON, Set 128 x 128
Graphic Display Mode, Icon
Line Disabled, 15 PWM,
oscillator resistor = 680kΩ,
VDD=2.775V
Display ON, Set 128 x 128
Graphic Display Mode, Icon
Line Disabled, 15 PWM,
Internal oscillator resistor
enabled, VDD=2.775V, Frame
frequency setting
(F2F1F0=000)
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Min
129.6
Typ
144
Max
158.4
Unit
KHz
147
175.5
199
KHz
67.5
75
82.5
Hz
76.5
90
103.5
Hz
SOLOMON
The formula for the Frame Frequency is:
FFRM =
FOSC
Mux * PWM *
* PWM is the number of levels of pulse width modulation.
Remarks: FOSC will be fine tuned automatically, while change Mux ratio. Therefore, the frame frequency
always within +/- 10Hz of the target frame frequency.
Frame Frequency Vs Oscillator Resistor
400
350
300
Freq [Hz]
250
200
150
100
50
0
0
100
200
300
400
500
600
700
800
900
1000
Resistor [k ohm]
o
Figure 14 Relationship between Frame Frequency and Oscillator resistor (TA=25 C, VDD=2.775V)
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Table 8 – 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 1.8, TA = -30 to
+85°C)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
200
0
0
40
10
10
15
500
500
100
200
100
-
Typ
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tAH
R/W
E
tcycle
PW CSL
CS
tF
tR
tDHW
tDSW
D0~D7(WRITE)
PW CSH
Valid Data
tACC
D0~D7(READ)
tDHR
Valid Data
tOH
Figure 15 – 6800-Series MPU Parallel Interface Characteristics (PS0=H; PS1=H)
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Table 9 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.7V, TA = -30 to
+85°C)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
100
0
0
30
5
10
15
250
250
50
100
50
-
Typ
500
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAH
tAS
WR
RD
tcycle
PW CSH
PW CSL
CS
tR
tDHW
tF
tDSW
D0~D7(WRITE)
Valid Data
tDHR
tACC
D0~D7(READ)
Valid Data
tOH
Figure 16 – 8080-Series MPU Parallel Interface Characteristics (PS0 = H, PS1 = L)
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Table 10 – 3-wires Serial Interface Timing Characteristics (VDD - VSS = 1.8V, TA = -30 to +85°C)
Symbol
tcycle
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Min
111
60
55.5
60
60
55.5
55.5
-
Clock Cycle Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
tCSS
CS
Max
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSH
tcycle
tCLKL
SCK(D6)
Typ
-
tCLKH
tR
tF
tDSW
SDA(D7)
tDHW
Valid Data
CS
SCK(D6)
SDA(D7)
D7
D6
D5
D4
Column
LSB
DDC
D3
D2
D1
D0
CS
SCK(D6)
SDA(D7)
Page
Column
MSB
No. of
DATA(n)
DATA0
DATAn
Command
Figure 17 – 3-wires Serial Interface Characteristics (PS0 = L, PS1 = L)
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Table 11 – 4-wires Serial Interface Timing Characteristics (VDD - VSS = 2.7V, TA = -30 to +85°C)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Min
58.8
10
5
30
29.4
30
30
29.4
29.4
-
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Typ
-
Max
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tAH
tCSS
CS
tCSH
tcycle
tCLKL
SCK(D6)
tF
tCLKH
tR
tDSW
SDA(D7)
tDHW
Valid Data
CS
SCK(D6)
SDA(D7)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 18 – 4-wire Serial Interface Timing Characteristics (PS0 = L, PS1 = H)
SSD1852
Rev 1.0
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13 APPLICATION EXAMPLES
ICONS
COM0
:
:
:
:
COM62
COM63
DISPLAY PANEL SIZE
128 X 128 + 1 ICON LINE
SEG0………………………………………….………….SEG127
Remapped COM
SCAN Direction
[Command: C8
C1….C5
:
:
:
:
ROW65
ROW64
C12
C11
C7
C6
C9
……
ROSC
VDD
C8
C10
VSS
Vcc
E
VSS
R/ W
D7
D/ C
VCI
VDD
RES
D0
CS
VL6
…..
:
:
VL2
C4P
C2N
C2P
C1P
C1N
C3P
C5P
Vcc
E
VSS
R/ W
VCI
VDD
D7
D/ C
:
RES
:
ROW60
ROW63
OSC1
128 MUX
(DIE FACE UP)
CS
:
:
:
:
:
:
SSD1852 IC
Remapped COM
SCAN Direction
[Command: C8
:
:
:
:
ROW0
ICONS
SEG127………………………………………………………………………SEG0
:
:
:
:
:
:
:
ROW127
ICONS
Remapped COM
SCAN Direction
[Command: C8]
Segment Remapped
[Command: A1)
D0
Remapped COM
SCAN Direction
[Command: C8
COM64
COM65
:
:
:
:
COM127
Remarks: For noise protection, the wiring
length form OSC1 to Rosc should be minimize
& shielding.
where VDD&VCI=2.775V,
C1~C5 = 0.47uF~2.0uF,
C6~C12 = 1uF~4.7uF,
ROSC = 680KΩ
Logic pin connections not specified above:
Pins connected to VDD: PS0;PS1;REF; INTRS
Pins connected to VSS: TEST_IN0
Figure 19 - Typical Application
45
SSD1852
Rev 1.0
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SOLOMON
14 APPENDIX
14.1 TAB Drawing
Figure 20 – SSD1852T TAB Drawing 1
SSD1852
Rev 1.0
01/2003
46
SOLOMON
Figure 21 – SSD1852T TAB Drawing 2
47
SSD1852
Rev 1.0
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SOLOMON
N
O
M
SS
D
18
52
T2
LO
SO
Figure 22 – SSD1852T2 TAB Drawing 1
SSD1852
Rev 1.0
01/2003
48
SOLOMON
Figure 23 – SSD1852T2 TAB Drawing 2
49
SSD1852
Rev 1.0
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SOLOMON
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for
each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of
others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.
SSD1852
Rev 1.0
01/2003
50
SOLOMON