ETC UT1553BRTR-GXC

UT1553B RTR Remote Terminal with RAM
FEATURES
❐ Complete MIL-STD-1553B remote terminal interface
❐ 1K x 16 of on-chip static RAM for message data,
completely accessible to host
❐ Self-test capability, including continuous loop-back
❐
❐
❐
❐
MCSA(4:0)
MODE CODE/
SUBADDRESS
OUT
IN
OUT
IN
OUTPUT MULTIPLEXING AND
SELF-TEST WRAPAROUND LOGIC
❐
compare
Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress
RT-RT Terminal Address Compare
Command word stored with incoming data for
enhanced data management
User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
❐
Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
Available in 68-pin pingrid array package
INTRODUCTION
The UT1553B RTR is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface. Designed to reduce cost and space, the RTR
integrates the remote terminal logic with a user-configured
1K x 16 static RAM. In addition, the RTR has a flexible
subsystem interface to permit use with most processors or
controllers.
The RTR provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTR’s memory
meets all of MIL-STD-1553B message storage needs
through user-defined memory mapping. This memorymapped architecture allows multiple message buffering at
RTA(4:0)
REMOTE TERMINAL
ADDRESS
CONTROL
INPUTS
STATUS
OUTPUTS
COMMAND
RECOGNITION
DECODER
CONTROL AND
ERROR LOGIC
1K X 16 RAM
DECODER
ADDR(9:0)
MUX
PTR REGISTER
ENCODER
12MHz
DATA(15:0)
2MHz
RESET
Figure 1. UT1553B RTR Functional Block Diagram
RTR-1
Table of Contents
RTR-2
1.0
ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 RTR RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . . .9
1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.0
MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.0
PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . 19
5.0
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0
AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.0
PACKAGE OUTLINE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.0 ARCHITECTURE AND OPERATION
The UT1553B RTR is an interface device linking a MILSTD-1553 serial data bus and a host microprocessor system.
The RTR’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition, 1K
x 16 of SRAM, pointer registers, clock, and reset circuits.
1.1 Memory Map and Host Memory Interface
The host can access the 1K x 16 RAM memory like a
standard RAM device through the 10-bit address and 16-bit
data buses. The host uses the Chip Select (CS), Read/Write
(RD/WR), and Output Enable (OE) signals to control data
transfer to and from memory. When the RTR requires access
to its own internal RAM, it asserts the RBUSY signal to
alert the host. The RBUSY signal is programmable via the
internal Control Register to be asserted either 5.7ms or
2.7ms prior to the RTR needing access to its internal RAM.
The RTR stores MIL-STD-1553B messages in 1K x 16 of
on-chip RAM. For efficient use of the 1K x 16 memory on
the RTR, the host programs a set of pointers to map where
the 1553B message is stored. The RTR uses the upper 64
words (address 3C0 (hex) through 3FF (hex)) as pointers.
The RTR provides pointers for all 30 receive subaddresses,
all 30 transmit subaddresses, and four mode code
commands with associated data words as defined in MILSTD-1553B. The remaining 960 words of memory
contain receive, transmit, and mode code data in a
host-defined structure.
RTR Memory Map
000 (hex)
Message
Storage
Locations
3BF(hex)
15 MSB
0 LSB
XMIT VECTOR WORD MODE CODE (W/DATA)
Receive
Message
Pointers
3C0 (hex)
3C1 (hex)
RCV SUBADDRESS 01
(3C1 TO 3DE)
RCV SUBADDRESS 30
SYNCHRONIZE MODE CODE (W/DATA)
15 MSB
3DE (hex)
3DF (hex)
0 LSB
XMIT LAST COMMAND MODE CODE (W/DATA)
XMT SUBADDRESS 01
Transmit
Message
Pointers
3E0 (hex)
3E1 (hex)
(3E1 TO 3FE)
XMT SUBADDRESS 30
XMT BIT WORD MODE CODE (W/DATA)
15 MSB
3FE (hex)
3FF (hex)
0 LSB
Figure 2. RTR Memory Map
RTR-3
MESSAGE INDEX
15 (MSB)
MESSAGE DATA ADDRESSES
10
9
0 (LSB)
Message Data Address:
Indicates the starting memory address for incoming
message storage.
Message index: Defines the
maximum messages buffered for
the given subaddresses.
Figure 3. Message Pointer Structure
1.2 RTR RAM Pointer Structure
The RAM 16-bit pointers have a 6-bit index field and a
10-bit address field. The 6-bit index field allows for the
storage of up to 64 messages per subaddress. A message
consists of the 1553 command word and its associated data
words.
The 16-bit pointer for Transmit Last Command Mode Code
is located at memory location 3E0 (hex). The Transmit Last
Command Mode Code pointer buffers up to 63 command
words. An example of command word storage follows:
Example:
3E0 (hex)
Contents = FC00 (hex)
11 1111 00 0000 0000
Address Field = 000 (hex)
Index Field = 3F (hex)
First command word storage location (3E0=F801):
Address Field = 001 (hex)
Index Field = 3E (hex)
Sixty-third command word storage location (3E0=003F):
Address Field = 03F (hex)
Index Field = 00 (hex)
Sixty-fourth command word storage location (3E0=003F)
(previous command word overwritten):
RTR-4
Address Field = 03F (hex)
Index Field = 00 (hex)
The Transmit Last Command Mode Code has Address Field
boundary conditions for the location of command word
buffers. The host can allocate a maximum 63 sequential
locations following the Address Field starting address. For
proper operation, the Address Field must start on an I x 40
(hex) address boundary, where I is greater than or equal to
zero and less than or equal to 14. A list of valid Index and
Address Fields follows:
I
Valid Index Fields
Valid Address Fields
0
3F (hex) to 00 (hex)
000 (hex) to 03F (hex)
1
3F (hex) to 00 (hex)
040 (hex) to 07F (hex)
2
3F (hex) to 00 (hex)
080 (hex) to 0BF (hex)
3
3F (hex) to 00 (hex)
0C0 (hex) to 0FF (hex)
4
3F (hex) to 00 (hex)
100 (hex) to 13F (hex)
5
3F (hex) to 00 (hex)
140 (hex) to 17F (hex)
6
3F (hex) to 00 (hex)
180 (hex) to 1BF (hex)
7
3F (hex) to 00 (hex)
1C0 (hex) to 1FF (hex)
8
3F (hex) to 00 (hex)
200 (hex) to 23F (hex)
9
3F (hex) to 00 (hex)
240 (hex) to 27F (hex)
10 3F (hex) to 00 (hex)
280 (hex) to 2BF (hex)
11 3F (hex) to 00 (hex)
2C0 (hex) to 2FF (hex
12 3F (hex) to 00 (hex)
300 (hex) to 33F (hex)
13 3F (hex) to 00 (hex)
340 (hex) to 37F (hex)
14 3F (hex) to 00 (hex)
380 (hex) to 3BF (hex)
Subaddress/Mode Code
RAM Location
Subaddress/Mode Code
RAM Location
Transmit Vector Word Mode Code
Receive Subaddress
01
Receive Subaddress
02
Receive Subaddress
03
Receive Subaddress
04
Receive Subaddress
05
Receive Subaddress
06
Receive Subaddress
07
Receive Subaddress
08
Receive Subaddress
09
Receive Subaddress
10
Receive Subaddress
11
Receive Subaddress
12
Receive Subaddress
13
Receive Subaddress
14
Receive Subaddress
15
Receive Subaddress
16
Receive Subaddress
17
Receive Subaddress
18
Receive Subaddress
19
Receive Subaddress
20
Receive Subaddress
21
Receive Subaddress
22
Receive Subaddress
23
Receive Subaddress
24
Receive Subaddress
25
Receive Subaddress
26
Receive Subaddress
27
Receive Subaddress
28
Receive Subaddress
29
Receive Subaddress
30
Synchronize w/Data Word Mode Code
3C0 (hex)
3C1 (hex)
3C2 (hex)
3C3 (hex)
3C4 (hex)
3C5 (hex)
3C6 (hex)
3C7 (hex)
3C8 (hex)
3C9 (hex)
3CA (hex)
3CB (hex)
3CC (hex)
3CD (hex)
3CE (hex)
3CF (hex)
3D0 (hex)
3D1 (hex)
3D2 (hex)
3D3 (hex)
3D4 (hex)
3D5 (hex)
3D6 (hex)
3D7 (hex)
3D8 (hex)
3D9 (hex)
3DA (hex)
3DB (hex)
3DC (hex)
3DD (hex)
3DE (hex)
3DF (hex)
Transmit Last Command Mode Code
Transmit Subaddress
01
Transmit Subaddress
02
Transmit Subaddress
03
Transmit Subaddress
04
Transmit Subaddress
05
Transmit Subaddress
06
Transmit Subaddress
07
Transmit Subaddress
08
Transmit Subaddress
09
Transmit Subaddress
10
Transmit Subaddress
11
Transmit Subaddress
12
Transmit Subaddress
13
Transmit Subaddress
14
Transmit Subaddress
15
Transmit Subaddress
16
Transmit Subaddress
17
Transmit Subaddress
18
Transmit Subaddress
19
Transmit Subaddress
20
Transmit Subaddress
21
Transmit Subaddress
22
Transmit Subaddress
23
Transmit Subaddress
24
Transmit Subaddress
25
Transmit Subaddress
26
Transmit Subaddress
27
Transmit Subaddress
28
Transmit Subaddress
29
Transmit Subaddress
30
Transmit Bit Word Mode Code
3E0 (hex)
3E1 (hex)
3E2 (hex)
3E3 (hex)
3E4 (hex)
3E5 (hex)
3E6 (hex)
3E7 (hex)
3E8 (hex)
3E9 (hex)
3EA (hex)
3EB (hex)
3EC (hex)
3ED (hex)
3EE (hex)
3EF (hex)
3F0 (hex)
3F1 (hex)
3F2 (hex)
3F3 (hex)
3F4 (hex)
3F5 (hex)
3F6 (hex)
3F7 (hex)
3F8 (hex)
3F9 (hex)
3FA (hex)
3FB (hex)
3FC (hex)
3FD (hex)
3FE (hex)
3FF (hex)
1.3 Internal Registers
The RTR uses two internal registers to allow the host to
control the RTR operation and monitor its status. The host
uses the Control (CTRL) signal along with Chip Select (CS),
Read/Write (RD/WR), and Output Enable (OE) to read the
16-bit Status Register or write to the 11-bit Control Register.
No address data is needed to select a register.
The Control Register toggles bits in the MIL-STD-1553B
status word, enables the biphase inputs, recognizes
broadcast commands, determines RAM Busy (RBUSY)
timing, selects terminal active flag, and puts the part in selftest mode. The Status Register supplies operational status
of the UT1553B RTR to the host. These registers must be
initialized before attempting RTR operation. Internal
registers can be accessed while RBUSY is active.
RTR-5
Control Register (Write Only)
The 11-bit write-only Control Register manages the operation of the RTR. Write to the Control Register by applying a logic
one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).
Control register write must occur 50ns before the rising edge of COMSTR to latch data into outgoing status word.
Bit
Number
Initial
Condition
Description
Bit 0
[1]
Channel A Enable. A logic 1 enables Channel A biphase inputs.
Bit 1
[1]
Channel B Enable. A logic 1 enables Channel B biphase inputs.
Bit 2
[0]
Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.
Bit 3
[1]
System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTR access to the
memory. No data words can be retrieved or stored; command words will be stored.
Bit 4
[0]
Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.
Bit 5
[0]
Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects
Channel A and a logic 0 selects Channel B.
Bit 6
[0]
Self-Test Enable. A logic 1 places the RTR in the internal self-test mode and inhibits normal
operation. Channels A and B should be disabled if self-test is chosen.
Bit 7
[0]
Service Request. A logic 1 sets the Service Request bit of the Status Word.
Bit 8
[0]
Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.
Bit 9
[1]
Broadcast Enable. A logic 1 enables the RTR to recognize broadcast commands.
Bit 10
[X]
Don’t care.
Bit 11
[X]
Don’t care.
Bit 12
[1]
RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs
RBUSY alert.
[] - Values in parentheses indicate the initialized values of these bits.
CONTROL REGISTER (WRITE ONLY):
X
X
X
RBUSY
TS
[1]
X
X
BCEN
INS
SRQ
ITST
ITCS
[1]
[0]
[0]
[0]
[0]
MSB
[0]
[1]
TF
[0]
CH B
EN
[1]
CH A
EN
[1]
LSB
[ ] defines reset state
X don’t care
Figure 4a. Control Register
RTR-6
SUBS BUSY
Status Register (Read Only)
The 16-bit read-only Status Register provides the RTR system status. Read the Status Register by applying a logic
0 to CTRL, CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data
I/O pins DATA(15:0).
Bit
Number
Initial
Condition
Description
Bit 0
[0]
MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.
Bit 1
[0]
MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 2
[0]
MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 3
[0]
MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 4
[0]
MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 5
[0]
MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the transmit or
receive command. A logic 0 indicates that bits 4 through 0 are a mode code, and that the
last command was a mode command.
Bit 6
[1]
Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a
logic 0 indicates that it arrived on Channel B.
Bit 7
[1]
Channel B Enabled. A logic 1 indicates that Channel B is available for both
Bit 8
[1]
Channel A Enabled. A logic 1 indicates that Channel A is available for both reception
and transmission.
Bit 9
[1]
Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not Bus Controller, via the above mode code, is overriding the host system’s ability to set the Terminal
Flag bit of the status word.
Bit 10
[1]
Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in
the Control Register is reset.
Bit 11
[0]
Self-Test. A logic 1 indicates that the chip is in the internal self-test mode.
Bit 12
[0]
TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it Error bit being
set to a logic one, and Channels A and B become disabled.
Bit 13
[0]
Message Error. A logic 1 indicates that a message error has occurred since has been
examined. Message error condition must be removed before reading the Status Register
to reset the Message Error bit.
Bit 14
[0]
Valid Message. A logic 1 indicates that a valid message has been received
Bit 15
[0]
Terminal Active. A logic 1 indicates the device is executing a transmit or
[] - Values in parentheses indicate the initialized values of these bits.
STATUS REGISTER (READ ONLY):
TERM VAL MESS TAPA SELF BUSY TFEN CH A CH B CHNL MC/ MCSA MCSA MCSA MCSA MCSA
ACTV MESS ERR ERR TEST
EN
EN
A/B SA
4
3
2
1
0
[0]
[0]
[0]
[0]
[0]
[1]
[1]
[1]
[1]
[1]
[0]
[0]
[0]
[0]
[0]
[0]
LSB
MSB
[] defines reset state
Figure 4b. Status Register
RTR-7
1.4 Mode Code and Subaddress
The UT1553B RTR provides subaddress and mode code
decoding meeting MIL-STD-1553B. In addition, the device
has automatic internal illegal command decoding for
reserved MIL-STD-1553B mode codes. Upon command
word validation and decode, status pins MCSA(4:0) and
MC/SA become valid. Status pin MC/SA will indicate
whether the data on pins MCSA(4:0) is mode code or
subaddress information. Status Register bits 0 through 5
contain the same information as pins MCSA(4:0) and MC/
SA.
The system designer can use signals MCSA(4:0), MC/SA,
BRDCST, RTRT, etc. to illegalize mode codes,
subaddresses, and other message formats (broadcast and
RT-to-RT) via the Illegal Command (ILLCOM) input to the
part (see figure 21 on page 31).
RTR MODE CODE HANDLING PROCEDURE
T/R
Mode Code
Function
0
10100
Selected Transmitter Shutdown 2
0
10101
Override Selected Transmitter Shutdown 2
0
10001
Synchronize (w/Data)
1
00000
Dynamic Bus Control 2
1
00001
Synchronize 1
1
00010
Transmit Status Word 3
1
00011
Initiate Self-Test 1
1
00100
Transmitter Shutdown
1
00101
Override Transmitter Shutdown
1
00110
Inhibit Terminal Flag Bit
1
00111
Override Inhibit Terminal Flag
1
01000
Reset Remote Terminal 1
1
10010
Transmit Last Command Word3
1
10000
Transmit Vector Word
1
10011
Transmit BIT Word
Operation
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
1. Command word stored
2. Data word stored
3. Status word transmitted
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
1. Command word stored
2. Status word transmitted
1. Command word stored
2. Status word transmitted
1. Command word stored
2. Status word transmitted
1. Command word stored
2. Alternate bus shutdown
3. Status word transmitted
1. Command word stored
2. Alternate bus enabled
3. Status word transmitted
1. Command word stored
2. Terminal Flag bit set to zero and disabled
3. Status word transmitted
1. Command word stored
2. Terminal Flag bit enabled, but not
set to logic one
3. Status word transmitted
1. Command word stored
2. Status word transmitted
1. Command word transmitted
2. Last command word transmitted
1. Command word stored
2. Status word transmitted
3. Data word transmitted
1. Command word stored
2. Status word transmitted
3. Data word transmitted
Notes:
1. Further host interaction required for mode code operation
2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one).
3. Status word not affected.
4. Undefined mode codes are treated as reserved mode codes.
RTR-8
1.5 MIL-STD-1553B Subaddress and Mode Code Definitions
Table 1: Subaddress and Mode Code Definitions Per MIL-STD-1553B
Message Format
Subaddress Field
Binary (Decimal)
00000 (00)
00001 (01)
00010 (02)
00011 (03)
00100 (04)
00101 (05)
00110 (06)
00111 (07)
01000 (08)
01001 (09)
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)
10100 (20)
10101 (21)
10110 (22)
10111 (23)
11000 (24)
11001 (25
11010 (26)
11011 (27)
11100 (28)
11101 (29)
11110 (30)
11111 (31)
Receive
Transmit
1
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1
Description
Mode Code Indicator
Mode Code Indicator
Notes:
1. Refer to mode code assignments per MIL-STD-1553B
1.6 Terminal Address
The Terminal Address of the RTR is programmed via five
input pins: RTA(4:0) and RTPTY. Asserting MRST latches
the RTR’s Terminal Address from pins RTA(4:0) and parity
bit RTPTY. The address and parity cannot change until the
next assertion of the MRST. The parity of the Terminal
Address is odd; input pin RTPTY is set to a logic state to
satisfy this requirement. A logic 1 on Status Register bit 12
indicates incorrect Terminal Address parity. An
example follows:
RTA(4:0) = 05 (hex) = 00101
RTPTY = 1 (hex) = 1
Sum of 1’s = 3 (odd), Status Register bit 12 = 0
RTA(4:0) = 04 (hex) = 00100
RTPTY = 0 (hex) = 0
Sum of 1’s = 1 (odd), Status Register bit 12 = 0
RTR-9
RTA(4:0) = 04 (hex) = 00100
RTPTY = 1 (hex) = 1
Sum of 1’s = 2 (even), Status Register bit 12 = 1
The RTR checks the Terminal Address and parity on Master
Reset. With Broadcast disabled, RTA (4:0) = 11111 operates
as a normal RT address.
1.7 Internal Self-Test
Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The self-test
capability of the RTR is based on the fact that the MIL-STD1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTR will recognize the
incoming status word as a command word and thus cause
the RTR to transmit another status word. After the host
invokes self-test, the RTR self-test logic forces a status word
transmission even though the RTR has not received a valid
command. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
self-test is controlled by the host periodically changing the
bit patterns in the status word being transmitted. Writing to
the Control Register bits 2, 3, 4, 7, and 8 changes the status
word. Monitor the self-test by sampling either the Status
Register or the external status pins (i.e., Command Strobe
(COMSTR), Transmit/Receive (T/R)). For more detailed
explanation of internal self-test, consult UTMC publication
RTR/RTS Internal Self-Test Routine.
1.8 Power-up and Master Reset
After power-up, reset initializes the part with its biphase
ports enabled, latches the Terminal Address, and turns on
the busy option. The device is ready to accept commands
from the MIL-STD-1553B bus. The busy flag is asserted
while the host is loading the message pointers and messages.
After this task is completed, the host removes the busy
condition via a Control Register write to the RTR. On
RTR-10
power-up if the terminal address parity (odd) is incorrect,
the biphase inputs are disabled and the message error pin
(MERR) is asserted. This condition can also be monitored
via bit 12 of the Status Register. The MERR pin is negated
on reception of first valid command.
1.9 Encoder and Decoder
The RTR interfaces directly to a bus transmitter/ receiver
via the RTR Manchester II encoder/decoder. The UT1553B
RTR receives the command word from the MIL-STD1553B bus and processes it either by the primary or
secondary decoder. Each decoder checks for the proper sync
pulse and Manchester waveform, edge skew, correct number
of bits, and parity. If the command is a receive command,
the RTR processes each incoming data word for correct
format and checks the control logic for correct word count
and contiguous data. If an invalid message error is detected,
the message error pin is asserted, the RTR ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.
The RTR automatically compares the transmitted word
(encoder word) to the reflected decoder word by way of the
continuous loop-back feature. If the encoder word and
reflected word do not match, the transmitter error pin
(TXERR) is asserted. In addition to the loop-back compare
test, a timer precludes a transmission greater than 760µs by
the assertion of Fail-safe Timer (TIMERON). This timer is
reset upon receipt of another command.
1.10 RT-RT Transfer Compare
The RT-to-RT Terminal Address compare logic makes sure
that the incoming status word’s Terminal Address matches
the Terminal Address of the transmitting RT specified in the
command word. An incorrect match results in setting the
Message Error bit and suppressing transmission of the status
word. (RT-to-RT transfer time-out = 54µs)
1.11 Illegal Command Decoding
The host has the option of asserting the ILLCOM pin to
illegalize a received command word. On receipt of an illegal
command, the RTR sets the Message Error bit in the status
word, sets the message error output, and sets the message
error latch in the Status Register.
The following RTR outputs may be used to externally
decode an illegal command, Mode Code or Subaddress
indicator (MC/SA), Mode Code or Subaddress bus
MCSA(4:0), Command Strobe (COMSTR), Broadcast
(BRDCST), and Remote Terminal to Remote Terminal
transfer (RTRT) (see figure 21 on page 31).
To illegalize a transmit command, the ILLCOM pin must
be asserted within 3.3µs after VALMSG goes to a logic 1 if
the RTR is to respond with the Message Error bit of the
status word at a logic 1. If the illegal command is mode code
2, 4, 5, 6, 7, or 18, the ILLCOM pin must be asserted within
664ns after Command Strobe (COMSTR) transitions to
logic 0. Asserting the ILLCOM pin within the 664ns inhibits
the mode code function. For mode code illegalization, assert
the ILLCOM pin until the VALMSG signal is asserted.
For an illegal receive command, the ILLCOM pin is asserted
within 18.2µs after the COMSTR transitions to a logic 0 in
order to suppress data words from being stored. In addition,
the ILLCOM pin must be at a logic 1 throughout the
reception of the message until VALMSG is asserted. This
does not apply to illegal transmit commands since the status
word is transmitted first.
The above timing conditions also apply when the host
externally decodes an illegal broadcast command. The host
must remove the illegal command condition so that the next
command is not falsely decoded as illegal.
2.0 MEMORY MAP EXAMPLE
Figures 5 and 6 illustrate the UT1553B RTR buffering three
receive command messages to Subaddress 4. The receive
message pointer for Subaddress 4 is located at 03C4 (hex)
in the 1K x 16 RAM. The 16-bit contents of location 03C4
(hex) point to the memory location where the first receive
message is stored. The Address Field defined as bits 0
through 9 of address 03C4 (hex) contain address
information. The Index Field defined as bits 10 through 15
of address 03C4 (hex) contain the message buffer index (i.e.,
number of messages buffered).
Figure 5 demonstrates the updating of the message pointer
as each message is received and stored. The memory storage
of these three messages is shown in figure 6. After receiving
the third message for Subaddress 4 (i.e., Index Field equals
zero) the Address Field of the message pointer is not
incremented. If the host does not update the receive message
pointer for Subaddress 4 before the next receive command
for Subaddress 4 is accepted, the third message will
be overwritten.
Figures 7 and 8 show an example of multiple message
retrieval from Subaddress 16 upon reception of a MIL-STD1553B transmit command. The message pointer for transmit
Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM.
The 16-bit contents of location 03F0 (hex) point to the
memory location where the first message data words
are stored.
Figure 7 demonstrates the updating of the message pointer
as each message is received and stored. The data memory
for these three messages is shown in figure 8.
RTR-11
Example:
Remote terminal will receive and buffer three MIL-STD-1553 receive commands of various word
lengths to Subaddress 4.
MIL-STD-1553 Bus Activity:
CMD WORD #1 DW0 DW1 DW2 DW3
SA = 4
CMD WORD #2 DW0 DW1
T/R = 0
SA = 4
WC = 4
CMD WORD #3 DW0 DW1 DW2 DW3
T/R = 0
SA = 4
WC = 2
T/R = 0
WC = 4
Receive Subaddress 4;
INDEX= 0000 10
03C4 (hex)
0840 (hex)
data pointer at 03C4
ADDRESS= 00 0100 0000
(hex). (Initial condition)
After message #1,
INDEX= 0000 01
03C4 (hex)
0445 (hex)
4 data words plus
ADDRESS= 00 0100 0101
command word.
After message #2,
INDEX= 0000 00
03C4 (hex)
0048 (hex)
2 data words plus
ADDRESS= 00 0100 1000
command word.
After message #3,
INDEX= 0000 00
03C4 (hex)
0048 (hex)
4 data words plus
ADDRESS= 00 0100 1000
command word.
Figure 5. RTR Message Handling
03C4 (hex)
03C4 (hex)
03C4 (hex)
03C4 (hex)
0840 (hex)
0445 (hex)
0048 (hex)
0048 (hex)
COMMAND WORD #1
041 (hex)
DATA WORD 1
042 (hex)
DATA WORD 2
043 (hex)
DATA WORD 3
044 (hex)
COMMAND WORD #2
045 (hex)
DATA WORD 0
046 (hex)
DATA WORD 1
047 (hex)
COMMAND WORD #3
048 (hex)
DATA WORD 0
049 (hex)
DATA WORD 1
04A (hex)
DATA WORD 2
04B (hex)
DATA WORD 3
04C (hex)
Figure 6. Memory Storage Subaddress 4
RTR-12
040 (hex)
DATA WORD 0
Example:
Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands of various word lengths to
Subaddress 16.
MIL-STD-1553 Bus Activity:
CMD WORD #1 SW DW0 DW1 DW2 DW3
SA= 16
CMD WORD #2 SW DW0 DW1
T/R=1
WC= 4
SA= 16
CMD WORD #3 SW DW0 DW1 DW2 DW3
T/R=1
WC= 2
SA= 16
T/R=1
WC= 4
Transmit Subaddress 16;
data pointer at 03F0
(hex). (Initial condition)
03F0 (hex)
0830 (hex)
INDEX= 0000 10
ADDRESS= 00 0011 0000
After message #1,
4 data words.
03F0 (hex)
0434 (hex)
INDEX= 0000 01
ADDRESS= 00 0011 0100
After message #2,
2 data words.
03F0 (hex)
0036 (hex)
INDEX= 0000 00
ADDRESS= 00 0011 0110
After message #3,
4 data words.
03F0 (hex)
0036 (hex)
INDEX= 0000 00
ADDRESS= 00 0011 0110
Figure 7. RTR Message Handling
0830 (hex)
0434 (hex)
0036 (hex)
0036(hex)
(hex)
034
DATA WORD 0
030 (hex)
DATA WORD 1
031 (hex)
DATA WORD 2
032 (hex)
DATA WORD 3
033 (hex)
DATA WORD 0
034 (hex)
DATA WORD 1
035 (hex)
DATA WORD 0
036 (hex)
DATA WORD 1
037 (hex)
DATA WORD 2
038 (hex)
DATA WORD 3
039 (hex)
Note:
The example is valid only if message structure is known in advance.
Figure 8. Memory Storage Subaddress 16
RTR-13
3.0 PIN IDENTIFICATION AND DESCRIPTION
BIPHASE OUT
TAZ
TAO
TBZ
TBO
BIPHASE IN
RAZ
RAO
RBZ
RBO
TERMINAL
ADDRESS
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
MODE/CODE
SUBADDRESS
MCSA0
MCSA1
MCSA2
MCSA3
STATUS
SIGNALS
MCSA4
MERR
TERACT
TXERR
TIMERON
COMSTR
MC/SA
BRDCST
T/R
RTRT
VALMSG
RBUSY
CONTROL
SIGNALS
CS
RD/WR
CTRL
OE
ILLCOM
J2
H1
H2
G1
G2
F1
E2
D1
D2
C1
A10
B10
A9
B9
L7
K8
L6
K7
L5
K5
L4
K4
L3
K6
B2
A2
A3
B3
A4
A5
A6
B5
B6
B8
B1
A7
B4
B7
L8
C2
K2
K1
J1
L9
K9
UT1553B
RTR
ADDR1
ADDR2
ADDRESS
BUS
ADDR(9:0)
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
L10
K10
K11
J10
J11
H10
H11
G10
F11
E10
E11
D10
D11
C10
C11
B11
DATA0
F10
VDD
E1
VDD
F2
G11
VSS
DATA1
DATA BUS
DATA(15:0)
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
POWER
GROUND
VSS
L2
A8
12MHZ
K3
MRST
Figure 9. UT1553B RTR Pin Description
RTR-14
ADDR0
CLOCK
2MHZ
RES
E
Legend for TYPE and ACTIVE fields:
TI = TTL input
TUI = TTL input (pull-up)
TDI = TTL input (pull-down)
TO = TTL output
TTO = Three-state TTL output
TTB = Three-state TTL bidirectional
AL = Active low
AH = Active high
[] - Value in parentheses indicates initial state of pins.
DATA BUS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
DATA15
B11
TTB
--
Bit 15 (MSB) of the bidirectional Data bus.
DATA14
C11
TTB
--
Bit 14 of the bidirectional Data bus.
DATA13
C10
TTB
--
Bit 13 of the bidirectional Data bus.
DATA12
D11
TTB
--
Bit 12 of the bidirectional Data bus.
DATA11
D10
TTB
--
Bit 11 of the bidirectional Data bus.
DATA10
E11
TTB
--
Bit 10 of the bidirectional Data bus.
DATA9
E10
TTB
--
Bit 9 of the bidirectional Data bus.
DATA8
F11
TTB
--
Bit 8 of the bidirectional Data bus.
DATA7
G10
TTB
--
Bit 7 of the bidirectional Data bus.
DATA6
H11
TTB
--
Bit 6 of the bidirectional Data bus.
DATA5
H10
TTB
--
Bit 5 of the bidirectional Data bus.
DATA4
J11
TTB
--
Bit 4 of the bidirectional Data bus.
DATA3
J10
TTB
--
Bit 3 of the bidirectional Data bus.
DATA2
K11
TTB
--
Bit 2 of the bidirectional Data bus.
DATA1
K10
TTB
--
Bit 1 of the bidirectional Data bus.
DATA0
L10
TTB
--
Bit 0 (LSB) of the bidirectional Data bus.
ADDRESS BUS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
ADDR9
C1
TI
--
Bit 9 (MSB) of the Address bus.
ADDR8
D2
TI
--
Bit 8 of the Address bus.
ADDR7
D1
TI
--
Bit 7 of the Address bus.
ADDR6
E2
TI
--
Bit 6 of the Address bus.
ADDR5
F1
TI
--
Bit 5 of the Address bus.
ADDR4
G2
TI
--
Bit 4 of the Address bus.
ADDR3
G1
TI
--
Bit 3 of the Address bus.
ADDR2
H2
TI
--
Bit 2 of the Address bus.
ADDR1
H1
TI
--
Bit 1 of the Address bus.
ADDR0
J2
TI
--
Bit 0 (LSB) of the Address bus.
RTR-15
CONTROL INPUTS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
CS
K2
TI
AL
Chip Select. The host processor uses the CS signal for RTR
Status Register reads, Control Register writes, or host
access to the RTR internal RAM.
RD/WR
K1
TI
--
Read/Write. The host processor uses a high level on this
input in conjunction with CS to read the RTR Status
Register or the RTR internal RAM. A low level on this
input is used in conjunction with CS to write to the RTR
Control Register or the RTR internal RAM.
CTRL
J1
TI
AL
Control. The host processor uses the active low CTRL
input signal in conjunction with CS and
RD/WR to access the RTR registers. A high level on this
input means access is to RTR internal RAM only.
OE
L9
TI
AL
Output Enable. The active low OE signal is used to control
the direction of data flow from the RTR. For OE = 1, the
RTR Data bus is three-state; for
OE = 0, the RTR Data bus is active.
ILLCOM
K9
TDI
AH
Illegal Command. The host processor uses the
ILLCOM input to inform the RTR that the present
command is illegal.
STATUS INPUTS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
MERR
[0]
A5
TO
AH
Message Error. The active high MERR output
signals that the Message Error bit in the Status
Register has been set due to receipt of an illegal command,
or an error during message sequence. MERR will reset to
logic zero on the receipt of the next valid command.
TXERR
[0]
B5
TO
AH
Transmission Error. The active high TXERR output is
asserted when the RTR detects an error in the reflected
word versus the transmitted word, using the continuous
loop-back compare feature. Reset on next COMSTR
assertion.
TIMERON
[1]
B6
TO
AL
Fail-safe Timer. The TIMERON output pulses low for
760µs when the RTR begins transmitting (i.e., rising edge
of VALMSG) to provide a fail-safe timer meeting the
requirements of MIL-STD-1553B. This pulse is reset when
COMSTR goes low or during a Master Reset.
COMSTR
[1]
B8
TO
AL
Command Strobe. COMSTR is an active low output of
500ns duration identifying receipt of a valid command.
TERACT
A6
TO
AL
Terminal Active. The active low TERACT output is
asserted at the beginning of the RTR access to internal
RAM for a given command and negated after the last
access for that command.
RTR-16
STATUS INPUTS
Continued from page 16.
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
BRDCST
[1]
A7
TO
AL
Broadcast. BRDCST is an active low output that identifies
receipt of a valid broadcast command.
T/R
[0]
B4
TO
--
Transmit/Receive. A high level on this pin indicates a
transmit command message transfer is being or was
processed, while a low level indicates a receive command
message transfer is being or was processed.
RTRT
[1]
B7
TO
AH
Valid Message. VALMSG is an active high output
indicating a valid message (including Broadcast) has been
received. VALMSG goes high prior to transmitting the
1553 status word and is reset upon receipt of the next
command.
RBUSY
[0]
C2
TO
AH
RTR Busy. RBUSY is asserted high while the RTR is
accessing its own internal RAM either to read or update the
pointers or to store or retrieve data words. RBUSY
becomes active either 2.7µs or 5.7µs before RTR requires
RAM access. This timing is controlled by Control Register
bit 12 (see section 1.3).
TYPE
ACTIVE
DESCRIPTION
MODE CODE/SUBADDRESS OUTPUTS
NAME
PIN NUMBER
(PGA)
MC/SA
[0]
B1
TO
--
Mode Code/Subaddress Indicator. If MC/SA is low, it
indicates that the most recent command word is a mode
code command. If MC/SA is high, it indicates that the most
recent command word is for a subaddress. This output
indicates whether the mode code/subaddress ouputs (i.e.,
MCSA(4:0)) contain mode code or subaddress
information.
MCSA0
[0]
B2
TO
--
Mode Code/Subaddress Output 0. If MC/SA is low, this
pin represents the least significant bit of the most recent
command word (the LSB of the mode code). If MC/SA is
high, this pin represents the LSB of the subaddress.
MCSA1
[0]
A2
TO
--
Mode Code/Subaddress Output 1.
MCSA2
[0]
A3
TO
--
Mode Code/Subaddress Output 2.
MCSA3
[0]
B3
TO
--
Mode Code/Subaddress Output 3.
MCSA4
[0]
A4
TO
--
Mode Code/Subaddress Output 4. If MC/SA is low, this
pin represents the most significant bit of the mode code. If
MC/SA is high, this pin represents the MSB of the
subaddress.
RTR-17
REMOTE TERMINAL ADDRESS INPUTS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
RTA4
L3
TUI
--
Remote Terminal Address bit 4 (MSB).
RTA3
K4
TUI
--
Remote Terminal Address bit 3.
RTA2
L4
TUI
--
Remote Terminal Address bit 2.
RTA1
K5
TUI
--
Remote Terminal Address bit 1.
RTA0
L5
TUI
--
Remote Terminal Address bit 0 (LSB).
RTPTY
K6
TUI
--
Remote Terminal Address Parity. This input must provide
odd parity for the Remote Terminal Address.
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
RAZ
L7
TI
--
Receiver - Channel A, Zero Input. Idle low Manchester
input form the 1553 bus receiver.
RAO
K8
TI
--
Receiver - Channel A, One Input. This input is the
complement of RAZ.
RBZ
L6
TI
--
Receiver - Channel B, Zero Input. Idle low Manchester
input from the 1553 bus receiver.
RBO
K7
TI
--
Receiver - Channel B, One Input. This input is the
complement of RBZ.
BIPHASE INPUTS
NAME
DESCRIPTION
1
Note:
1. For uniphase operation, tie RAZ (or RBZ) to VDD and apply true uniphase input signal to RAO (or RBO).
BIPHASE OUTPUTS
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
TAZ
[0]
A10
TO
--
Transmitter - Channel A, Zero Output. This idle low
Manchester encoded data output is connected to the 1553
bus transmitter input. The output is idle low.
TAO
[0]
B10
TO
--
Transmitter - Channel A, One Output. This output is the
complement of TAZ. The output is idle low.
TBZ
[0]
A9
TO
--
Transmitter - Channel B, Zero Output. This idle low
Manchester encoded data output is connected to the 1553
bus transmitter input. The output is idle low.
TBO
[0]
B9
TO
--
Transmitter - Channel B, One Output. This input is the
complement of TBZ. The output is idle low.
RTR-18
MASTER RESET AND CLOCK
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
MRST
K3
TUI
--
Master Reset. Initializes all internal functions of the RTR.
MRST must be asserted 500ns before normal RTR
operation (500ns minimum). Does not reset RAM.
12MHz
L2
TI
--
12 MHz Input Clock. This is the RTR system clock that
requires an accuracy greater than 0.01% with a duty cycle
of 50% ± 10%.
2MHz
A8
TO
--
2MHz Clock Output. This is a 2MHz clock output
generated by the 12MHz input clock. This clock is stopped
when MRST is low.
POWER AND GROUND
NAME
PIN NUMBER
(PGA)
TYPE
ACTIVE
DESCRIPTION
VDD
F10
E1
PWR
PWR
---
+5 VDC Power. Power supply must be +5 VDC
± 10%.
VSS
F2
G11
GND
GND
---
Reference ground. Zero VDC logic ground.
4.0 OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
(referenced to VSS)
VDD
SYMBOL
PARAMETER
DC supply voltage
LIMITS
-0.3 to +7.0
VIO
Voltage on any pin
0.3 to VDD+0.3
V
II
DC input current
±10
mA
TSTG
Storage temperature
°C
TJ
Maximum power dissipation
Maximum junction temperature
-65 to +150
300
+175
°C
ΘJC
Thermal resistance, junction-to-case
20
°C/W
PD
1
UNIT
V
mW
Note:
1. Does not reflect the added PD due to an output short-circuited.
* Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification
is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VDD
SYMBOL
PARAMETER
DC supply voltage
LIMITS
4.5 to 5.5
UNIT
VIN
DC input voltage
0 to VDD
V
TC
Temperature range
-55 to +125
°C
FO
Operating frequency
12 ± .01%
MHz
V
RTR-19
5.0 DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V ±10%; -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
VIL
Low-level input voltage
VIH
High-level input voltage
IIN
Input leakage current
TTL inputs
Inputs with pull-down resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
VOL
Low-level output voltage
IOL = 3.2mA
VOH
IOZ
High-level output voltage
Three-state output
leakage current
IOS
CIN
MINIMUM
MAXIMUM
UNIT
0.8
V
2.0
V
µA
µA
µA
-1
1110
-2000
1
-2000
-110
0.4
V
IOH = -400µA
VO = VDD or VSS
2.4
-10
+10
V
µA
Short-circuit output current 1, 2
VDD = 5.5V, VO = VDD
VDD = 5.5V VO = 0V
-90
90
mA
mA
Input capacitance 3
ƒ = 1MHz @ 0V
10
pF
ƒ = 1MHz @ 0V
ƒ = 1MHz @ 0V
15
20
pF
pF
3
COUT
CIO
Output capacitance
Bidirect I/O capacitance 3
IDD
Average operating current 1, 4
ƒ = 12MHz, CL = 50pF
50
mA
QIDD
Quiescent current
Note 5
1.5
mA
Notes:
1. Supplied as a design limit but not guaranteed or tested.
2. Not more than one output may be shorted at a time for a maximum duration of one second.
3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.
Voltage supply should be adequately sized and decoupled to handle a large surge current.
5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.
10 11 12 13 14
5
1
5
P
1
1
1
Figure 10. MIL-STD-1553B Word Formats
1
1
1
1
1
1
PARITY
DATA
TERMINAL FLAG
1
DYNAMIC BUS CONTROL ACCEPTANCE
16
SUBSYSTEM FLAG
REMOTE TERMINAL
P
BUSY
5
ADDRESS
RTR-20
1
BROADCAST COMMAND RECEIVED
SYNC
SYNC
20
REMOTE TERMINAL T/R SUBADDRESS/MODE DATA WORD COUNT/
MODE CODE
ADDRESS
CODE
DATA WORD
STATUS WORD
15 16 17 18 19
5
RESERVED
SYNC
9
SERVICE REQUEST
COMMAND
WORD
45678
INSTRUMENTATION
123
MESSAGE ERROR
BIT TIMES
6.0 AC ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions)
INPUT
VIH MIN
VIL MAX
ta
IN-PHASE
OUTPUT
OUT-OF-PHASE
OUTPUT
tc
VIH MIN
VIL MAX
1
1
tb
2
2
2
2
VOH MIN
VOL MAX
td
VOH MIN
VOL MAX
te
VOH MIN
VOL MAX
BUS
tf
tg
th
SYMBOL
ta
tb
tc
td
te
tf
tg
th
INPUT↓ to response ↑
INPUT↓ to response ↓
INPUT↑ to response ↓
INPUT↓ to response ↑
INPUT↓to data valid
INPUT↓ to high Z
INPUT↑ to high Z
INPUT↑to data valid
PARAMETER
Notes:
1. Timing measurements made at (VIH MIN + VIL MAX)/2.
2. Timing measurements made at (VOL MAX + VOH MIN)/2.
3. Based on 50pF load.
4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization.
Figure 11a. Typical Timing Measurements
5V
IREF (source)
90%
3V
90%
VREF
10%
50pF
10%
0V
IREF (sink)
< 2ns
< 2ns
Input Pulses
Note:
50pF including scope probe and test socket
Figure 11b. AC Test Loads and Input Waveforms
RTR-21
12MHz
t12i
CS
t12j
t12a
t12f
CTRL
t12b
RD/WR
t12k
t12c
t12g
ADDR(9:0)
t12d
DATA(15:0)
t12l
DATA VALID
t12h
t12e
t12m
OE
Figure 12. Microprocessor RAM Read
SYMBOL
t12a
t12b
t12c
t12d
t12e
t12f
t12g
t12h
t12i
t12j
t12k
t12l
t12m
PARAMETER
1
CTRL↑ set up wrt CS↓
RD/WR ↑ set up wrt CS↓
ADDR(9:0) Valid to CS↓ (Address Set up)
CS↓ to DATA(15:0) Valid
OE↓ to DATA(15:0) Don’t Care (Active)
CS↑ to CTRL Don’t Care
CS↑ to ADDR(9:0) Don’t Care
OE↑ to DATA(15:0) High Impedance
CS↓ to CS↑ 2
CS↑ to CS↓
CS↑ to RD/WR Don’t Care
CS↑ to DATA(15:0) Invalid 3
OE↓ to OE↑
MIN
MAX
UNITS
10
10
10
--0
0
-220
85
0
25
65
---155
65
--40
5500
-----
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. “wrt” defined as “with respect to.”
2. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs
RBUSY option, the maximum CS low time is 2500ns.
3. Assumes OE is asserted.
RTR-22
12MHz
t13i
CS
t13j
t13a
t13k
CTRL
t13b
RD/WR
t13f
t13c
ADDR(9:0)
t13g
t13d
VALID DATA
DATA(15:0)
t13h
OE
t13e
Figure 13. Microprocessor RAM Write
SYMBOL
MIN
MAX
UNITS
t13a
CTRL↑ set up wrt CS↓
PARAMETER
10
--
ns
t13b
t13c
t13d
t13e
t13f
t13g
t13h
t13i
t13j
t13k
RD/WR↓ set up wrt CS↓
ADDR(9:0) Valid to CS↓(Address set up)
DATA(15:0) Valid to CS↓(DATA set up)
OE↑ to DATA(15:0) High Impedance
CS↑ to RD/WR Don’t Care
CS↑ to ADDR(9:0) Don’t Care
CS↑ to DATA(15:0) Don’t Care (Hold-time)
CS↓ to CS↑ 1
CS↑ to CS↓
CS↑ to CTRL Don’t Care
10
10
0
40
0
0
20
180
85
0
-------5500
---
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7ms RBUSY option. For the 2.7ms
RBUSY option, the maximum CS low time is 2500ns.
RTR-23
12MHz
t14c
CS
t14a
t14e
CTRL
t14b
RD/WR
t14f
DATA(15:0)
t14h
VALID DATA
t14d
OE
t14g
Figure 14. Control Register Write
SYMBOL
PARAMETER
MIN
MAX
UNITS
t14a
CTRL↓ set up wrt CS↓
0
--
ns
t14b
t14c
t14d
t14e
t14f
t14g
t14h
RD/WR↓ set up wrt CS↓
CS↓ to CS↑ 1
CS↑ to DATA(15:0) Don’t Care (Hold-time)
CS↑ to CTRL Don’t Care
CS↑ to RD/WR Don’t Care
OE↑ to DATA(15:0) High Impedance
DATA(15:0) Valid to CS↓ (DATA set up)
0
50
0
0
0
40
0
-5500
------
ns
ns
ns
ns
ns
ns
ns
Note:
1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs
RBUSY option, the maximum CS low time is 2500ns.
RTR-24
12MHz
t15b
CS
t15a
t15e
CTRL
t15c
RD/WR
t15f
t15d
t15j
VALID DATA
DATA(15:0)
t15g
t15h
t15i
OE
Figure 15. Status Register Read
SYMBOL
t15a
t15b
t15c
t15d
t15e
t15f
t15g
t15h
t15i
t15j
PARAMETER
MIN
MAX
UNITS
CTRL↓ set up wrt CS↓
CS↓ to CS↑ 1
RD/WR↑ set up wrt CS↓
CS↓ to DATA(15:0) Valid
CS↑ to CTRL Don’t Care
CS↑ to RD/WR Don’t Care
OE↓ to DATA(15:0) Don’t Care (Active)
OE↑ to DATA(15:0) High Impedance
OE↓ to OE↑
CS↓ to DATA(15:0) Don’t Care (Active)
0
65
0
-5
5
--65
25
-5500
-65
--65
40
---
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7ms RBUSY option. For the 2.7ms
RBUSY option, the maximum CS low time is 2500ns.
RTR-25
VALMSG
t16a
t16c
TIMERON
A/B
BIPHASE
OUTPUT ZERO
t16b
COMSTR
t16d
ILLCOM
t16e
t16g
t16f
Figure 16. RT Fail-Safe Timer Signal Relationships
SYMBOL
t16a
t16b
t16c
t16d
t16e
t16f
t16f
t16g
PARAMETER
VALMSG↑ before TIMERON↓
TIMERON↓ before first
BIPHASE OUT O↑
TIMERON low pulse width (time-out)
COMSTR↓ to TIMERON↑
VALMSG↑ to ILLCOM↑
COMSTR↓ to ILLCOM↑ 1
COMSTR↓ to ILLCOM↑ 2
ILLCOM↑ to ILLCOM↓ 3
Notes:
1. Mode code 2, 4, 5, 6, 7, or 18 received.
2. To suppress data word storage.
3. For transmit command illegalization.
RTR-26
MIN
MAX
UNITS
0
1.2
35
--
µs
µs
727.3
----500
727.4
25
3.3
664
18.2
--
µs
µs
µs
µs
µs
µs
12MHz
CS COMMAND WORD
BIPHASE IN
P
1
t17a
MC/SA
and MCSA(4:0)
t17b
t17c
COMSTR
t17l
t17d
t17e
BRDCST
t17f
t17g
T/R
t17h
t17i
VALMSG
t17j
t17k
MERR
Note:
1. Measured from the mid-bit parity crossing.
Figure 17. Status Output Timing
SYMBOL
t17a 4
t17b
t17c 4
t17d
t17e 4
t17f
t17g 4
t17h
t17i 4
t17j
t17k 4
t17l
PARAMETER
12MHz↑ to MC/SA Valid
Command Word to MC/SA Valid 3
12MHz↑ to COMSTR↓
Command Word to COMSTR↓ 3
12MHz↑ to BRDCST↓
Command Word to BRDCST↓ 3
12MHz↑ to T/R Valid
Command Word to T/R Valid 3
12MHz↑ to VALMSG↑
Command Word to VALMSG↑ 1, 2, 3
12MHz↑ to MERR↑
COMSTR↓ to COMSTR↑
MIN
MAX
UNITS
0
2.1
0
3.2
0
2.6
0
2.2
0
6.2
0
485
14
2.8
17
3.7
32
3.2
57
2.7
32
6.7
37
500
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Notes:
1. Receive last data word to Valid Message active (VALMSG↑).
2. Transmit command word to Valid Message active (VALMSG↑).
3. Command word measured from mid-bit crossing.
4. Guaranteed by test.
RTR-27
12MHz
CS
COMMAND WORD
P
t18a
BIPHASE IN
RBUSY
t18b
t18c
t18i
t18h
TERACT
t18d
t18e
RTRT
t18f
t18g
MRST
Note:
1. Measured from mid-bit parity crossing.
Figure 18. Status Output Timing
SYMBOL
t18a
t18b
t18c 1
t18d
t18e 1
t18f
t18g
t18h
t18i
PARAMETER
12MHz↑ to RBUSY↑
Command Word to RBUSY↑ 2
12MHz↑ to TERACT↓
Command Word to TERACT↓ 2
12MHz↑ to RTRT↑
Command Word to RTRT↑ 2
MRST↓ to MRST↑
RBUSY↑ to RBUSY↓ (2.7ms)
(5.7ms)
RBUSY↓ to RBUSY↑ (2.7ms)
(5.7ms)
Notes:
1. Guaranteed by test.
2. Command word measured from mid-bit crossing.
RTR-28
MIN
MAX
UNITS
-3.2
0
3.1
0
21.0
500
--3.10
240
37
3.8
37
3.7
32
22.0
-5.5
8.5
---
ns
µs
ns
µs
ns
µs
ns
µs
µs
µs
µs
BIPHASE IN CS COMMAND WORD DATA WORD
P DS
DATA WORD
P
COMSTR
T/R
RBUSY
1
2
3
TERACT
SS
BIPHASE OUT
STATUS
P
VALMSG
Notes:
1. Burst of 5 DMAs: read command pointer, store command word, update command pointer, read data word pointer, store
command word.
2. Burst of 1 DMA: store data word.
3. Burst of 2 DMAs: store data word, update data word pointer.
4.Approximately 560ns per DMA access.
Figure 19a. Receive Command with Two Data Words
BIPHASE IN
CS
COMMAND
P
COMSTR
T/R
RBUSY
1
2
3
TERACT
BIPHASE OUT
SS
STATUS
P
DS
DATA
P
DS
DATA
P
VALMSG
CS = Command sync
SS = Status sync
DS = Data sync
P = Parity
Notes:
1. Burst of 4 DMAs: read command pointer, store command word, update command pointer, read data word pointer.
2. Burst of 1 DMA: read data word.
3. Burst of 2 DMAs: read data word, update data word pointer.
4. Approximately 560ns per DMA access.
Figure 19b. Transmit Command with Two Data Words
RTR-29
ADDR(9:0)
DATA(15:0)
HOST
SUBSYSTEM
UT1553B
RTR
CONTROL
UT63M125
1553 TRANSCEIVER
1553 BUS A
1553 BUS B
Figure 20a. RTR General System Diagram (Idle low interface)
RAO
RAZ
RXOUT
RXOUT
TAO
TAZ
TXINHB
TXIN
TXIN
CHANNEL A
UTMC
63M125
RTR
CHANNEL B
RBO
RBZ
RXOUT
RXOUT
TBO
TBZ
TXINHB
TXIN
TXIN
TIMERON
Figure 20b. RTR Transceiver Interface Diagram
RTR-30
CHANNEL A
CHANNEL B
MC/SA
RTR
MCSA0
MCSA1
MCSA2
MCSA3
MCSA4
ILLEGAL
COMMAND
DECODER
COMSTR
BRDCST
RTRT
T/R
ILLCOM
Figure 21. Mode Code/Subaddress Illegalization Circuit
RTR-31
Package Selection Guide
RTI
24-pin DIP
(single cavity)
36-pin DIP
(dual cavity)
68-pin PGA
84-pin PGA
144-pin PGA
84-lead LCC
36-lead FP
(dual cavity)
(50-mil ctr)
84-lead FP
132-lead FP
RTMP
RTR
Product
BCRT BCRTM BCRTMP
RTS
XCVR
X
X
X
X
X
X
X
X1
X
X1
X
X
X
X
X
X
X
NOTE:
1. 84LCC package is not available radiation-hardened.
Packaging-1
D
1.565 ± 0.025
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
0.040 REF.
0.080 REF.
(2 Places)
A
L
0.130 ±0.010
0.100 REF.
(4 Places)
E
1.565 ± 0.025
-B-
PIN 1 I.D.
(Geometry Optional)
e
0.100
TYP.
TOP VIEW
-CA
(Base Plane)
b
0.018 ± 0.002
0.030 C A B
0.010 C 2
R
SIDE VIEW
P
N
M
L
K
J
D1/E1
1.400
H
G
F
E
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW
0.003 MIN. TYP.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All package finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
144-Pin Pingrid Array
Packaging-2
1
D/E
1.525 ± 0.015 SQ.
D1/E1
0.950 ± 0.015 SQ.
A
0.110
0.006
A
PIN 1 I.D.
(Geometry
Optional)
e
0.025
SEE DETAIL A
A
LEAD KOVAR
TOP VIEW
C
0.005 + 0.002
- 0.001
L
0.250
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX. REF.
(At Braze Pads)
DETAIL A
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
132-Lead Flatpack (25-MIL Lead Spacing)
Packaging-3
A
0.115 MAX.
D/E
1.150 ± 0.015 SQ.
A1
0.080 ± 0.008
A
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
SIDE VIEW
L/L1
0.050 ± 0.005 TYP.
h
0.040 x 45_
REF. (3 Places)
B1
0.025 ± 0.003
e
0.050
J
0.020 X 455 REF.
e1
0.015 MIN.
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-LCC
Packaging-4
A
D/E
1.810 ± 0.015 SQ.
D1/E1
1.150 ± 0.012 SQ.
A
0.110
0.060
PIN 1 I.D.
(Geometry
Optional)
A
e
0.050
b
0.016 ± 0.002
SEE DETAIL A
A
LEAD KOVAR
C
0.007 ± 0.001
TOP VIEW
L
0.260
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX.
REF.
(At Braze Pads)
BOTTOM VIEW A-A
DETAIL A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-Lead Flatpack (50-MIL Lead Spacing)
Packaging-5
D
1.100 ± 0.020
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
A
L
0.130 ± 0.010
E
1.100 ± 0.020
PIN 1 I.D.
(Geometry Optional)
-B-
-C(Base Plane)
TOP VIEW
e
0.100
TYP.
0.030 C A B
0.010 C 2
SIDE VIEW
L
K
J
H
G
D1/
1.000
F
E
D
1
A
b
0.018 ± 0.002
2
3
4
5
6
7
8 9 10 11
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
0.003 MIN.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
84-Pin Pingrid Array
Packaging-6
1
D
1.100 ± 0.020
A
0.130 MAX.
Q
0.050 ± 0.010
-A-
A
L
0.130 ± 0.010
E
1.100 ± 0.020
-B-
PIN 1 I.D.
(Geometry Optional)
A
-C(Base Plane)
TOP
b
0.010 ± 0.002
∅ 0.030 C A B
∅ 0.010 C 2
e
0.100
TYP.
1
SIDE VIEW
L
K
J
H
G
F
E
D
C
B
A
D1/E1
1.00
1 2 3 4 5 6
PIN 1 I.D.
(Geometry Optional)
7
8
9
10 11
0.003 MIN. TYP.
BOTTOM VIEW A-A
Notes:
1 True position applies to pins at base plane (datum C).
2 True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
68-Pin Pingrid Array
Packaging-7
E
0.750 ± 0.015
L
0.490
MIN.
b
0.015 ± 0.002
D
1.800 ± 0.025
e
0.10
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
c
0.008
+ 0.002
- 0.001
A
0.130 MAX.
END VIEW
Notes:
1 All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)
Packaging-8
Q
0.080 ± 0.010
(At Ceramic Body)
E
0.700 + 0.015
L
0.330
MIN.
b
0.016 + 0.002
D
1.000 ± 0.025
e
0.050
PIN 1 I.D
(Geometry Optional)
TOP
+ 0.002
c
0.007 - 0.001
A
0.100 MAX.
END
Q
0.070 + 0.010
(At Ceramic Body)
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)
Packaging-9
E
0.590 ± 0.012
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.800 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
C
0.010 +- 0.002
0.001
E1
0.600 + 0.010
(At Seating Plane)
A
0.155 MAX.
L/L1
0.150 MIN.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
36-Lead Side-Brazed DIP, Dual Cavity
Packaging-10
E
0.590 ± 0.015
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.200 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
+ 0.002
C
0.010 - 0.001
E1
0.600 + 0.010
(At Seating Plane)
L/L1
0.150 MIN.
A
0.140 MAX.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
24-Lead Side-Brazed DIP, Single Cavity
Packaging-11
ORDERING INFORMATION
UT1553B RTR Remote Terminal with RAM: S
5962
*
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(X) = 68 pin PGA
Class Designator:
(-) = Blank or No field is QML Q
Drawing Number: 8957601
Total Dose:
(-) = None
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8957601XC).
UT1553B RTR Remote Terminal with RAM
No UT Part
Number- *
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Package Type:
(G) = 68 pin PGA
UTMC Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).