TI INA159AIDGKTG4

INA159
SBOS333B − JULY 2005 − REVISED OCTOBER 2005
Precision, Gain of 0.2 Level Translation
DIFFERENCE AMPLIFIER
FEATURES
DESCRIPTION
D GAIN OF 0.2 TO INTERFACE ±10V SIGNALS
TO SINGLE-SUPPLY ADCs
D
D
D
D
D
D
GAIN ACCURACY: ±0.024% (max)
WIDE BANDWIDTH: 1.5MHz
HIGH SLEW RATE: 15V/µs
LOW OFFSET VOLTAGE: ±100µV
LOW OFFSET DRIFT: ±1.5µV/°C
SINGLE-SUPPLY OPERATION DOWN TO 1.8V
APPLICATIONS
D INDUSTRIAL PROCESS CONTROLS
D INSTRUMENTATION
D DIFFERENTIAL TO SINGLE-ENDED
D
The INA159 is a high slew rate, G = 1/5 difference amplifier
consisting of a precision op amp with a precision resistor
network. The gain of 1/5 makes the INA159 useful to
couple ±10V signals to single-supply analog-to-digital
converters (ADCs), particularly those operating on a single
+5V supply. The on-chip resistors are laser-trimmed for
accurate gain and high common-mode rejection. Excellent
temperature coefficient of resistance (TCR) tracking of the
resistors maintains gain accuracy and common-mode
rejection over temperature. The input common-mode
voltage range extends beyond the positive and negative
supply rails. It operates on a total of +1.8V to +5.5V single
or split supplies. The INA159 reference input uses two
resistors for easy mid-supply or reference biasing.
The difference amplifier is the foundation of many
commonly-used circuits. The INA159 provides this circuit
function without using an expensive external precision
resistor network. The INA159 is available in an MSOP-8
surface-mount package and is specified for operation over
the extended industrial temperature range, −40°C to
+125°C.
CONVERSION
AUDIO LINE RECEIVERS
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
C1
1000pF
VIN
+IN
100kΩ
40kΩ
REF 2
40kΩ
V+
−IN
ADS8325
ADC
DCLOCK
CS
GND
REF 1
INA159
Figure 1. Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2005, Texas Instruments Incorporated
! ! www.ti.com
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
Signal Input Terminals (−IN and +IN), Voltage . . . . . . . . . . . . . ±30V
Reference (REF 1 and REF2) and Sense Pins
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Voltage . . . . . . . . . . . . . . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V
Output Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
INA159
MSOP-8
DGK
CJB
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
PIN CONFIGURATIONS
TOP VIEW
MSOP
INA159
2
REF 1
1
8
REF 2
−IN
2
7
V+
+IN
3
6
OUT
V−
4
5
SENSE
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5V, unless otherwise noted.
INA159
PARAMETER
CONDITIONS
OFFSET VOLTAGE(1)
Initial (1)
VOS
vs Temperature
vs Power Supply
PSRR
Reference Divider Accuracy(2)
over Temperature
RTO
VS = ±2.5V, Reference and Input Pins Grounded
MIN
VS = ±0.9V to ±2.75V
INPUT IMPEDANCE(3)
Differential
Common-Mode
INPUT VOLTAGE RANGE
Common-Mode Voltage
Range
Positive
Negative
Common-Mode Rejection
Ratio
over Temperature
CMRR
±100
±1.5
±20
±0.002
±0.002
±500
µV
µV/°C
µV/V
%
%
±100
±0.024
240
60
kΩ
kΩ
17.5
−12.5
V
V
VCM = −10V to +10V, RS = 0Ω
80
96
dB
94
dB
10
30
µVPP
nV/√Hz
RTO
VREF2 = 4.096V, RL Connected to GND,
(VIN+) − (VIN−) = −10V to +10V, VCM = 0V
G
OUTPUT
Voltage, Positive
Voltage, Negative
Current Limit, Continuous to Common
Capacitive Load
Open-Loop Output Impedance
RO
0.2
±0.005
±1
±0.0002
VREF2 = 4.096V, RL Connected to GND
VREF2 = 4.096V, RL Connected to GND
f = 1MHz, IO = 0
VS
Quiescent Current
IQ
±0.024
(V+) − 0.1
(V−) + 0.048
(V+) − 0.02
(V−) + 0.01
±60
See Typical Characteristic
110
−3dB
SR
tS
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
MSOP-8
UNIT
VCM
GAIN
FREQUENCY RESPONSE
Small-Signal Bandwidth
Slew Rate
Settling Time, 0.01%
Overload Recovery Time
MAX
RTI
OUTPUT VOLTAGE NOISE(4)
f = 0.1Hz to 10Hz
f = 10kHz
Initial
Error
vs Temperature
Nonlinearity
TYP
V
V
mA
pF
Ω
1.5
15
1
250
4V Output Step, CL = 100pF
50% Overdrive
MHz
V/µs
µs
ns
+5
+1.8
IO = 0mA, VS = ±2.5V,
Reference and Input Pins Grounded
1.1
−40
−40
−65
qJA
Surface-Mount
150
V/V
%
ppm/°C
% of FS
+5.5
V
V
1.5
mA
+125
+150
+150
°C
°C
°C
°C/W
(1) Includes effects of amplifier input bias and offset currents.
(2) Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 2.
(3) Internal resistors are ratio matched but have ±20% absolute value.
(4) Includes effects of amplifier input current noise and thermal noise contribution of resistor network.
3
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
+5V
V+
2
7
100kΩ
20kΩ
5
6
3
100kΩ
40kΩ
40kΩ
INA159
V−
The test is performed by
measuring the output
with the reference
applied to alternate
reference resistors, and
calculating a result such
that the amplifier offset is
cancelled in the final
measurement.
OUT
1
8
4
Figure 2. Test Circuit for Reference Divider Accuracy
TYPICAL CHARACTERISTICS
At TA = +25°C, RL = 10kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5V, unless otherwise noted.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
−500
−450
−400
−350
−300
−250
−200
−150
−100
−50
0
50
100
150
200
250
300
350
400
450
500
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Population
Population
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Offset Voltage Drift (µV/_C)
Offset Voltage (µV)
GAIN vs FREQUENCY
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
0
PSRR (dB)
Gain (dB)
−10
−20
−30
−40
−50
10
100
1k
10k
Frequency (Hz)
4
100k
1M
10M
130
120
110
100
90
80
70
60
50
40
30
20
10
0
−10
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5V, unless otherwise noted.
COMMON−MODE REJECTION RATIO vs FREQUENCY
QUIESCENT CURRENT vs TEMPERATURE
120
1.20
110
1.15
VS = 5.5V
100
1.10
CMRR (dB)
90
IQ (mA)
80
70
60
VS = 5V
1.05
1.00
0.95
VS = 1.8V
50
0.90
40
0.85
30
0.80
20
10
100
1k
10k
100k
1M
−50
10M
−25
0
Frequency (Hz)
SHORT−CIRCUIT CURRENT vs TEMPERATURE
120
75
100
125
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
2.5
2.0
80
60
VS = ±2.5V
Output Swing (V)
I SC (mA)
50
3.0
VS = ±2.75V
100
25
Temperature (_C)
40
20
VS = ±0.9V
0
−20
VS = ±2.5V
−40
−100
−50
VS = ±2.75V
−25
0
25
50
TA = −40_C
1.0
0.5
TA = −40_C
TA = +25_C
TA =
+125_ C
0
−0.5
TA = +125_C
−1.0
−1.5
−60
−80
1.5
−2.0
VS = ±0.9V
−2.5
VS = ±2.5V
−3.0
75
100
0
125
10
20
30
40
50
60
70
80
Temperature (_C)
Output Current (mA)
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
OUTPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
90
1000
Output Voltage Noise (nV/√Hz)
THD+Noise (%)
0.01
0.25VPP
2kΩ
4VPP
100
600Ω
10
0.001
10
100
1k
Frequency (Hz)
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
5
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5V, unless otherwise noted.
0.1Hz TO 10Hz NOISE
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
60
5µV/div
Overshoot (%)
50
40
30
VS = 5V
20
10
0
100
Time (1s/div)
1000
Load Capacitance (pF)
LARGE−SIGNAL STEP RESPONSE
1V/div
200mV/div
SMALL−SIGNAL STEP RESPONSE
Time (500ns/div)
Time (500ns/div)
SETTLING TIME
2mV/div
VOUT = 4V Step
CL = 100pF
Time (250ns/div)
6
3000
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
APPLICATION INFORMATION
The internal op amp of the INA159 has a rail-to-rail
common-mode voltage capability at its inputs. A rail-to-rail
op amp allows the use of ±10V inputs into a circuit biased
to 1/2 of a 5V reference (2.5V quiescent output). The inputs
to the op amp will swing from approximately 400mV to
3.75V in this application.
The unique input topology of the INA159 eliminates the
input offset transition region typical of most rail-to-rail
complementary stage operational amplifiers. This allows
the INA159 to provide superior glitch- and transition-free
performance over the entire common-mode range.
Good layout practice includes the use of a 0.1µF bypass
capacitor placed closely across the supply pins.
Where one REF pin is connected to the reference, and the
other pin grounded (1/2 reference connection):
V CM) + (V)) ) 5[(V)) * (0.5VREF)]
(3)
V CM* + (V*) * 5[(0.5V REF) * (V*)]
(4)
Some typical values are shown in Table 1.
Table 1. Common-Mode Range For Various
Supply and Reference Voltages
REF 1 and REF 2 Connected Together
V+
V−
VREF
VCM+
5
0
3
15
VCM−
−15
5
0
2.5
17.5
−12.5
5
0
1.25
23.75
−6.25
VREF
VCM+
VCM−
1/2 Reference Connection
COMMON-MODE RANGE
The common-mode range of the INA159 is a function of
supply voltage and reference. Where both pins, REF1 and
REF2, are connected together:
V CM) + (V)) ) 5[(V)) * VREF]
V CM* + (V*) * 5[V REF * (V*)]
(1)
(2)
V+
V−
5
0
5
17.5
−12.5
5
0
4.096
19.76
−10.24
5
0
2.5
23.75
−6.25
3.3
0
3.3
11.55
−8.25
3.3
0
2.5
13.55
−6.25
3.3
0
1.25
16.675
−3.125
7
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
Table 2. Input and Output Relationships for Various Reference and Connection Combinations
VREF
(V)
REF CONNECTION
5V
5
VOUT for VIN = 0
(V)
LINEAR VIN RANGE
(V)
USEFUL VOUT SWING
(V)
2.5
+10
0
−10
4.5
(±2V swing)
0.5
2.048
+10
0
−10
4.048
(±2V swing)
0.048
1.65
+10
0
−7.885
3.65
(−1.577V, +2V swing)
0.048
1.25
+10 (also +5)
0
−6 (also −5)
3.25
(−1.2V, +2V swing)
0.048
0.9
+10
0
−4.26
2.9
(−0.852V, +2V swing)
0.048
2.5
+10
0
−10
4.5
(±2V swing)
0.5
1.8
+10
0
−8.76
3.8
(−1.752V, +2V swing)
0.048
1.2
+10
0
−5.76
3.2
(−1.15V, +2V swing)
0.048
V+
−IN
100k
100kΩ
20k
20kΩ
SENSE
4.096
OUT
3.3
VIN
+IN
100kΩ
40kΩ
REF 2
VREF
2.5
40kΩ
REF 1
INA159
1.8
5V
V+
2.5
−IN
100kΩ
20kΩ
SENSE
OUT
1.8
VIN
+IN
100kΩ
40kΩ
40kΩ
REF 2
V REF
REF 1
INA159
1.2
8
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
C1
1000pF
VIN
+IN
100kΩ
40kΩ
40kΩ
V+
−IN
ADS8325
ADC
DCLOCK
CS
REF 2
GND
REF 1
INA159
Figure 3. Typical Application Circuit Interfacing to Medium-Speed, Single-Supply ADCs
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
100kΩ
40kΩ
40kΩ
REF 2
ADS8361 or
ADS7861
ADC
−IN
+IN
C1
1000pF
VIN
V+
DCLOCK
CS
GND
REF 1
INA159
Figure 4. Typical Application Circuit Interfacing to Medium-Speed, Single-Supply ADCs with
Pseudo-Differential Inputs (such as the ADS7861 and ADS8361)
9
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
VIN
+IN
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
V+
ADC
−IN
REF 2
GND
REF 1
INA159
a) Unipolar, Noninverting, G = 0.2
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
VIN
+IN
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
V+
ADC
−IN
REF 2
GND
REF 1
INA159
b) Bipolar, Noninverting, G = 0.2
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
+IN
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
REF 2
REF 1
INA159
VIN
c) Unipolar, Unity Gain
Figure 5. Basic INA159 Configurations
10
V+
ADC
−IN
GND
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SBOS333B − JULY 2005 − REVISED OCTOBER 2005
5V
V+
VIN−
−IN A
100kΩ
20kΩ
SENSE A
OUT A
100Ω
1000pF
VIN+
+IN A
100kΩ
40kΩ
40kΩ
REF 2A
REF 1A
INA159
VREF
V+
−IN B
100kΩ
20kΩ
REF
SENSE B
OUT B
V+
+IN
100Ω
−IN
5V
ADC
1000pF
GND
+IN B
100kΩ
40kΩ
40kΩ
REF 2B
REF 1B
INA159
Figure 6. Differential ADC Drive
11
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
INA159AIDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
INA159AIDGKT
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
INA159AIDGKTG4
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
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