TI TS3V330DR

SCDS162B – MAY 2004 – REVISED OCTOBER 2004
D Low Differential Gain and Phase
D
D
D
D
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
EN
S1D
S2D
DD
S1C
S2C
DC
RGY PACKAGE
(TOP VIEW)
S1A
S2A
DA
S1B
S2B
DB
VCC
D
D
16
2
1
16
15 EN
14 S2D
2
3
13 S2D
12 DD
4
5
6
7
8
9
11 S1C
10 S2C
DC
D
D
1
IN
D
IN
S1A
S2A
DA
S1B
S2B
DB
GND
GND
D
D
D
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
(DG = 0.82%, DP = 0.1 Degree Typ)
Wide Bandwidth (BW = 300 MHz Min)
Low Crosstalk (XTALK = −80 dB Typ)
Low Power Consumption
(ICC = 10 µA Max)
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron = 3 Ω Typ)
Rail-to-Rail Switching on Data I/O Ports
(0 to VCC)
VCC Operating Range From 3 V to 3.6 V
Ioff Supports Partial-Power-Down Mode
Operation
Data and Control Inputs Provide
Undershoot Clamp Diode
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Suitable for Both RGB and
Composite-Video Switching
description/ordering information
The TI TS3V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input.
When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch
is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the
data path of the multiplexer/demultiplexer.
ORDERING INFORMATION
QFN − RGY
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP (QSOP) − DBQ
TSSOP − PW
TVSOP − DGV
Tape and reel
TS3V330RGYR
Tube
TS3V330D
Tape and reel
TS3V330DR
Tape and reel
TS3V330DBQR
Tube
TS3V330PW
Tape and reel
TS3V330PWR
Tape and reel
TS3V330DGVR
TOP-SIDE
MARKING
TF330
TS3V330
TF330
TF330
TF330
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
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1
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
description/ordering information (continued)
Low differential gain and phase make this switch ideal for composite and RGB video applications. This device
has wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. This switch maintains isolation
during power off.
To ensure the high-impedance state during power up or power down, EN should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
EN
IN
INPUT/OUTPUT
D
FUNCTION
L
L
S1
D port = S1 port
L
H
S2
D port = S2 port
H
X
Z
Disconnect
PIN DESCRIPTIONS
PIN NAME
2
DESCRIPTION
S1, S2
Analog video I/Os
D
Analog video I/Os
IN
Select input
EN
Switch-enable input
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SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER DEFINITIONS
DESCRIPTION
PARAMETER
RON
Resistance between the D and S ports, with the switch in the ON state
IOZ
IOS
VIN
Output leakage current measured at the D and S ports, with the switch in the OFF state
VEN
CIN
Voltage at the EN pin
Short-circuit current measured at the I/O pins
Voltage at the IN pin
Capacitance at the control (EN, IN) inputs
COFF
Capacitance at the analog I/O port when the switch is OFF
CON
Capacitance at the analog I/O port when the switch is ON
VIH
VIL
Minimum input voltage for logic high for the control (EN, IN) inputs
VH
VIK
Hysteresis voltage at the control (EN, IN) inputs
VI
VO
Voltage applied to the D or S pins when D or S is the switch input
IIH
IIL
Input high leakage current of the control (EN, IN) inputs
II
IO
Ioff
Current into the D or S pins when D or S is the switch input
tON
tOFF
BW
Minimum input voltage for logic low for the control (EN, IN) inputs
I/O and control (EN, IN) inputs diode clamp voltage
Voltage applied to the D or S pins when D or S is the switch output
Input low leakage current of the control (EN, IN) inputs
Current into the D or S pins when D or S is the switch output
Output leakage current measured at the D or S ports, with VCC = 0
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned ON
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned OFF
Frequency response of the switch in the ON state measured at −3 dB
XTALK
Unwanted signal coupled from channel to channel. Measured in −dB. XTALK = 20 log VO/VI. This is a nonadjacent
crosstalk.
OIRR
Off isolation is the resistance (measured in −dB) between the input and output with the switch OFF.
DG
Magnitude variation between analog input and output pins when the switch is ON and the dc offset of composite video
signal varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is
from 0 to 0.714 V.
DP
Phase variation between analog input and output pins when the switch is ON and the dc offset of composite-video signal
varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is from 0
to 0.714 V.
ICC
Static power-supply current
ICCD
Variation of ICC for a change in frequency in the control (EN, IN) inputs
∆ICC
This is the increase in supply current for each control input that is at the specified voltage level, rather than VCC or GND.
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3
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
functional diagram (positive logic)
2
4
S1A
DA
3
S2A
DB
7
5
S1B
6
S2B
9
11
DC
10
DD
12
14
13
IN
1
15
Control
Logic
EN
4
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S1C
S2C
S1D
S2D
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
MAX
UNIT
VCC
VIH
Supply voltage
3
3.6
V
High-level control input voltage (EN, IN)
2
V
VIL
VANALOG
Low-level control input voltage (EN, IN)
0
VCC
0.8
V
Analog I/O voltage
0
VCC
V
TA
Operating free-air temperature
−40
85
°C
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
electrical characteristics over recommended
VCC = 3.3 V 0.3 V (unless otherwise noted)
PARAMETER
VIK
VH
EN, IN
IIH
IIL
EN, IN
operating
free-air
TEST CONDITIONS
temperature
range,
TYP†
MAX
UNIT
−1.8
V
MIN
VCC = 3 V,
IIN = −18 mA
VCC = 3.6 V,
VCC = 3.6 V,
VIN and VEN = VCC
VIN and VEN = GND
IOZ‡
VCC = 3.6 V,
VO = 0 to 3.6 V,
VI = 0,
Switch OFF
IOS§
VCC = 3.6 V,
VO = 0.5 VCC,
VI = 0,
Switch ON
Ioff
ICC
VCC = 0,
VCC = 3.6 V,
VO = 0 to 3.6 V,
II/O = 0,
VI = 0
Switch ON or OFF
VCC = 3.6 V,
VCC = 3.6 V,
VEN = GND,
One input at 3 V,
Other inputs at VCC or GND
VIN or VEN = 0,
f = 1 MHz
3.5
VI = 0,
f = 1 MHz,
Outputs open
10
Switch OFF
CON
VI = 0,
f = 1 MHz,
Outputs open
Switch ON
ron¶
VCC = 3 V
VI = 1 V,
VI = 2 V,
IO = 13 mA,
IO = 26 mA,
∆ICC
EN, IN
EN, IN
EN, IN
ICCD
CIN
EN, IN
150
D port
COFF
S port
D and S ports open,
mV
±1
µA
±1
µA
±1
µA
50
mA
VIN input switching 50% duty cycle
15
µA
10
µA
750
µA
0.45
mA/
MHz
pF
pF
5
17
pF
RL = 75 Ω
5
7
RL = 75 Ω
7
10
Ω
VI, VO, II, and IO refer to I/O pins.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, IOZ includes the input leakage current.
§ The IOS test is applicable to only one ON channel at a time. The duration of this test is less than one second.
¶ Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (D or S) terminals.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V, RL = 75 Ω, CL = 20 pF (unless otherwise noted) (see Figure 5)
FROM
(INPUT)
TO
(OUTPUT)
tON
S
tOFF
S
PARAMETER
dynamic characteristics over recommended
VCC = 3.3 V 0.3 V (unless otherwise noted)
PARAMETER
DG #
DP#
BW
MAX
D
2.5
6.5
ns
D
1.1
3.5
ns
free-air
TEST CONDITIONS
RL = 150 Ω,
f = 3.58 MHz, see Figure 6
RL = 150 Ω,
f = 3.58 MHz, see Figure 6
RL = 150 Ω, see Figure 7
XTALK
RL = 150 Ω,
f = 10 MHz,
OIRR
RL = 150 Ω,
f = 10 MHz, see Figure 9
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
# DG and DP are expressed in absolute magnitude.
6
TYP
operating
MIN
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RIN = 10 Ω, see Figure 8
• DALLAS, TEXAS 75265
temperature
UNIT
range,
TYP†
UNIT
0.82
%
0.1
Deg
300
MHz
−80
dB
−50
dB
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
0
0
−2
0.08
−0.2
0.07
−20
−0.4
−30
Gain
J
−4
−40
Y
Phase − Deg
0.06
J
Differental Gain
0.05
−0.6
0.04
Y
−0.8
−5
−50
−6
−60
−7
−70
−1.4
0.01
−8
−80
−1.6
0.00
−90
1000
−1.8
−9
1
10
100
Frequency − MHz
−1.0
0.03
−1.2
−0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VBIAS − V
Y
Gain 3 dB at 400 MHz
J
Phase at 3-dB Frequency, −38.28 Degrees
Y
Differential Gain at 0.714 V, −0.81%
J
Differential Phase at 0.714 V, 0.06 Degree
Figure 1. Gain/Phase vs Frequency
Figure 2. Differential Gain/Phase vs VBIAS
0
160
0
250
−10
140
−20
200
−40
−20
Phase
−30
100
J
−40
80
−50
Y
−60
Off Isolation
60
Crosstalk − dB
120
Phase − Deg
Off Isolation − dB
0.02
Differental Phase
40
20
−70
1
10
0
1000
100
Frequency − MHz
Y
Off
Y Isolation
Differential
at 10Gain
Mhz,at−50.08
0.714 V,
dB−0.81%
J
Phase
J
Differential
at 10 MHz,Phase
87.8 Degrees
at 0.714 V, 0.06 Degrees
Figure 3. Off Isolation vs Frequency
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150
−60
J
100
−80
Y
50
Crosstalk
0
−100
−120
−50
−140
−100
−160
−150
−180
−200
−200
−80
Phase
1
100
10
Frequency − MHz
Y
Crosstalk at 10 MHz, −80 dB
J
Phase at 10 MHz, 100.62 Degrees
Phase − Deg
Gain − dB
−3
0.0
−10
Differential Gain − %
Phase
−1
Differential Phase − Deg
OPERATING CHARACTERISTICS
−250
1000
Figure 4. Crosstalk vs Frequency
• DALLAS, TEXAS 75265
7
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
IN
50 Ω
VG1
S1
DUT
VS1
VO
D
S2
CL
(see Note A)
EN
RL
VS2
TEST
VCC
RL
CL
VS1
VS2
tON
3.3 V ± 0.3 V
3.3 V ± 0.3 V
75
75
20
20
GND
VCC
VCC
GND
tOFF
3.3 V ± 0.3 V
3.3 V ± 0.3 V
75
75
20
20
GND
VCC
VCC
GND
TEST CIRCUIT
VCC
Output
Control
(VIN)
50%
50%
0V
tOFF
tON
Analog Output
Waveform
(VO)
90%
90%
VOH
0V
VOLTAGE WAVEFORMS
tON AND tOFF TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Test Circuit and Voltage Waveforms
8
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SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
VBIAS
BIAS
Network Analyzer
(HP8753ES)
Sawtooth
Waveform Generator
P1
P2
VCC
S1A
DA
RL = 150 Ω
IN
DUT
VIN
EN
VEN
NOTE: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase, literature
number SLOA040.
Figure 6. Test Circuit for Differential Gain/Phase Measurement
Differential gain and phase are measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and
DA is the input, the output is measured at S1A.
HP8753ES setup
Average = 20
RBW = 300 Hz
ST = 1.381 s
P1 = −7 dBM
CW frequency = 3.58 MHz
sawtooth waveform generator setup
VBIAS = 0 to 1 V
Frequency = 0.905 Hz
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9
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VCC
S1A
DA
RL = 150 Ω
IN
DUT
VIN
EN
VEN
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and DA is
the input, the output is measured at S1A. All unused analog I/O ports are left open.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
10
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SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VCC
DA
S1A
RL = 150 Ω
IN
50 Ω†
VIN
EN
DUT
VEN
DB
S1B
RIN = 10 Ω
RL = 150 Ω
† A 50-Ω termination resistor is needed for the network analyzer.
Figure 8. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VIN = 0, VEN = 0, and DA
is the input, the output is measured at S1B. All unused analog input (D) ports and output (S) ports are connected to
GND through 10-Ω and 50-Ω pulldown resistors, respectively.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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11
SCDS162B – MAY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VCC
S1A
DA
RL = 150 Ω
IN
DUT
VIN
S2A
EN
RL = 150 Ω
50 Ω†
VEN
† A 50-Ω termination resistor is needed for the Network Analyzer.
Figure 9. Test Circuit for Off Isolation (OIRR)
Off isolation is measured at the output of the OFF channel. For example, when VIN = VCC, VEN = 0, and DA is the input,
the output is measured at S1A. All unused analog input (D) ports are left open, and output (S) ports are connected
to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
12
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MSOI004E JANUARY 1995 − REVISED MAY 2002
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
0.005 (0,13)
13
24
0.244 (6,20)
0.228 (5,80)
0.157 (3,99)
0.150 (3,81)
0.008 (0,20) NOM
Gauge Plane
1
12
0.010 (0,25)
A
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
28
A MAX
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
AB
AD
AE
AF
DIM
D
4073301/F 02/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
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1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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