TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 TM DIGITAL AMPLIFIER POWER STAGE FEATURES • 100-W RMS Power (BTL) Into 4 Ω With Less Than 10% THD+N 80-W RMS Power (BTL) Into 4 Ω With Less Than 0.2% THD+N 0.09% THD+N at 1 W Into 4 Ω Power Stage Efficiency Greater Than 90% Into 4-Ω Load Self-Protecting Design Industrial Temperature Rating 36-Pin PSOP3 Package 3.3-V Digital Interface EMI Compliant When Used With Recommended System Design • • • • • • • • APPLICATIONS • • DVD Receiver Home Theatre • • Mini/Micro Component Systems Internet Music Appliance DESCRIPTION The TAS5121I is a high-performance, digital-amplifier power stage designed to drive a 4-Ω speaker up to 100 W. The TAS5121I is rated for operation at industrial temperatures. The device incorporates PurePath Digital™ technology and can be used with a TI audio pulse-width modulation (PWM) processor and a simple passive demodulation filter to deliver high-quality, high-efficiency, digital-audio amplification. The efficiency of this digital amplifier can be greater than 90%, depending on the system design. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5121I, safeguarding the device and speakers against fault conditions that could damage the system. TOTAL HARMONIC DISTORTION + NOISE vs POWER 90 RL = 4 Ω TC = 75°C Gain = 3 dB 80 4Ω 70 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 UNCLIPPED OUTPUT POWER vs H-BRIDGE VOLTAGE 1 6Ω 0.1 4Ω 60 6Ω 50 40 30 20 10 8Ω 0.01 0.1 8Ω 0 1 10 100 P − Power − W 0 4 8 12 16 20 24 28 32 PVDD_X − H-Bridge Voltage − V G001 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFOMATION Terminal Assignment The TAS5121I is offered in a thermally enhanced 36-pin PSOP3 (DKD) package. The DKD package has the thermal pad on top. DKD PACKAGE (TOP VIEW) GND PWM_BP GND RESET DREG_RTN GVDD M3 DREG DGND M1 M2 DVDD SD DGND OTW GND PWM_AP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GVDD_B GVDD_B GND BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GND GVDD_A GVDD_A ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) DVDD TO DGND –0.3 V to 4.2 V GVDD_x TO GND 14.2 V PVDD_X TO GND (dc voltage) 33.5 V PVDD_X TO GND (2) OUT_X TO GND (dc voltage) OUT_X TO GND (2) 48 V BST_X TO GND (dc voltage) 46 V BST_X TO GND (2) 53 V PWM_XP, RESET, M1, M2, M3, SD, OTW TJ (1) (2) 2 48 V 33.5 V –0.3 V to DVDD + 0.3 V Maximum junction temperature range –40°C to 150°C Storage temperature –40°C to 125°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The duration should be less than 100 ns (see application note SLEA025). TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 ORDERING INFORMATION TA PACKAGE TRANSPORT MEDIA DESCRIPTION –40°C to 85°C TAS5121IDKD Tube 36-pin PSOP3 –40°C to 85°C TAS5121IDKDR Tape and reel 36-pin PSOP3 PACKAGE DISSIPATION RATINGS (1) PACKAGE RθJC (°C/W) 36-Pin DKD PSOP3 0.85 RθJA (°C/W) See (1) The TAS5121I package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the devices with the pad exposed to ambient air as the only heat sinking of the device. Therefore RθJA, a system parameter that characterizes the thermal treatment, is provided in the Thermal Information section. This information should be used as a reference to calculate the heat dissipation ratings for a specific application. Terminal Functions TERMINAL NAME DKD FUNCTION (1) DESCRIPTION BST_A 22 P High-side bootstrap (BST) supply, external resistor and capacitor to OUT_A required BST_B 33 P High-side bootstrap (BST) supply, external resistor and capacitor to OUT_B required DGND 9, 14 P I/O reference ground DREG 8 P Digital supply-voltage regulator-decoupling pin, 1-µF capacitor connected to DREG_RTN DREG_RTN 5 P Decoupling return pin DVDD 12 P I/O reference supply input: 100 Ω to DREG, decoupled to GND, 0.1-µF capacitor connected to GND 1, 3, 16, 18, 21, 27, 28, 34 P Power ground, connected to system GND GND GVDD 6 P Local GVDD decoupling pin GVDD_A 19, 20 P Gate-drive input voltage GVDD_B 35, 36 P Gate-drive input voltage M1 10 I Protection-mode selection pin, connect to GND M2 11 I Protection-mode selection pin, connect to DREG M3 7 I Output-mode selection pin; connect to GND OTW 15 O Overtemperature warning output, open-drain with internal pullup, asserted low when temperature exceeds 115°C OUT_A 25, 26 O Output, half-bridge A OUT_B 29, 30 O Output, half-bridge B PVDD_A 23, 24 P Power supply input for half-bridge A PVDD_B 31, 32 P Power supply input for half-bridge B PWM_AP 17 I PWM input signal, half-bridge A PWM_BP 2 I PWM input signal, half-bridge B RESET 4 I Reset signal, active-low SD 13 O Shutdown signal for half-bridges A and B (open-drain with internal pullup) (1) I = input, O = Output, P = Power 3 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 FUNCTIONAL BLOCK DIAGRAM GVDD_A GVDD_A BST_A PVDD_A OCH DREG Gate DVDD DREG Drive PWM_AP PWM Receiver Timing Control GVDD_A and Protection DGND OUT_A Gate Drive GND OCL GVDD_B RESET GVDD_B BST_B PVDD_B OCH DREG DVDD DVDD PWM_BP Gate Drive DREG PWM Receiver Timing Control GVDD_B and Protection DGND OUT_B Gate Drive GND OCL GVDD DREG OTW SD M1 M2 M3 4 DREG Protection Logic OT and UVP DREG DREG Internally Connected to GVDD_x DREG_RTN TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS DVDD Digital supply (1) Relative to DGND GVDD_x Supply for internal gate drive and logic regulators Relative to GND PVDD_x Half-bridge supply Relative to GND, RL= 4 Ω TJ Junction temperature (1) MIN NOM MAX UNIT 3 3.3 3.6 V 10.8 12 13.2 V 0 30.5 0 32 V 125 °C It is recommended for DVDD to be connected to DREG via a 100-Ω resistor. ELECTRICAL CHARACTERISTICS PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs= 384 kHz, TAS5026 PWM processor, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS OVER TEMPERATURE TCase= 75°C UNITS MIN/TYP/ MAX RL = 4 Ω, THD = 10%, AES17 filter 100 W Typ RL = 4 Ω, THD = unclipped, AES17 filter 80 W Typ RL = 8 Ω, THD = unclipped, AD mode 44 W Typ PO = 1 W/channel, RL = 4 Ω, AES17 filter 0.09 % Typ PO = 10 W/channel, RL = 4 Ω, AES17 filter 0.15 % Typ PO = 80 W/channel, RL = 4 Ω, AES17 filter 0.19 % Typ TA=25°C TA=25°C AC PERFORMANCE, BTL Mode, 1 kHz PO Output power THD+N Total harmonic distortion + noise Vn Output-integrated noise voltage A-weighted, RL = 4 Ω, 20 Hz to 20 kHz, AES17 filter 300 µV Max SNR Signal-to-noise ratio A-weighted, AES17 filter 95 dB Typ DR Dynamic range f = 1 kHz, –60 dB, A-weighted, AES17 filter 95 dB Typ INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION V Min V Max 30 mA Max 1 5 mA Max DREG Voltage regulator Io = 1 mA 3.3 IGVDD_x Total GVDD supply current, operating fS = 384 kHz, no load, 50% duty cycle 24 IDVDD DVDD supply current, operating fS = 384 kHz, no load OUTPUT STAGE MOSFETs RDSon,LS Forward on-resistance, low side TJ = 25°C 120 132 mΩ Max RDSon,HS Forward on-resistance, high side TJ = 25°C 120 132 mΩ Max 7 V Min INPUT/OUTPUT PROTECTION Vuvp,G Undervoltage protection limit, GVDD V Max OTW Overtemperature warning Static 115 °C Typ OTE Overtemperature error Static 150 °C Typ OC Overcurrent protection See 9.5 A Min (1) 7.6 (1). 8.2 To optimize device performance and prevent overcurrent (OC) protection activation, the demodulation filter must be designed with special care. See Demodulation Filter Design in the Application Information section of this data sheet and consider the recommended inductors and capacitors for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5121I. 5 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs= 384 kHz, TAS5026 PWM processor, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25°C OVER TEMPERATURE TA=25°C TCase= 75°C UNITS MIN/TYP/ MAX STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS, AND OUTPUT MODE SELECTION PINS VIH High-level input voltage VIL Low-level input voltage Leakage Input leakage current 2 V Min DVDD V Max Max 0.8 V –10 µA Min 10 µA Max 22 kΩ Min 0.4 V Max OTW/SHUTDOWN (SD) Internal pullup resistor from OTW and SD to DVDD VOL Low-level output voltage 32 IO = 1 mA TYPICAL APPLICATION CONFIGURATION USED WITH TAS5026 PWM PROCESSOR TAS5121IDKD 1 2 PWM_AP_1 3 4 5 6 100 nF 7 8 9 1 µF 100 Ω 10 11 12 13 100 nF 14 15 16 PWM_BP_1 17 18 GVDD_B PWM_BP GVDD_B RESET 34 GND 33 1Ω 100 nF BST_B 2.7 Ω 32 PVDD_B GVDD PVDD_B 31 75 nH LPCB‡ 33 nF 10 µH 30 M3 OUT_B DREG OUT_B 29 DGND GND M1 GND 28 TVS Zener† 27 TVS Zener† 26 M2 OUT_A DVDD OUT_A DGND 22 Ω 35 DREG_RTN SD Gate-Drive Power Supply 36 GND GND 1 µF 10 µH 1 µF 4.7 kΩ H-Bridge Power Supply 1000 µF 1 µF 4.7 kΩ 25 33 nF 24 PVDD_A PVDD_A OTW BST_A GND GND GVDD_A GND GVDD_A 2.7 Ω 22 21 PWM_AP 75 nH LPCB‡ 23 20 1Ω 100 nF 22 Ω 19 33 µF 1 µF Microcontroller † ‡ Voltage suppressor diodes: 1SMA33CAT3 LPCB : Track in the PCB (1 mm wide and 50 mm long) S0015−01 6 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 TOTAL HARMONIC DISTORTION + NOISE vs POWER 90 RL = 4 Ω TC = 75°C Gain = 3 dB 80 4Ω 70 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 UNCLIPPED OUTPUT POWER vs H-BRIDGE VOLTAGE 1 6Ω 0.1 4Ω 60 6Ω 50 40 30 20 8Ω 10 8Ω 0 0.01 0.1 1 10 0 100 4 P − Power − W 8 12 16 20 24 28 32 PVDD_X − H-Bridge Voltage − V G001 Figure 1. Figure 2. POWER LOSS vs TOTAL OUTPUT POWER UNCLIPPED OUTPUT POWER vs CASE TEMPERATURE 100 14 90 12 80 PO − Output Power − W Power Loss − W 10 8 6 4 70 60 50 40 30 20 2 10 0 0 10 20 30 40 50 60 PO(Total) − Total Output Power − W Figure 3. 70 80 0 −40 −20 0 20 40 60 80 TC − Case Temperature − °C 100 120 G004 Figure 4. 7 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 EFFICIENCY vs TOTAL OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 100 THD+N − Total Harmonic Distortion + Noise − % 10 90 80 η − Efficiency − % 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 RL = 4 Ω TC = 75°C 1 75 W 0.1 10 W 1W 0.01 20 80 100 PO(Total) − Total Output Power − W Figure 5. Figure 6. AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 PO = 1 W TC = 75°C −20 0.3 8Ω −40 0.2 Amplitude − dBr A Amplitude − dBr A 10k 20k G006 0.5 0.4 1k f − Frequency − Hz 6Ω 0.1 0.0 −0.1 −0.2 4Ω −60 −80 −100 −120 −0.3 −140 −0.4 −0.5 10 −160 100 1k f − Frequency − Hz Figure 7. 8 10k 20k 0 2 4 6 8 10 12 14 f − Frequency − kHz Figure 8. 16 18 20 22 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 THEORY OF OPERATION POWER SUPPLIES This power device requires only two power supply voltages: GVDD_x and PVDD_x. GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply. GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power supply, 3.3 V, for the TAS5121I internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1-µF capacitor. PVDD_x is the H-bridge power supply. Two power pins are provided for each half-bridge due to the high current density. It is important to follow the circuit and PCB layout recommendations for the design of the PVDD_x connection. For component suggestions, see the Typical Application Configuration Used With TAS5026 PWM Processor section in this document. Following these recommendations is important because they influence key system parameters such as EMI, idle current, and audio performance. When GVDD_x is applied, while RESET is held low, the error latches are cleared, SHUTDOWN is set high, and the outputs are held in a high-impedance state. The bootstrap (BST) capacitor is charged by the current path through the internal BST diode and external resistors placed on the PCB from each OUT_x pin to ground. Ideally, PVDD_x is applied after GVDD_x. When GVDD_x and PVDD_x are applied, the TAS5121I is ready for operation. PWM input signals can then be applied any time during the power-on sequence, but they must be active and stable before RESET is set high. Recommendations for Powering Up > 1 ms > 1 ms RESET GVDD PVDD_X PWM_xP Table 1 describes the input conditions and the output states of the device. Table 1. Input/Output States INPUTS OUTPUTS RESET PWM_AP PWM_BP SHUTDOWN OUT_A OUT_B CONDITION DESCRIPTION X X X 0 Hi-Z Hi-Z Shutdown 0 X X 1 Hi-Z Hi-Z Reset 1 0 0 1 GND GND 1 0 0 1 PVDD PVDD Normal 1 0 1 1 GND PVDD Normal 1 1 1 1 PVDD PVDD Reserved After the previously mentioned conditions are met, the device output begins. If PWM_AP is equal to a high and PMW_BP is equal to a low, the high-side MOSFET in the A half-bridge of the output H-bridge conducts while the 9 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 THEORY OF OPERATION (continued) low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is referenced to the drain of the low-side MOSFET, a bootstrapped capacitor is used to eliminate the need for additional high-voltage power supplies. Under this condition, the opposite is true for the B half-bridge of the output H-bridge. The low-side MOSFET in the B half-bridge conducts while the high-side MOSFET is not conducting; therefore, the load connected between the OUT_A and OUT_B pins has PVDD applied to it from the A side while ground is applied from the B side for the period of time PWM_AP is high and PWM_BP is low. Furthermore, when the PWM signals change to the condition where PWM_AP is low and PWM_BP is high, the opposite condition exists. A constant high level is not permitted on the PWM inputs. This condition causes the BST capacitors to discharge and can cause device damage. A digitally controlled dead-time circuit controls the transitions between the high-side and low-side MOSFETs to ensure that both devices in each half-bridge are not conducting simultaneously. POWERING DOWN For power down of the TAS5121I, an opposite approach is necessary. The RESET must be asserted LOW before the valid PWM signal is removed. PRECAUTION The TAS5121I must always start up in the high-impedance (Hi-Z) state. In this state, the BST capacitor is precharged by a resistor on each PWM output node to ground. See Typical Application Configuration Used With TAS5026 PWM Processor. This ensures that the TAS5121I is ready for receiving PWM pulses, indicating either HIGH- or LOW-side turnon after RESET is deasserted to the power stage. With the following pulldown resistor and BST capacitor size, the BST charge time is: • C = 33 nF, R = 4.7 kΩ • R × C × 5 = 775.5 µs After GVDD has been applied, it takes approximately 800 µs to fully charge the BST capacitor. During this time, RESET must be kept low. After approximately 1 ms, the power-stage BST is charged and ready. RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the device. Valid PWM signals are switching PWM signals with a frequency between 350-400 kHz. A constant HIGH level on PWM+ forces the high-side MOSFET ON until it eventually runs out of BST capacitor energy. Putting the device in this condition should be avoided. In practice, this means that the DVDD-to-PWM processor (modulator) should be stable, and initialization should be completed before RESET is deasserted to the TAS5121I. CONTROL I/O SHUTDOWN PIN: SD The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other front-end device. The pin is open-drain with an internal pullup to DVDD. The logic output is, as shown in Table 2, a combination of the device state and RESET input. Table 2. Error Indication (1) 10 SD RESET DESCRIPTION 0 0 Reserved 0 1 Device in protection mode, i.e., UVP and/or OC and/or OT error 1 (1) 0 Device set high-impedance (Hi-Z), SD forced high 1 1 Normal operation SD is independent from RESET. This is desirable to maintain compatibility with some TI PWM modulators. TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 OVERTEMPERATURE WARNING PIN: OTW The OTW pin gives a temperature warning signal when temperature exceeds the set limit, as shown in Table 3. The pin is of the open-drain type with an internal pullup to DVDD. Table 3. OTW Temperature Indication OTW DESCRIPTION 0 Junction temperature higher than 115°C 1 Junction temperature lower than 115°C OVERALL REPORTING The SD pin, together with the OTW pin, gives chip state information as described in Table 4. Table 4. Error Signal Decoding OTW SD 0 0 Overtemperature error (OTE) DESCRIPTION 0 1 Overtemperature warning (OTW) 1 0 Overcurrent (OC) or undervoltage (UVP) error 1 1 Normal operation, no errors/warnings CHIP PROTECTION The TAS5121I protection function is generally implemented in a closed-loop control system with, for example, a system controller. The TAS5121I contains three individual systems protecting the device against fault conditions. All of the error events result in the output stage being set in a high-impedance state (Hi-Z) for maximum protection of the device and connected equipment. The device can be recovered by toggling RESET low and then high, after all errors are cleared. It is recommended that if the error persists, the device is held in reset until user intervention clears the error. OVERCURRENT (OC) PROTECTION The device has individual current protection on both high-side and low-side power-stage FETs. The OC protection works only with the demodulation filter present at the output. See Filter Demodulation Design in the Application Information section of this data sheet for design constraints. OVERTEMPERATURE (OT) PROTECTION A dual-temperature protection system asserts a warning signal when the device junction temperature exceeds 115°C and shuts down the device when the junction temperature exceeds 150°C. The OT protection circuit is shared by both half-bridges. UNDERVOLTAGE PROTECTION (UVP) Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system protects the device under fault power-up and power-down situations by shutting the device down. The UV protection circuits are shared by both half-bridges. RESET FUNCTION The reset has two functions: • Reset the power stage after a latched error event. • Hard mute—when RESET is asserted, the power stage stops switching. In protection modes where the reset input functions as the means to re-enable operation after an error event, the error latch is cleared on the falling edge of RESET, and normal operation is resumed on the rising edge of RESET. 11 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 PROTECTION MODE LATCHED SHUTDOWN ON ALL ERRORS In latched shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin. MODE PINS SELECTION The protection mode is selected by connecting M1/M2 to DREG or DGND according to Table 5. Table 5. Protection Mode Selection M1 M2 0 0 Reserved PROTECTION MODE 0 1 Latched shutdown on all errors 1 0 Reserved 1 1 Reserved The output configuration mode is selected by connecting the M3 pin to DREG or DGND according to Table 6. Table 6. Output Mode Selection M3 12 OUTPUT MODE 0 Bridge-tied load output stage (BTL) 1 Reserved TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION DEMODULATION FILTER DESIGN The TAS5121I amplifier outputs are driven by high-current DMOS transistors in an H-bridge configuration. These transistors are either off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. TAS5121I Output A L C1 R(Load) C2 Output B L S0016−01 Figure 9. Demodulation Filter The main purpose of the demodulation filter is to attenuate the high-frequency components of the output signals that are out of the audio band. Design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to ensure proper operation of the OC protection circuit and meet the device THD+N specification, the selection of the inductors used in the output filter should be carefully considered. The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver approximately 5 µH of inductance at 15 A. If this rule is observed, the TAS5121I should not have distortion issues due to the output inductors. This prevents device damage due to overcurrent conditions because of inductor saturation in the output filter. Another parameter to be considered is the idle current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05. If this specification is not met, idle current increases. In general, 10-µH inductors suffice for most applications. The frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to deviate from 10 µH. The graphs in Figure 10 display the inductance-versus-current characteristics of two inductors that are suggested for use with the TAS5121I. 13 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION (continued) INDUCTANCE vs CURRENT 11 DBF1310A 10 L − Inductance − µH 9 DASL983XX−1023 8 7 6 5 4 0 5 10 15 I − Current − A Figure 10. Inductance Saturation The selection of the capacitors that are placed from the output of each inductor to ground is simple. To complete the output filter, use a 1-µF capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD_x). This capacitor should be a good quality polyester dielectric. THERMAL INFORMATION The following information is provided as an example. The thermally enhanced package provided with the TAS5121I is designed to be interfaced directly to a heatsink using a thermal interface compound (for example, Wakefield Engineering type 126 thermal grease.) The heatsink then absorbs heat from the ICs and transfers it to the ambient air. If the heatsink is carefully designed, this process can reach equilibrium and heat can be continually removed from the ICs without device overtemperature shutdown. Because of the efficiency of the TAS5121I, heatsinks are smaller than those required for linear amplifiers of equivalent performance. RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with roughly the following components: • RθJC (the thermal resistance from junction to case, or in this case the metal pad) • Heatsink compound thermal resistance • Heatsink thermal resistance The thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W). The area thermal resistance of the example thermal grease with a 0.001-inch-thick layer is about 0.054 °C-in2/W. The approximate exposed pad area is as follows: 36-pin PSOP3 0.116 in2 Dividing the example thermal grease area resistance by the area of the pad gives the actual resistance through the thermal grease for the device: 14 TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION (continued) 36-pin PSOP3 0.47 °C/W The thermal resistance of thermally conductive pads is generally higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance and should not be used with this package. Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus, for a single monaural IC, the system RθJA = RθJC + thermal grease resistance + heatsink resistance. Table 7 indicates modeled parameters for one TAS5121I IC on a heatsink. The junction temperature is set at 110°C while delivering 70 W RMS into 4-Ω loads with no clipping. It is assumed that the thermal grease is about 0.001 inch thick (this is critical). Table 7. Example of Thermal Simulation 36-PIN PSOP3 Ambient temperature 25°C Power to load 70 W Delta T inside package 5.5°C Delta T through thermal grease 3.2°C Required heatsink thermal resistance 11.0°C/W Junction temperature 110°C System RθJA 12.3°C/W RθJA * power dissipation 85°C RθJC 0.85°C/W As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases to 0.002 inches thick, the required heatsink thermal resistance increases to 5.2°C/W for the PSOP3 package. REFERENCES 1. 2. 3. 4. Digital Audio Measurements application report – TI (SLAA114) PowerPAD™ Thermally Enhanced Package technical brief – TI (SLMA002) System Design Considerations for True Digital Audio Power Amplifiers application report – TI (SLAA117) Voltage Spike Measurement Technique and Specification application note – TI (SLEA025) 15 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TAS5121IDKD ACTIVE SSOP DKD 36 29 Pb-Free (RoHS) CU NIPDAU Level-4-260C-72 HR/ Level-2-220C-1 YEAR TAS5121IDKDE4 ACTIVE SSOP DKD 36 29 Pb-Free (RoHS) CU NIPDAU Level-4-260C-72 HR/ Level-2-220C-1 YEAR TAS5121IDKDR ACTIVE SSOP DKD 36 500 Pb-Free (RoHS) CU NIPDAU Level-4-260C-72 HR/ Level-2-220C-1 YEAR TAS5121IDKDRE4 ACTIVE SSOP DKD 36 500 Pb-Free (RoHS) CU NIPDAU Level-4-260C-72 HR/ Level-2-220C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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