TI SNJ54LVTH574FK

SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SN54LVTH574 . . . FK PACKAGE
(TOP VIEW)
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
1D
2D
3D
4D
5D
6D
7D
8D
20
2D
1D
OE
VCC
1
3D
4D
5D
6D
7D
19 1Q
18 2Q
2
3
17 3Q
16 4Q
4
5
15 5Q
14 6Q
6
7
13 7Q
12 8Q
8
9
10
11
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
20
VCC
1
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN74LVTH574 . . . RGY PACKAGE
(TOP VIEW)
SN54LVTH574 . . . J OR W PACKAGE
SN74LVTH574 . . . DB, DW, NS,
OR PW PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
D
CLK
D
D
OE
D
D Bus Hold on Data Inputs Eliminates the
GND
D
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
1Q
D Support Mixed-Mode Signal Operation (5-V
description/ordering information
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
QFN − RGY
SN74LVTH574RGYR
Tube
SN74LVTH574DW
Tape and reel
SN74LVTH574DWR
SOP − NS
Tape and reel
SN74LVTH574NSR
LVTH574
SSOP − DB
Tape and reel
SN74LVTH574DBR
LXH574
Tube
SN74LVTH574PW
Tape and reel
SN74LVTH574PWR
TSSOP − PW
VFBGA − GQN
VFBGA − ZQN (Pb-free)
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tape and reel
SOIC − DW
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LXH574
LVTH574
LXH574
SN74LVTH574GQNR
Tape and reel
SN74LVTH574ZQNR
LXH574
CDIP − J
Tube
SNJ54LVTH574J
SNJ54LVTH574J
CFP − W
Tube
SNJ54LVTH574W
SNJ54LVTH574W
LCCC − FK
Tube
SNJ54LVTH574FK
SNJ54LVTH574FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
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1
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of
the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
SN74LVTH574 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
terminal assignments
4
1
2
3
4
A
A
1D
OE
1Q
B
B
3D
3Q
VCC
2D
C
C
5D
4D
5Q
4Q
D
D
7D
7Q
6D
6Q
E
E
GND
8D
CLK
8Q
FUNCTION TABLE
(each flip-flop)
INPUTS
2
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
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2Q
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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3
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 5)
SN54LVTH574
SN74LVTH574
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
−24
−32
mA
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−55
High-level input voltage
2
Low-level output current
Outputs enabled
2
V
−40
V
µs/V
200
125
V
85
°C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VCC = 2.7 V,
IOH = −8 mA
IOH = −24 mA
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
Control inputs
II
Data inputs
Ioff
II(hold)
VCC = 0 or 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V
VCC = 0,
Data inputs
SN54LVTH574
TYP†
MAX
TEST CONDITIONS
MIN
SN74LVTH574
TYP†
MAX
MIN
−1.2
VCC−0.2
2.4
−1.2
V
2
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
0.55
10
10
VI = VCC or GND
VI = VCC
±1
±1
1
1
VI = 0
VI or VO = 0 to 4.5 V
−5
VCC = 3.6 V‡,
VCC = 3.6 V,
VI = 0 to 3.6 V
VO = 3 V
V
0.55
IOL = 64 mA
VI = 5.5 V
VCC = 3 V
V
VCC−0.2
2.4
IOH = −32 mA
IOL = 100 µA
VI = 0.8 V
VI = 2 V
UNIT
A
µA
−5
±100
75
75
−75
−75
µA
µA
±500
5
5
µA
−5
−5
µA
IOZPU
VCC = 3.6 V,
VO = 0.5 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care
±100*
±100
µA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care
±100*
±100
µA
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
IOZH
IOZL
Outputs high
Outputs low
Outputs disabled
∆ICC§
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Co
5
5
0.19
0.19
0.2
0.2
mA
mA
3
3
pF
7
7
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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5
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH574
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
Clock frequency
tsu
th
Setup time, data before CLK↑
MAX
VCC = 2.7 V
MIN
150
Pulse duration, CLK high or low
Hold time, data after CLK↑
SN74LVTH574
VCC = 3.3 V
± 0.3 V
MAX
MIN
150
MAX
VCC = 2.7 V
MIN
150
UNIT
MAX
150
MHz
3.3
3.3
3.3
3.3
ns
2
2.4
2
2.4
ns
0.9
0.9
0.3
0
ns
switching characteristics over recommended free-air temperature, CL = 50 pF (unless otherwise
noted) (see Figure 1)
SN54LVTH574
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
VCC = 2.7 V
MAX
150
CLK
Q
OE
Q
OE
Q
SN74LVTH574
MIN
MAX
150
MIN
TYP†
VCC = 2.7 V
MAX
150
MIN
MHz
4.9
5.9
1.8
3
4.5
5.3
1.7
4.9
5.5
1.8
3
4.5
5.3
1.4
5.1
6.5
1.5
3.2
4.8
5.9
1.4
5.1
6.1
1.5
3.5
4.8
5.9
1
5.9
6.4
2
3.5
4.8
5.1
0.8
4.8
5.3
2
3.2
4.4
4.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
150
1.7
† All typical values are at VCC = 3.3 V, TA = 25°C.
6
VCC = 3.3 V
± 0.3 V
ns
ns
ns
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
2.7 V
1.5 V
Input
Output
Control
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
tPLZ
3V
1.5 V
tPZH
tPLH
tPHL
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPHL
tPLH
1.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
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11-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9583201Q2A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
5962-9583201QRA
ACTIVE
CDIP
J
20
1
None
Call TI
Level-NC-NC-NC
5962-9583201QSA
ACTIVE
CFP
W
20
1
None
Call TI
Level-NC-NC-NC
5962-9583201VRA
ACTIVE
CDIP
J
20
1
None
Call TI
Level-NC-NC-NC
5962-9583201VSA
ACTIVE
CFP
W
20
1
None
Call TI
Level-NC-NC-NC
SN74LVTH574DBLE
OBSOLETE
SSOP
DB
20
None
Call TI
Call TI
SN74LVTH574DBR
ACTIVE
SSOP
DB
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LVTH574DW
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LVTH574DWR
ACTIVE
SOIC
DW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LVTH574GQNR
ACTIVE
VFBGA
GQN
20
1000
None
SNPB
SN74LVTH574NSR
ACTIVE
SO
NS
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LVTH574PW
ACTIVE
TSSOP
PW
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LVTH574PWLE
OBSOLETE
TSSOP
PW
20
None
Call TI
SN74LVTH574PWR
ACTIVE
TSSOP
PW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LVTH574RGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVTH574ZQNR
ACTIVE
VFBGA
ZQN
20
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
SNJ54LVTH574FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54LVTH574J
ACTIVE
CDIP
J
20
1
None
Call TI
Level-NC-NC-NC
SNJ54LVTH574W
ACTIVE
CFP
W
20
1
None
Call TI
Level-NC-NC-NC
Level-1-240C-UNLIM
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2005
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MCFP006B − JANUARY 1995 − REVISED JULY 2003
W (R-GDFP-F20)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.300 (7,62)
0.245 (6,22)
0.045 (1,14)
0.026 (0,66)
0.009 (0,23)
0.004 (0,10)
0.100 (2,54)
0.045 (1,14)
0.320 (8,13) MAX
1
0.022 (0,56)
0.015 (0,38)
20
0.050 (1,27)
0.540 (13,72)
MAX
0.005 (0,13) MIN
4 Places
10
11
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
4040180-4 /D 07/03
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only.
Falls within Mil-Std 1835 GDFP2-F20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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