ETC IS65C256

ISSI
®
IS65C256
32K x 8 LOW POWER CMOS
STATIC RAM
MARCH 2004
DESCRIPTION
FEATURES
The ISSI IS65C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's highperformance, low power CMOS technology.
• High-speed access time: 20 ns
• Low active power: 200 mW (typical)
• Low standby power:
250 µW (typical) CMOS standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
• Temperature Offerings:
Option A1: –40oC to +85oC
Option A2: –40oC to +105oC
Option A3: –40oC to +125oC
When CS is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CS) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS65C256 is Packaged in the JEDEC Standard 28-Pin
SOP and 28-Pin TSOP (Type I).
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CS
OE
WE
CONTROL
CIRCUIT
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
1
ISSI
IS65C256
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP
32-Pin TSOP (Type 1)
A14
1
28
VDD
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CS
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
PIN DESCRIPTIONS
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
1
2
3
4
5
6
7
®
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
TRUTH TABLE
A0-A14
Address Inputs
Mode
CS
Chip Select Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Not Selected
(Power-down)
Output Disabled
Read
Write
VDD
Power
GND
Ground
WE
CS
OE I/O Operation
X
H
X
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
VDD Current
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
ISSI
IS65C256
®
OPERATING RANGE
Range
A1
A2
A3
Ambient Temperature
–40°C to +85°C
–40°C to +105°C
VDD
5V ± 10%
5V ± 10%
–40°C to +125°C
5V ± 10%
DC ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Test Conditions
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
GND ≤ VIN ≤ VDD
Min.
2.4
—
2.2
–0.3
–10
Max.
—
0.4
VDD + 0.5
0.8
10
Unit
V
V
V
V
µA
–10
10
µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
ICC1
Parameter
VDD Operating
Supply Current
Test Conditions
VDD = Max., CS = VIL
IOUT = 0 mA, f = 0
ICC2
VDD Dynamic Operating
Supply Current
VDD = Max., CS = VIL
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
VIN = VIH or VIL
CS = VIH, f = 0
VDD = Max.,
CS ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
A1
A2
A3
A1
A2
A3
A1
A2
A3
A1
A2
A3
Min.
—
—
—
—
—
—
—
—
—
—
—
—
-20 ns
typ(2) Max.
40
50
60
25
95
25 105
25 115
5
10
10
0.5
1.0
1.5
Unit
mA
mA
mA
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25oC, tAA = 70 ns, and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
3
ISSI
IS65C256
®
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR1
IDR2
IDR3
Parameter
VDD for retention of data
Data retention current
Data retention current
Data retention current
Test Conditions
Options
VDR = 3.0V
VDR = 3.0V
VDR = 3.0V
A1
A2
A3
Min.
2.0
—
—
—
typ (1)
50
50
50
Max.
—
150
300
500
Units
V
µA
µA
µA
Note:
2. Typical values are measured at VDD = 3V, TA = 25oC, and not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol
Parameter
Min.
Max.
Unit
tRC
Read Cycle Time
20
—
ns
tAA
Address Access Time
—
20
ns
tOHA
Output Hold Time
3
—
ns
tACS
CS Access Time
—
20
ns
OE Access Time
—
8
ns
OE to Low-Z Output
0
—
ns
tHZOE
OE to High-Z Output
0
9
ns
tLZCS(2)
CS to Low-Z Output
3
—
ns
tHZCS(2)
CS to High-Z Output
0
9
ns
tPU
CS to Power-Up
0
—
ns
tPD
CS to Power-Down
—
18
ns
tDOE
tLZOE
(2)
(2)
(3)
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
ISSI
IS65C256
®
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 1.
Figure 2.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
5
ISSI
IS65C256
®
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CS
t ACS
t HZCS
t LZCS
DOUT
HIGH-Z
DATA VALID
CS_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = VIL.
3. Address is valid prior to or coincident with CS LOW transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-20 ns
Min.
Max.
Unit
tWC
Write Cycle Time
20
—
ns
tSCS
CS to Write End
13
—
ns
tAW
Address Setup Time to Write End
15
—
ns
tHA
Address Hold from Write End
1
—
ns
Address Setup Time
0
—
ns
tPWE
WE Pulse Width
13
—
ns
tSD
Data Setup to Write End
10
—
ns
tHD
Data Hold from Write End
0
—
ns
tSA
(4)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
ISSI
IS65C256
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SA
t SCS
t HA
CS
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CS_WR1.eps
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CS
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CS_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
7
ISSI
IS65C256
®
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CS
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
ISSI
IS65C256
®
ORDERING INFORMATION
Temperature Range (A1): –40°C to +85°C
Speed (ns)
20
Order Part No.
Package
IS65C256-20TA1
TSOP
Temperature Range (A2): –40°C to +105°C
Speed (ns)
Order Part No.
Package
20
IS65C256-20TA2
IS65C256-20UA2
TSOP
Plastic SOP
Temperature Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
20
IS65C256-20TA3
IS65C256-20UA3
TSOP
Plastic SOP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/24/04
9
ISSI
PACKAGING INFORMATION
®
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
B
e
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
α
α
C
Plastic TSOP (T—Type I)
Millimeters
Inches
Min
Max
Min
Max
28
1.00
1.20
0.05
0.20
0.16
0.27
0.10
0.20
7.90
8.10
11.70
11.90
13.20
13.60
0.55 BSC
0.30
0.70
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28
L
A1
Rev. B 01/31/97
0.037
0.047
0.002
0.008
0.006
0.011
0.004
0.008
0.308
0.316
0.456
0.465
0.515
0.531
0.022 BSC
0.011
0.027
0°
5°
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
1
ISSI
®
PACKAGING INFORMATION
330-mil Plastic SOP
Package Code: U (28-pin)
N
E1
E
1
D
SEATING PLANE
A
S
L
B
e
A1
MILLIMETERS
Sym.
Min.
No. Leads
Max.
h x 45o
INCHES
Min.
28
Max.
28
A
—
2.84
—
0.112
A1
0.10
—
0.004
—
B
0.36
0.51
0.014
0.020
C
0.25
—
0.010
—
D
17.98
18.24
0.708
0.718
E
11.51
12.12
0.453
0.477
E1
8.28
8.53
0.326
0.336
e
1.27 BSC
0.30
0.51
0.012
0.020
L
0.71
1.14
0.028
0.045
α
0
8
0
8o
S
0.58
1.19
0.023
0.047
o
C
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
0.050 BSC
h
o
α
o
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/26/03