P4C1024 P4C1024 HIGH SPEED 128K x 8 CMOS STATIC RAM FEATURES High Speed (Equal Access and Cycle Times) — 15/17/20/25/35 ns (Commercial) — 20/25/35/45 ns (Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —32-Pin 300 mil DIP and SOJ —32-Pin 400 mil SOJ DESCRIPTION The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory Access times of 15 nanoseconds permit greatly en- location is presented on the data input/output pins. The hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either reduce power consumption to a low level. The P4C1024 CE1 or OE is HIGH or WE or CE2 is LOW. is a member of a family of PACE RAM™ products offering fast access times. Package options for the P4C1024 include 32-pin 300 mil DIP and SOJ packages as well as 400 mil SOJ. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM ••• ROW SELECT A (9) A ••• ••• INPUT DATA CONTROL ••• ••• ••• ••• I/O1 262,144BIT MEMORY ARRAY COLUMN I/O I/O2 COLUMN SELECT ••• CONTROL CIRCUIT A (8) 1 32 VCC 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O0 13 20 I/O7 I/O6 I/O1 I/O2 WE CE1 CE2 NC A16 GND ••• 14 19 15 16 18 17 I/O5 I/O4 I/O3 1024.2 DIP (P300), SOJ (J300, J400) TOP VIEW A 1024.1 OE Means Quality, Service and Speed 1Q97 141 P4C1024 RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 4.5V ≤ VCC ≤ 5.5V Industrial (-40°C to 85°C) 4.5 ≤ VCC ≤ 5.5V MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit VCC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter Min Test Conditions VOH Output High Voltage (I/O0 - I/O7) IOH = –4mA, VCC = 4.5V VOL Output Low Voltage (I/O0 - I/O7) IOL = 8 mA IOL = 10 mA Max 2.4 Unit V V 0.4 0.5 V VIH Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage -0.5 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VCC Ind'l. Com'l. -10 -5 +10 +5 µA ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE1 ≥ VIH or CE2 ≤ VIL Ind'l. Com'l. -10 -5 +10 +5 µA IOS Output Short-Circuit Current VOUT = GND, VCC = Max (Single output) not to exceed 30 second duration -350 mA ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V 20 (Standard) mA 142 P4C1024 CAPACITANCES (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Test Conditions Max Input Capacitance VIN = 0V 8 pF Output Capacitance VOUT = 0V 10 pF Unit POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Industrial -15 -17 -20 -25 -35 -45 190 N/A 180 N/A 160 175 150 165 145 160 N/A 155 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1, and WE ≤ VIL (max). Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -35 -45 -15 -17 -20 -25 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 15 17 20 25 35 45 ns tAC Chip Enable Access Time Output Hold from Address Change 15 17 20 25 35 45 ns tOH 17 15 20 25 45 35 ns 3 3 3 3 3 3 ns 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z tHZ Chip Disable to Output in High Z 8 9 9 11 15 20 ns tOE Output Enable Low to Data Valid 6 7 9 10 15 20 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 0 0 0 12 0 9 7 6 0 0 143 20 0 15 11 0 0 15 0 0 20 ns 20 ns 0 20 ns 25 ns P4C1024 OE CONTROLLED)(1) READ CYCLE NO. 1 (OE tRC(5) ADDRESS tAA OE tOH t OE t CE OLZ CE 2 tAC t OHZ t LZ t HZ DATA OUT NOTES: 1. WE is HIGH for READ cycle. 2. CE1 and OE is LOW and CE2 is HIGH for read cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. READ CYCLE NO. 2 (ADDRESS CONTROLLED) t RC (5) ADDRESS t AA t OH DATA OUT DATA VALID PREVIOUS DATA VALID CE CONTROLLED) READ CYCLE NO. 3 (CE tRC CE 1 CE 2 tHZ tAC tLZ DATA OUT DATA VALID HIGH IMPEDANCE ICC tPD tPU VCC SUPPLY I SB CURRENT 144 P4C1024 AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -15 -17 -45 -25 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 15 17 20 25 35 45 ns tCW Chip Enable Time to End of Write Address Valid to End of Write 12 13 15 18 22 30 ns 12 13 15 20 25 35 ns 0 0 0 0 0 0 ns tWP Address Set-up Time Write Pulse Width 12 12 15 18 22 25 ns tAH Address Hold Time 0 0 0 0 0 0 ns tDW Data Valid to End of Write Data Hold Time 7 7 8 10 15 20 ns 0 0 0 0 0 0 ns tAW tAS tDH tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 8 3 10 3 3 3 15 11 3 18 3 WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE t WC (9) ADDRESS tCW CE 1 CE 2 t AW tWP tAH WE t AS t DW DATA IN DATA VALID (4) t OW tWZ (7) DATA OUT tDH (4,7) DATA UNDEFINED HIGH IMPEDANCE Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. 145 ns ns P4C1024 CE CONTROLLED)(6) TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE tWC (9) ADDRESS tAS tCW CE 1 tAH tAW CE2 t WP WE tDW DATA VALID DATA IN DATA OUT tDH (12) HIGH IMPEDANCE TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels CE1 CE2 OE WE I/O GND to 3.0V Mode Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V 1.5V Standby X L X X High Z Standby DOUT Disabled L H H H High Z Active See Figures 1 and 2 Read L DOUT L L X H Write H H L High Z Active Active Output Timing Reference Level Output Load Power +5V 480 Ω RTH D OUT D OUT 255 Ω 30pF* (5pF* for t HZ , t LZ , t OHZ , t OLZ , t WZ and t OW ) Figure 1. Output Load = 166.5 Ω VTH = 1.73 V 30pF* (5pF* for t HZ , t LZ , t OHZ, t OLZ , t WZ and t OW ) Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1024, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. 146 To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). P4C1024 TEMPERATURE RANGE SUFFIX PACKAGE SUFFIX Package Suffix P3 J3 J4 Temperature Description Range Suffix Description C Plastic DIP, 300 mil wide standard Plastic SOJ, 300 mil wide standard Plastic SOJ, 400 mil wide standard Commercial Temperature Range, 0˚C to +70˚C Industrial Temperature Range, -40˚C to +85˚C I ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 1024 ss p t Temperature Range: C, I Package Code: P3, J3, J4 Speed (Access/Cycle Time): 15, 17, etc. Device Number: 1024 Static RAM Prefix SELECTION GUIDE The P4C1024 is available in the following temperature, speed and package options. Temperature Range Package Commercial Temperature Plastic DIP 300 Plastic SOJ 300 Plastic SOJ 400 Industrial Temperature Plastic DIP 300 Plastic SOJ 300 Plastic SOJ 400 -15 -17 Speed (ns) -20 -25 -35 -15P3C -17P3C -20P3C -25P3C -35P3C -15J3C -17J3C -20J3C -25J3C -35J3C -15J4C -17J4C -20J4C -25J4C -35J4C N/A N/A N/A N/A N/A N/A N/A = Not Available 147 -20P3I -20J3I -20J4I -25P3I -25J3I -25J4I -35P3I -35J3I -35J4I P4C1024 148