ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8402 is a general purpose, Crystal-toLVCMOS/LVTTL High Frequency Synthesizer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8402 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8402 make it an ideal clock source for Gigabit Ethernet and SONET applications. • 2 LVCMOS/LVTTL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 15.625MHz to 350MHz • Crystal input frequency range: 12MHz to 40MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 8ps (typical) • Cycle-to-cycle jitter: 40ps (typical) • Full 3.3V or mixed 3.3V core/2.5V output supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 nP_LOAD M0 M1 M2 M3 M4 OE1 VCO_SEL OE0 VCO_SEL 32 31 30 29 28 27 26 25 XTAL_SEL TEST_CLK 0 XTAL1 OSC 1 XTAL2 PLL M5 1 24 XTAL2 M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VDDA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK GND 8 17 MR PHASE DETECTOR 9 10 11 12 13 14 15 16 TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View M0:M8 N0:N1 8402AY GND CONFIGURATION INTERFACE LOGIC Q0 S_LOAD S_DATA S_CLOCK nP_LOAD Q1 Q1 VDDO Q0 OE0 1 ÷2 ÷4 ÷8 ÷16 OE1 ÷M 0 VDD VCO TEST MR ICS8402 www.icst.com/products/hiperclocks.html 1 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. put divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS8402 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVCMOS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8402 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N out- T1 T0 TEST Output 0 0 LOW 0 1 Shift Register Output 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK T1 S_DATA t S S_LOAD t T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t Time H FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 8402AY www.icst.com/products/hiperclocks.html 2 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 M5 Input 2, 3, 4, 28, 29, 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input M divider inputs. Data latched on LOW-to-HIGH transition Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. 5, 6 N0, N1 Input Pulldown 7 nc Unused 8, 16 GND Power Power supply ground. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. 10 VDD Power Core supply pin. 11, 12 OE1, OE0 Input 13 VDDO Power Output supply pin. 14, 15 Q1, Q0 Output Clock outputs. LVCMOS / LVTTL interface levels. Pullup Pullup MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VDDA Power 22 XTAL_SEL Input 23 TEST_CLK Input 24, 25 XTAL2, XTAL1 Input nP_LOAD Input 27 VCO_SEL Input Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. 17 26 Description Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are in Tri-State. See Table 3D, OE Function Table. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Pullup Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels Pulldown Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 8402AY www.icst.com/products/hiperclocks.html 3 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance Minimum Typical Maximum Units 4 pF VDD, VDDA, VDDO = 3.465V 13 pF VDD, VDDA = 3.465V, VDDO = 2.625V 11 pF 51 KΩ 51 5 7 KΩ 12 Ω TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition 8402AY www.icst.com/products/hiperclocks.html 4 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 10 0 0 0 0 0 1 0 1 0 275 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • • • • • • • • • • • • 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 0 VCO Frequency (MHz) M Divide 250 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz. TABLE 3D. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) Minimum Maximum N1 N0 0 0 2 125 350 0 1 4 62.5 175 1 0 8 31.25 87.5 1 1 16 15.625 43.75 8402AY Control Inputs OE0 OE1 Q0 Q1 0 0 Hi-Z Hi-Z 0 1 Hi-Z Enabled 1 0 Enabled Hi-Z 1 1 Enabled Enabled www.icst.com/products/hiperclocks.html 5 Output REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 32 Lead LQFP 47.9°C/W (0 lfpm) 32 Lead VFQFN 34.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 125 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 10 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, OE0, OE1, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VDD = 3.465V, VIN = 0V VDD = 3.465V, M5, OE0, OE1, XTAL_SEL, VCO_SEL VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VIN = 0V Minimum Typical -5 µA -150 µA 2.6 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. 8402AY www.icst.com/products/hiperclocks.html 6 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 125 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 10 mA TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, OE0, OE1, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA VDD = 3.465V, VIN = 0V VDD = 3.465V, M5, OE0, OE1, XTAL_SEL, VCO_SEL VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VIN = 0V Minimum Typical -5 µA -150 µA 1.8 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fIN Input Frequency Maximum Units TEST_CLK; NOTE 1 Test Conditions Minimum 12 Typical 40 MHz XTAL1, XTAL2; NOTE 1 12 40 MHz S_CLOCK 50 MHz NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58. Using the maximum frequency of 40MHz, valid values of M are 7 ≤ M ≤ 17. 8402AY www.icst.com/products/hiperclocks.html 7 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency 12 50 Ω Shunt Capacitance (CO) 7 pF TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Units FOUT Output Frequency 350 MHz tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1, 3 40 80 ps tjit(per) Period Jitter, RMS; NOTE 1 8 20 ps tsk(o) Output Skew; NOTE 2, 3 60 ps tR / tF Output Rise/Fall Time 1.1 ns tS Setup Time tH odc Hold Time 15.625 Maximum 20% to 80% 0.3 M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 40 60 % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency Minimum Typical 15.625 Maximum Units 350 MHz tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1, 3 40 80 ps tjit(per) Period Jitter, RMS; NOTE 1 8 15 ps tsk(o) Output Skew; NOTE 2, 3 60 ps tR / tF Output Rise/Fall Time 1.0 ns tS Setup Time 20% to 80% 0.3 M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns tH Hold Time odc Output Duty Cycle S_CLOCK to S_LOAD 5 40 ns 60 % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 8402AY www.icst.com/products/hiperclocks.html 8 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO VDDO Qx LVCMOS SCOPE VDD, VDDA Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT VOH VREF V DDO Qx 2 V DDO Qy VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements 2 t sk(o) Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) PERIOD JITTER OUTPUT SKEW V V DDO V DDO 2 DDO 2 ➤ Q0, Q1 ➤ tcycle n 80% 80% tR tF 2 tcycle n+1 ➤ Clock Outputs 20% 20% ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME V DDO 2 Q0, Q1 Pulse Width t odc = PERIOD t PW t PERIOD Output Duty Cycle/tPERIOD 8402AY www.icst.com/products/hiperclocks.html 9 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8402 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS8402 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS8402 ICS84332 Figure 3. CRYSTAL INPUt INTERFACE 8402AY www.icst.com/products/hiperclocks.html 10 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8A. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8B. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN θ JA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W TRANSISTOR COUNT The transistor count for ICS8402 is: 3784 8402AY www.icst.com/products/hiperclocks.html 11 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX FOR 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER 32 LEAD LQFP TABLE 9A. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8402AY www.icst.com/products/hiperclocks.html 12 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - K SUFFIX FOR A 32 LEAD VFQFN TABLE 9B. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A 0.80 -- 1.00 A1 0 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D D2 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 8402AY www.icst.com/products/hiperclocks.html 13 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8402AY ICS8402AY 32 Lead LQFP 250 per tray 0°C to 70°C ICS8402AYT ICS8402AY 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C ICS8402AK ICS8402AK 32 Lead MLF 490 per tray 0°C to 70°C ICS8402AKT ICS8402AK 32 Lead MLF on Tape and Reel 2500 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8402AY www.icst.com/products/hiperclocks.html 14 REV. B OCTOBER 6, 2004 ICS8402 Integrated Circuit Systems, Inc. 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table 7A Page 8 7B 8 B T1 3 B T1 3 T8B T9B T10 1 6 11 13 14 B B 8402AY Description of Change 3.3V AC Characteristics Table, changed Output Rise/Fall Time 1.4ns max. to 1.1ns max. Date 3.3V/2.5V AC Characteristics Table, changed Output Rise/Fall Time 1.4ns max. to 1.0ns max. Pin Description Table - corrected OE0 and OE1 pin name to correspond with the pin number. Pin Description Table - corrected placement of Q0, Q1 pins to correspond with Pin Assignment. Pin Assignment - added 32 Lead VFQFN package. AMR - added 32 Lead VFQFN Package Thermal Impedance. Added 32 Lead VFQFN Thermal Resistance. Add 32 Lead VFQFN Package Outline & Dimensions. Ordering Information Table - added 32 Lead VFQFN ordering information www.icst.com/products/hiperclocks.html 15 8/1/03 11/4/03 8/10/04 10/6/04 REV. B OCTOBER 6, 2004