ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8521 is a low skew, 1-to-9 3.3V Differential-to-LVHSTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulseson the outputs during asynchronous assertion/ deassertion of the clock enable pin. • 9 LVHSTL outputs Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8521 ideal for today’s most advanced applications, such as IA64 and static RAMs. • Part-to-part skew: 250ps (maximum) ,&6 • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Output skew: 50ps (maximum) • Propagation delay: 1.8ns (maximum) • VOH = 1.2V (maximum) • 3.3V core, 1.8V output operating supply voltages • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT CLK nCLK PCLK nPCLK CLK_SEL VDDO nQ2 Q2 Q nQ1 Q1 nQ0 Q0 VDDO D CLK_EN LE 0 1 32 31 30 29 28 27 26 25 Q0 nQ0 VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 ICS8521 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 9 1 0 1 1 1 2 1 3 1 4 1 5 16 VDDO Q6 nQ6 Q7 nQ7 Q6 nQ6 Q8 nQ8 VDDO Q5 nQ5 32-Lead LQFP 7mm x 7mm x 1.4mm Package Body Y Package Top View Q7 nQ7 Q8 nQ8 8521BY www.icst.com/products/hiperclocks.html 1 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Type Description Power Positive supply pin. Connect to 3.3V. 2 CLK Input Pulldown 3 nCLK Input Pullup 4 CLK_SEL Input Pulldown 5 PCLK Input Pulldown Pullup 6 nPCLK Input 7 GND Power 8 CLK_EN Input Pullup Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Power supply ground. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /LVTTL interface levels. 9, 16, 17, 24, 25, 32 10, 11 VDDO Power Output supply pins. Connect to 1.8V. nQ8, Q8 Output Differential output pair. LVHSTL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVHSTL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVHSTL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVHSTL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVHSTL interface level. 22, 23 nQ3 Q3 Output Differential output pair. LVHSTL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVHSTL interface level. 28, 29 nQ1, Q1 Output Differential output pair. LVHSTL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVHSTL interface level. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical CLK, nCLK, PCLK, nPLCK CLK_EN, CLK_SEL Maximum Units 4 pF CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8521BY 4 www.icst.com/products/hiperclocks.html 2 pF REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Sourced Q0 thru Q8 nQ0 thru nQ8 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0 - nQ8 Q0 - Q8 FIGURE 1: CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK Q0 thru Q8 nQ0 thru nQ8 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential input to accept single ended levels. 8521BY www.icst.com/products/hiperclocks.html 3 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9°C/W -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 60 80 mA Typical TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter VIH CLK_EN, CLK_SEL VIL CLK_EN, CLK_SEL IIH Input High Current IIL Input Low Current Test Conditions Minimum Maximum Units 2 3.765 V -0.3 0.8 V CLK_EN VIN = VDD = 3.465V 5 µA CLK_SEL VIN = VDD = 3.465V 150 µA CLK_EN VIN = 0V, VDD = 3.465V -150 µA CLK_SEL VIN = 0V, VDD = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK Minimum Typical VIN = VDD = 3.465V Units 150 µA nCLK VIN = VDD = 3.465V CLK VIN = 0V, VDD = 3.465V -5 5 µA nCLK VIN = 0V, VDD = 3.465V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8521BY Maximum www.icst.com/products/hiperclocks.html 4 µA 1.3 V VDD - 0.85 V REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 150 µA 5 µA VDD = VIN = 3.465V PCLK nPCLK VDD = VIN = 3.465V PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; VCMR 1.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 1 V VDD V VPP TABLE 4E. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Test Conditions Output Crossover Voltage Minimum Maximum Units 1.0 1.2 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.6 1.1 V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50Ω to ground. VSWING Typical TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency Test Conditions Minimum ƒ≤ 250MHz Typical 1 Maximum Units 500 MHz tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % odc Output Duty Cycle 48 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differntial cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the output are measurd at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8521BY www.icst.com/products/hiperclocks.html 5 1.8 ns 50 ps REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDDO VDD SCOPE Qx LVHSTL VDD = 3.3V ± 5% VDDO = 1.8V ± 0.2V nQx GND = 0V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT V DD CLK, PCLK V Cross Points PP V CMR nCLK, nPCLK GND FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8521BY www.icst.com/products/hiperclocks.html 6 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 5 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 6 - INPUT AND OUTPUT RISE AND F FALL TIME CLK, PCLK nCLK, nPCLK Q0, Q8 nQ0, nQ8 t PD FIGURE 7 - PROPAGATION DELAY CLK, PCLK nCLK, nPCLK Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 8 - odc & tPERIOD 8521BY www.icst.com/products/hiperclocks.html 7 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8521BY www.icst.com/products/hiperclocks.html 8 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8521. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32mW = 288mW Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 288mW = 565.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.565W * 42.1°C/W = 93.8°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 32-pin LQFP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8521BY www.icst.com/products/hiperclocks.html 9 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 10. VDD Q1 VOUT RL 50Ω FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. DD Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX • L -V DD_MAX /R ) * (V L -V DD_MAX For logic high, V For logic low, V OUT ) OL_MAX =V OUT • ) OH_MAX =V OH_MAX =V OL_MAX – 1.2V DD_MAX =V – 0.4V DD_MAX Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW 8521BY www.icst.com/products/hiperclocks.html 10 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8521 is: 944 8521BY www.icst.com/products/hiperclocks.html 11 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8521BY www.icst.com/products/hiperclocks.html 12 REV. B JULY 31, 2001 ICS8521 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number ICS8521BY ICS8521BYT Marking ICS8521BY ICS8521BY Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0°C to 70°C 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8521BY www.icst.com/products/hiperclocks.html 13 REV. B JULY 31, 2001