TI 74ACT11008PW

74ACT11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS013C – AUGUST 1987 – REVISED APRIL 1996
D
D
D, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline (D), Plastic Thin Shrink
Small-Outline (PW), and Standard Plastic
300-mil DIPs (N) Packages
D
D
D
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1B
2A
2B
VCC
VCC
3A
3B
4A
description
The 74ACT11008 contains four independent 2-input AND gates. It performs the Boolean function Y = ASB or
Y
+ A ) B in positive logic.
The 74ACT11008 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
INPUTS
logic symbol†
1A
1B
2A
2B
3A
3B
4A
4B
1
logic diagram (positive logic)
&
16
2
1Y
1A
1B
15
3
14
2Y
2A
2B
11
6
10
3Y
3A
3B
9
7
8
4Y
4A
4B
1
2
16
15
3
14
11
6
10
9
8
7
1Y
2Y
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
74ACT11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS013C – AUGUST 1987 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
–24
mA
IOL
Dt/Dv
Low-level output current
24
mA
0
10
ns/ V
TA
Operating free-air temperature
–40
85
°C
2
Input transition rise or fall rate
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V
74ACT11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS013C – AUGUST 1987 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
4.5 V
IOH = –50
50 mA
VOH
24 mA
IOH = –24
IOL = 50 mA
VOL
IOL = 24 mA
TA = 25°C
TYP
MAX
MIN
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.7
5.5 V
4.94
MAX
UNIT
V
4.7
4.5 V
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
V
0.44
IOH†
IOL†
VO = 3.85 V
VO = 1.65 V
5.5 V
II
ICC
VI = VCC or GND
VI = VCC or GND,
5.5 V
±0.1
±1
mA
IO = 0
5.5 V
4
40
mA
DICC‡
One input at 3.4 V,,
Other inputs at GND or VCC
55V
5.5
09
0.9
1
mA
–75
5.5 V
mA
75
mA
Ci
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 1 second.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 or VCC.
pF
switching characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
MIN
TA = 25°C
TYP
MAX
MIN
MAX
1.5
5.8
8
1.5
9
1.5
5.2
7.7
1.5
8.2
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
CL = 50 pF,
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f = 1 MHz
TYP
UNIT
29
pF
3
74ACT11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS013C – AUGUST 1987 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
3V
Input
(see Note B)
From Output
Under Test
CL = 50 pF
(see Note A)
1.5 V
1.5 V
0V
tPLH
tPHL
500 Ω
Output
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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