ICS ICS85304AG-01

ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout
HiPerClockS™
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS85304-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable
pin.
• 5 differential 3.3V LVPECL outputs
Guaranteed output and part-to-part skew characteristics
make the ICS85304-01 ideal for those applications
demanding well defined performance and repeatability.
• Output skew: 35ps (maximum)
,&6
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
D
CLK_EN
Q
LE
CLK
nCLK
PCLK
nPCLK
00
11
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
20
19
18
17
16
15
14
13
12
11
VCC
CLK_EN
VCC
nPCLK
PCLK
VEE
nCLK
CLK
CLK_SEL
VCC
ICS85304-01
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
Q4
nQ4
85304AG-01
1
2
3
4
5
6
7
8
9
10
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1
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
Q0, nQ0
Type
Description
Output
Differential output pair. LVPECL interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. LVPECL interface levels.
9, 10
Q4, nQ4
Output
11, 18, 20
VCC
Power
12
CLK_SEL
Input
13
CLK
Input
14
nCLK
Input
15
VEE
Power
16
PCLK
Input
17
nPCLK
Input
Differential output pair. LVPECL interface levels.
Positive supply pins. Connect to 3.3V.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown When LOW, selects CLK, nCLK inputs.
LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Negative supply pin. Connect to ground.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock
19
CLK_EN
Input
Pullup
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
CLK, nCLK
Maximum
Units
4
pF
4
pF
4
pF
RPULLUP
PCLK, nPCLK
CLK_EN,
CLK_SEL
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
CIN
85304AG-01
Input Capacitance
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2
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_EN
CLK_SEL
Outputs
Selected Source
Q0 thru Q4
nQ0 thru nQ4
0
0
CLK, nCLK
Disabled; LOW
Disabled; HIGH
0
1
PCLK, nPCLK
Disabled; LOW
Disabled; HIGH
1
0
CLK, nCLK
Enabled
Enabled
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ4
Q0 - Q4
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK or CLK
nPCLK or nPCLK
Q0 thru Q4
nQ0 thru nQ4
0
1
LOW
HIGH
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
1
0
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section on page 8, Figure 8, which discusses wiring the differential
input to accept single ended levels.
85304AG-01
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3
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
4.6V
Inputs, VI
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
55
mA
Maximum
Units
2
3.765
V
-0.3
0.8
V
TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
CLK_EN
VIN = VCC = 3.465V
5
µA
CLK_SEL
VIN = VCC = 3.465V
150
µA
CLK_EN
VCC = 3.465V, VIN = 0V
-150
µA
CLK_SEL
VCC = 3.465V, VIN = 0V
-5
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Units
nCLK
VCC = VIN = 3.465V
5
µA
CLK
VCC = VIN = 3.465V
150
µA
nCLK
VCC = 3.465V, VIN = 0V
-150
CLK
VCC = 3.465V, VIN = 0V
-5
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
0.5
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
VPP
85304AG-01
Maximum
www.icst.com/products/hiperclocks.html
4
µA
µA
1.3
V
VCC - 0.85
V
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Maximum
Units
PCLK
VCC = VIN = 3.465V
Test Conditions
Minimum
Typical
150
µA
nPCLK
VCC = VIN = 3.465V
5
µA
PCLK
VCC = 3.465V, VIN = 0V
-5
nPCLK
VCC = 3.465V, VIN = 0V
-150
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.5
VCC - 0.85
V
µA
µA
VOH
Output High Voltage; NOTE 3
VCC - 1.4
VCC - 1.0
V
VOL
Output Low Voltage; NOTE 3
VCC - 2.0
VCC - 1.7
V
0.85
V
Maximum
Units
650
MHz
2.1
ns
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
IJ 650MHz
1.0
Typical
fMAX
Maximum Output Frequency
tPD
Propagation Delay; NOTE 1
t sk(o)
Output Skew; NOTE 2, 4
35
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
150
ps
tR
Output Rise Time
20% to 80% @ 50MHz
300
700
ps
tF
Output Fall Time
20% to 80% @ 50MHz
300
700
ps
52
ps
odc
Output Duty Cycle
48
50
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85304AG-01
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5
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK, PCLK
V
Cross Points
PP
V
CMR
nCLK, nPCLK
VEE
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
85304AG-01
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6
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
80%
80%
V
20%
SWING
20%
Clock Inputs
and Outputs
t
t
R
FIGURE 5 - INPUT
AND
OUTPUT RISE
AND
F
FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0 - Q4
nQ0 - nQ4
t
PD
FIGURE 6 - PROPAGATION DELAY
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
t
t
odc =
t
PERIOD
PW
PERIOD
FIGURE 7 - odc & tPERIOD
85304AG-01
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7
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
VCC
CLK_IN
R1
1K
R1
1K
CLK_IN
+
+
V_REF
-
V_REF
C1
0.1uF
C1
0.1uF
R2
1K
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
85304AG-01
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8
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85304-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85304-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.57mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.341W * 66.6°C/W = 92.71°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85304AG-01
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9
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 9 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load,
and a termination voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
OH_MAX
OL_MAX
•
– (V - 2V))/R ]*(V - V
CC
L
CC
)
OH_MAX
– (V - 2V))/R ]*(V - V
CC
L
For logic high , V
OUT
=V
CC
OH_MAX
)
OL_MAX
=V
CC
– 1.0V
Using V = 3.465, this results in V
CC
•
OH_MAX
For logic low , V
OUT
=V
OL_MAX
= V – 1.7V
CC
Using V = 3.465, this results in V
CC
= 2.465V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85304AG-01
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10
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85304-01 is: 489
85304AG-01
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11
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
85304AG-01
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12
REV. B JULY 13, 2001
ICS85304-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS85304AG-01
ICS85304AG-01
20 lead TSSOP
72 per tube
0°C to 70°C
ICS85304AG-01T
ICS85304AG-01
20 lead TSSOP on Tape and Reel
2500
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85304AG-01
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13
REV. B JULY 13, 2001