ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85322 is a Dual LVCMOS / LVTTL-toDifferential 2.5V / 3.3V LVPECL translator and a HiPerClockS™ member of the HiPerClocks™ family of High Performance Clocks Solutions from ICS. The ICS85322 has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. • 2 differential 2.5V/3.3V LVPECL outputs ,&6 • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency up to 267MHz • Part-to-part skew: 150ps (maximum) • 3.3V operating supply voltage (operating range 3.135V to 3.465V) • 2.5V operating supply voltage (operating range 2.375V to 2.625V) • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT CLK0 Q0 nQ0 CLK1 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK0 CLK1 VEE ICS85322 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85322AM www.icst.com/products/hiperclocks.html 1 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL interface levels. Description 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. Connect to ground. 6 CLK1 Input Pullup 7 CLK0 Input Pullup 8 VCC Power LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin. Connect to 3.3V or 2.5V NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 85322AM Test Conditions Minimum Typical CLK0, CLK1 www.icst.com/products/hiperclocks.html 2 Maximum Units 4 pF REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θ JA -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 112.7°C/W (0lfpm) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 25 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage CLK0, CLK1 Test Conditions VIL Input Low Voltage CLK0, CLK1 IIH Input High Current CLK0, CLK1 VCC = VIN = 3.465V IIL Input Low Current CLK0, CLK1 VCC = VIN = 3.465V Minimum Maximum Units 2 Typical 3.765 V -0.3 1.3 V 5 µA -150 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC = VIN = 3.465V VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC = VIN = 3.465V VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.65 0.9 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 85322AM www.icst.com/products/hiperclocks.html 3 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency Test Conditions ƒ ≤ 267MHz tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR Output Rise Time 20% to 80% @ 50MHz tF Output Fall Time 20% to 80% @ 50MHz Minimum Typical 0.6 www.icst.com/products/hiperclocks.html 4 Units 267 MHz 1.8 ns 150 ps 300 700 ps 300 700 ps 60 % odc Output Duty Cycle 40 All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85322AM Maximum REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 25 mA TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage CLK0, CLK1 1.6 2.925 V VIL Input Low Voltage CLK0, CLK1 -0.3 0.9 V 5 µA IIH Input High Current CLK0, CLK1 VCC = VIN = 2.625 IIL Input Low Current CLK0, CLK1 VCC = VIN = 2.625 -150 µA TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC - 1.4 VCC - 1.0 V VCC - 2.0 VCC - 1.7 V 0.65 0.9 V Maximum Units 215 MHz NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency Test Conditions ƒ ≤ 215MHz tPD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR Output Rise Time 20% to 80% @ 50MHz tF Output Fall Time 20% to 80% @ 50MHz Minimum Typical 0.8 2 ns 150 ps 300 700 ps 300 700 ps 60 % odc Output Duty Cycle 40 All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.. 85322AM www.icst.com/products/hiperclocks.html 5 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR PARAMETER MEASUREMENT INFORMATION V CC SCOPE Qx LVPECL VCC = 2V nQx VEE = -1.3V ± 0.135V FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT V CC SCOPE Qx LVPECL VCC = 2V nQx VEE = -0.5V ± 0.125V FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT 85322AM www.icst.com/products/hiperclocks.html 6 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 2 - PART-TO-PART SKEW 80% 80% V 20% Clock Inputs and Outputs 20% t t R FIGURE 3 - INPUT 85322AM SWING AND OUTPUT RISE AND F FALL TIME www.icst.com/products/hiperclocks.html 7 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR V /2 CC CLK0, CLK1 Q0 - Q1 nQ0 - nQ1 t PD FIGURE 4 - PROPAGATION DELAY CLK0, CLK1, Q0, Q1 nQ0, nQ1 Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 5 - odc & tPERIOD 85322AM www.icst.com/products/hiperclocks.html 8 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85322. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85322 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.147W * 103.3°C/W = 85.2°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 5. Thermal Resistance qJA for 8-pin SOIC, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 200 128.5°C/W 103.3°C/W 500 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85322AM www.icst.com/products/hiperclocks.html 9 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) L • For logic high, VOUT = V OH_MAX Using V CC_MAX • OH_MAX OL_MAX CC_MAX – 1.0V CC_MAX = 3.465, this results in V For logic low, VOUT = V Using V =V =V CC_MAX = 2.465V – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 85322AM www.icst.com/products/hiperclocks.html 10 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 200 128.5°C/W 103.3°C/W 500 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85322 is: 269 85322AM www.icst.com/products/hiperclocks.html 11 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR PACKAGE OUTLINE - M SUFFIX TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85322AM www.icst.com/products/hiperclocks.html 12 REV. A JULY 31, 2001 ICS85322 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85322AM ICS85322AM 8 lead SOIC 96 per tube 0°C to 70°C ICS85322AM-T ICS853322AM 8 lead SOIC on Tape and Reel 2500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85322AM www.icst.com/products/hiperclocks.html 13 REV. A JULY 31, 2001