ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8535-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. • 4 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8535-01 ideal for those applications demanding well defined performance and repeatability. • Output skew: 30ps (maximum) ,&6 • Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications • CLK0 or CLK1 can accept the following differential input levels: LVCMOS or LVTTL • Maximum output frequency up to 266MHz • Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels • Part-to-part skew: 150ps (maximum) • Propagation delay: 1.9ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VEE CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VCC D CLK_EN Q LE CLK0 0 CLK1 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8535-01 Q3 nQ3 ICS8535AG-01 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 4.4mm x 6.5mm x 0.92mm body package G Package Top View www.icst.com/products/hiperclocks.html 1 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VEE Power 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown 4 CLK0 Input Pulldown 6 5, 7, 8, 9 CLK1 nc Input Unused Pulldown 10, 13, 18 VCC Power Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. No connect. Positive supply pins. Conncect to 3.3V. 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units 4 pF 4 pF RPULLUP CLK0, CLK1 Input Capacitance CLK_EN, CLK_SEL Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CIN ICS8535AG-01 www.icst.com/products/hiperclocks.html 2 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN 0 CLK_SEL 0 Selected Source CLK0 Q0 thru Q3 Disabled; LOW nQ0 thru nQ3 Disabled; HIGH 0 1 CLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0 Enabled Enabled 1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B. Disabled CLK0, CLK1 Enabled CLK_EN nQ0 - nQ3 Q0 - Q3 FIGURE 1 - CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK0 or CLK1 0 1 ICS8535AG-01 Q0 thru Q3 LOW HIGH www.icst.com/products/hiperclocks.html 3 nQ0 thru nQ3 HIGH LOW REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (no airflow) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1, CLK_SEL CLK_EN CLK0, CLK1, CLK_SEL CLK_EN Minimum Maximum Units 2 Typical 3.765 V 2 3.765 V -0.3 1.3 V -0.3 0.8 V VIN = VCC = 3.465V 150 µA VIN = VCC = 3.465V 5 µA VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.85 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. ICS8535AG-01 www.icst.com/products/hiperclocks.html 4 REV. B JULY 5, 2001 Integrated Circuit Systems, Inc. ICS8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum ƒ≤ 266MHz 1.0 Typical Maximum Units 266 MHz 1.9 ns 30 ps fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 150 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps odc Output Duty Cycle 48 50 52 All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the 50% point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Uusing the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % ICS8535AG-01 11 www.icst.com/products/hiperclocks.html 5 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC SCOPE Qx LVPECL VCC = 2V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT Qx nQx Qy nQy tsk(o) FIGURE 3 - OUTPUT SKEW ICS8535AG-01 www.icst.com/products/hiperclocks.html 6 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 4 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R F FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME CLK0, CLK1 Q0 - Q3 nQ0 - nQ3 t PD FIGURE 6 - PROPAGATION DELAY CLK0, CLK 1, Qx nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD ICS8535AG-01 www.icst.com/products/hiperclocks.html 7 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8535-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 30.2mW = 120.8mW Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS8535AG-01 www.icst.com/products/hiperclocks.html 8 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 8 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V – (V OH_MAX Pd_L = [(V – (V OL_MAX • - 2V))/R ]*(V CC_MAX L - 2V))/R ]*(V CC_MAX L For logic high, V -V =V OH_MAX – 1.0V CC_MAX = 3.465, this results in V OUT CC_MAX = 2.465V OH_MAX For logic low, V Using V ) OL_MAX CC_MAX • ) OH_MAX CC_MAX =V OUT Using V -V CC_MAX =V =V OL_MAX – 1.7V CC_MAX = 3.465, this results in V = 1.765V OL_MAX Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW ICS8535AG-01 www.icst.com/products/hiperclocks.html 9 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8535-01 is: 412 ICS8535AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JULY 5, 2001 ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 ICS8535AG-01 www.icst.com/products/hiperclocks.html 11 REV. B JULY 5, 2001 < ICS8535-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8535AG-01 ICS8535AG-01T ICS8535AG-01 20 lead TSSOP 72 per tube 0°C to 70°C ICS8535AG-01 20 lead TSSOP on Tape and Reel 2500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8535AG-01 www.icst.com/products/hiperclocks.html 12 REV. B JULY 5, 2001