PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION Features The ICS874004 is a high performance Differentialto HCSL Jitter Attenuator designed for use in PCI HiPerClockS™ Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, highphase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874004 has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz. 200KHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. 400KHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. 800KHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5 Gb serdes have x20 multipliers while others have than x25 multipliers, the 874004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pin. • (4) Differential LVDS output pairs The ICS874004 uses ICS 3 rd Generation FemtoClock TM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express™ add-in cards. PLL BANDWIDTH ICS • (1) Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 50ps (maximum) design target • 3.3V operating supply • 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature BW_SEL 0 = PLL Bandwidth: ~200KHz Float = PLL Bandwidth: ~400KHz (Default) 1 = PLL Bandwidth: ~800KHz BLOCK DIAGRAM OEA PIN ASSIGNMENT PU F_SEL PD BW_SEL 0 = ~200KHz Float = ~400KHz 1 = ~800KHz QA0 Float 0 ÷5 (default) 1 nQA0 QA1 ÷4 nQA1 CLK PD nCLK PU PD FB_IN Phase Detector VCO 490-640MHz QB0 nQB0 nFB_IN PU QB1 nQB1 ÷5 FB_OUT nFB_OUT MR PD nQA0 nQB0 QB0 VDDO FB_OUT nFB_OUT MR BW_SEL VDDA F_SEL VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QA0 VDDO QA1 nQA1 QB1 nQB1 nFB_IN FB_IN OEB GND nCLK CLK ICS874004 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View OEB PU The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 874004AG www.icst.com/products/hiperclocks.html REV. A JANUARY 21, 2005 1 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 24 nQA0, QA0 Output Type Differential output pair. LVDS interface levels. Description 2, 3 nQB0, QB0 Output Differential output pair. LVDS interface levels. 4, 23 VDDO Power Output supply pins. 5 FB_OUT Output Non-inver ting differential feedback output. 6 nFB_OUT Output 7 MR Input 8 BW_SEL Input 9 VDDA Power Inver ting differential feedback output. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ Selects PLL Band Width input. LVCMOS/LVTTL interface levels. Pulldown Analog supply pin. 10 F_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 11 VDD Power 12 OEA Input 13 CLK Input Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. 14 nCLK Input 15 GND Power 16 OEB Input 17 FB_IN Input 18 nFB_IN Input 19, 20 nQB1, QB1 Output Differential output pair. LVDS interface levels. 21, 22 nQA1, QA1 Output Differential output pair. LVDS interface levels. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential feedback input. Pullup Inver ting differential feedback input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs Minimum Typical Units TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs Outputs OEA OEB QAx/nQAx QBx/nQBx FB_OUT/nFB_OUT BW_SEL PLL Bandwidth 0 0 HiZ HiZ Enabled 0 ~200KHz 1 1 Enabled Enabled Enabled 1 ~800KHz Float ~400KHz 874004AG Maximum www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 60 mA IDDA Analog Supply Current 8 mA IDDO Output Supply Current 82 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions F_SEL, MR, OE A , OE B BW_SEL F_SEL, MR, OEA, OEB BW_SEL Minimum Typical Maximum Units 2 VDD + 0.3 V VDD - 0.3 VDD + 0.3 V -0.3 0.8 V -0.3 0.3 V µA BW_SEL, OEA, OEB VDD = VIN = 3.465V 5 F_SEL, MR VDD = VIN = 3.465V 150 µA BW_SEL, OEA, OEB VDD = 3.465V, VIN = 0V -150 µA F_SEL, MR VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V IIL Input Low Current V PP Peak-to-Peak Input Voltage Minimum Typical Maximum Units 150 µA 5 µA 150 -150 0.15 µA 1.3 Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD - 0.85 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V. 874004AG www.icst.com/products/hiperclocks.html 3 µA V V REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 350 mV 50 mV 1.35 V 50 mV TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter, NOTE 1 tR / tF Output Rise/Fall Time Test Conditions Typical 98 20% to 80% odc Output Duty Cycle NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. 874004AG Minimum www.icst.com/products/hiperclocks.html 4 Maximum Units 160 MHz 13 ps 330 ps 50 % REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 3.3V VDD SCOPE Qx POWER SUPPLY Float GND + - nCLK, nFB_IN V LVDS V Cross Points PP CMR CLK, FB_IN nQx GND 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQAx, nQBx nQAx, nQBx QAx, QBx QAx, QBx n ➤ tcycle ➤ tcycle n+1 Pulse Width t ➤ ➤ t jit(cc) = tcycle n –tcycle n+1 odc = 1000 Cycles PERIOD t PW t PERIOD CYCLE-TO-CYCLE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD 80% 80% out VSW I N G DC Input 20% 20% tR LVDS ➤ Clock Outputs tF out ➤ VOS/∆ VOS ➤ OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP 874004AG www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 874004AG www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V Zo = 50 Ohm 3.3V 3.3V R3 125 BY R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION 874004AG www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS874004 is: 1216 874004AG www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 21, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX ICS874004 PCI EXPRESS™ JITTER ATTENUATOR FOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 874004AG www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 21, 2005 PRELIMINARY ICS874004 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS874004AG ICS874004AG 24 Lead TSSOP tube 0°C to 70°C ICS874004AGT ICS874004AG 24 Lead TSSOP 2500 tape & reel 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and PCI ExpresS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 874004AG www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 21, 2005