ICS9147-06 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUMTM General Description Features The ICS9147-06 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Glitch-free Stop clock control is provided for CPU and BUS clocks. Complete chip low current mode is achieved with the Power Down# pin. High drive BUS outputs typically provide greater than 1 V/ ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50± 5% duty cycle. The REF and IOAPIC clock outputs typically provide better than 0.5V/ns slew rates. Separate buffer supply pins VDDL allow for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs. Generates five processor, eight bus, four 14.31818 MHz, two 48 MHz clocks for USB support and one 24 MHz clock. CPU to BUS clock skew 1 to 4ns (CPU early) Synchronous clocks skew matched to 250ps window on CPU and 500ps window on BUS. Selectable multiplying ratios Glitch free stop clock controls CPUEN and BUSEN 3.0V 3.7V supply range, 2.5V to VDD supply range for CPU (1:4) clocks and IOAPIC clock. 48-pin SSOP package Pin Configuration Block Diagram 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147- 06 RevA 5/29/97P ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9147-06 Functionality 0 CPU (1:4) CPUH Tristate Tristate REF IOAPIC Tristate 24 (MHz) Tristate 48 (MHz) Tristate 0 1 60 30 14.31818 24 48 1 1 0 66.6 33.3 14.31818 24 48 1 1 1 1 REF/2 REF/4 REF REF/4 REF/2 1 1 1 0 0 X X LOW Running 14.31818 24 48 1 X X Running LOW 14.31818 24 48 0 X X X X LOW LOW LOW LOW LOW PD# BUSEN CPUEN FS1 FS0 1 1 1 0 1 1 1 1 1 1 BUS Pin Descriptions PIN NUMBER PIN NAME 1, 2, 47 REF1, REF2, REF3 3, 10, 18, 24, 30, 32, GND 37, 43, 44 TYPE DESCRIPTION OUT 14.318 MHz reference clock outputs. PWR Ground. 4 X1 IN 5 8, 9, 11, 12, 13, 14, 16, 17 26, 27 X2 OUT Crystal input, has internal crystal load capacitor, and feedback resistor from X2. Nominally 14.31818MHz. Crystal output, has internal crystal load capacitor BUS (1:8) OUT BUS clock outputs, operates synchronously at CPU/2. 7, 15, 21, 25, 34, 48 22, 23 VDD3 48M (1:2) FS (0:1) IN PWR OUT 28 PD# IN 29 CPUEN IN 36 CPUH OUT CPU (1:4) OUT 38, 39, 41, 42 6 BUSEN IN 45 IOAPIC OUT VDDL PWR 24M OUT 40, 46 33 Select pin for enabling CPU and BUS clock frequencies.* Core and Buffer output clock power supply. 48 MHz clock output Device power down input, stops outputs low and shuts off crystal oscillator and PLLs when low.* Output enable for all CPU clocks, a logic low will Stop low all CPU clocks.* 3.3 (VDD3 dependent) CPU clock output CPU clock output clocks, operates at VDDL supply voltage (with IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Output enable for all BUS clock, a logic low will stop Low all Bus clocks.* IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage with CPU (1:4), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Power supply for CPU and IOAPIC block buffers, operates at nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. 24 MHz clock output * Has internal pull-up to V DD3. 2 ICS9147-06 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V V DDL=VDD3=3.0 3.7 V, TA = 0 70° C unless otherwise stated DC C haracteristics PARAMETER SYMBOL Input Low Voltage V Input High Voltage V Input Low Current I Input High Current I IL IH IL V - V -28.0 -10.5 - µA 33.0 - mA VOH=2.0V; for CPUH, BUS & REF1 (and CPU & IOAPIC at VDDL = 3.0 to 3.7V) - -28.0 - mA VOL=0.8V; REF (2:3), 24, 48 CLKs - 26.0 - mA VOH=2.0V; REF (2:3), 24, 48 CLKs - -21.0 - mA OL3 VOL=0.8V; for CPUL at VDDL = 2.5V - 26 - mA OH3 VOH = 1.7V; for CPUL at VDDL = 2.5V - 24 - mA IOL = 10mA; for CPUH, BUS & REF1 (and CPUL at VDDL = 3.0 to 3.7V) - 0.22 0.4 V IOH = -10mA; for CPUH, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) 2.4 2.8 - V IOL = 8mA - 0.25 0.4 V IOH = -8mA OH1 Output High Current I OL2 OH2 I Output Low Voltage V Output High Voltage V V Output High Voltage V OL2 2.4 2.6 - V OL3 IOL = 8 mA; for CPUL at VDDL = 2.5V - 0.25 0.4 V OH3 IOH = -8mA; for CPUL at VDDL = 2.5V 2.1 2.25 - V - 70 140 mA 230 500 µA OH2 V V OL1 OH1 Output Low Voltage Output High Voltage 0.2VDD - I Output Low Voltage - µA Output Low Current I 0.7V DD UNITS 5.0 Output High Current Output High Current MAX - OL1 VIN=VDD TYP -5.0 IH Output Low Current Output Low Current VIN=0V MIN VOL=0.8V; for CPUH, BUS & REF1 (and CPU & IOAPIC at VDDL= 3.0 to 3.7V) I I TEST CONDITIONS Supply Current I Supply Current I DD DD @66.6 MHz; all outputs unloaded PD# Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 ICS9147-06 Electrical Characteristics at 3.3V V DDL=VDD3=3.0 3.7 V, TA = 0 70° C unless otherwise stated AC Characteristics PARAMETER Rise Time 1 SYMBOL Tr1 Fall Time1 Tf1 Rise Time1 Tr2 Fall Time1 Tf2 Rise Time1 Tr1 Fall Time1 Tf1 Rise Time1 Tr2 Fall Time1 Tf2 Rise Time1 Tr3 Fall Time1 Tf3 Rise Time1 Tr4 Fall Time1 Duty Cycle Duty Cycle Tf4 1 Dt1 Dt2 Jitter, One Sigma1 Tjis1 Jitter, Absolute1 Tjab1 1 Jitter, One Sigma Jitter, Absolute1 Input Frequency 1 Logic Input Capacitance 1 Oscillator Input Capacitance 1 Power-on Time1 Tjis2 Tjab2 Fi CIN CINX ton Clock Skew1 Tsk1 Clock Skew 1 Tsk2 Clock Skew 1 Tsk3 Clock Skew1 Tsk4 Tsk5 Tsk6 TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, BUS & REF1 20pF load, 2.0 to 0.8V CPU, BUS & REF1 20pF load, 20% to 80% CPU, BUS & REF1 20pF load, 80% to 20% CPU, BUS & REF1 30pF load, 0.8 to 2.0V CPU, BUS & REF1 30pF load, 2.0 to 0.8V CPU, BUS & REF1 30pF load, 20% to 80% CPU, BUS & REF1 30pF load, 80% to 20% CPU, BUS & REF1 20pF load, 0.8 to 2.0V 24 & 48 clocks & REF (2:3) 20pF load, 2.0 to 0.8V 24 & 48 clocks & REF (2:3) 20pF load, 0.4 to 2.0V , CPU with VDDL = 2.5V and IOAPIC 20pF load, 2.0 to 0.4V, CPU with VDDL = 2.5V and IOAPIC 20pF load @ VOUT=1.4V REF (1:3) CPU & Fixed BUS Load=20pF, BUS; Load = 30pF CPU & Fixed BUS Load=20pF, BUS; Load = 30pF REF1; Load = 47pF REF1; Load = 47pF Logic input pins X1, X2 pins From VDD=3.0V to 1st crossing of 66.6 MHz VDD supply ramp < 1 ms CPU to CPU; Load=20pF; @1.4V (Same VDD) BUS to BUS; Load=20pF; @1.4V CPU to BUS; Load=20pF; @1.4V (CPU is early) (All at 3.3V) CPU @ 2.5 to CPUH @ 3.3V CPU @ 2.5V to BUS @ 3.3V REF @ 3.3V to IOAPIC @ 2.5V MIN TYP MAX UNITS - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns - - - ns - - - - 1.6 ns - - 1.6 ns 45 40 50 45 55 50 % % - 50 150 ps -250 - 250 ps -500 12.0 - 55 200 14.318 5 18 250 500 16.0 - ps ps MHz pF pF - 1.5 3.0 ms - 150 250 ps - 300 500 ps 1 3.3 4 ns Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ns ICS9147-06 Recommended PCB Layout for ICS9147-06 NOTE: This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the different Vdd planes. 5 ICS9147-06 SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48 Ordering Information ICS9147F-06 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device 6 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.