Integrated Circuit Systems, Inc. ICS9148-47 Pentium/ProTM System Clock Chip General Description Features The ICS9148-47 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 and 12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), seven PCI (3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz, and one selectable 48/24MHz. Generates system clocks for CPU, PCI, IOAPIC , 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU, IOAPIC 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SOIC Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported. Pin Configuration Block Diagram 28 pin SOIC Power Groups VDD = Supply for PLL core VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = 48MHz VDDL = CPUCLK (0:1) VDDL1=IOAPIC Ground Groups GND = Ground Source Core GND1 = REF0, X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz GNDL = CPUCLK (0:1) Pentium is a trademark on Intel Corporation. 9148-47 Rev D 08/04/98 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-47 Pin Descriptions PIN NUMBER PIN NAME TYPE 1 X1 IN 2 3 4 5, 6, 7, 8, 10, 11 6, 9 12 13 X2 GND2 PCICLK_F PCICLK (0:5) VDD2 VDD3 48MHz OUT PWR OUT OUT PWR PWR OUT 14 24/48MHz OUT 15 GND3 PWR 16 SEL100/66.6# IN 17 18 19 20 21, 22 23 24 25 26 SCLK SDATA GND VDD CPUCLK (1:0) VDDL IOAPIC VDDL VDD1 IN IN PWR PWR OUT PWR OUT PWR PWR 27 REF0/SEL 48# OUT/IN 28 GND1 PWR DESCRIPTION XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Ground for CPUCLK (0:1) Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V IOAPIC clock output 14.318MHz. Power for IOAPIC Power for REF outputs. 14.318MHz clock output/Latched input at power up. When low, pin 14 is 48MHz. Ground for REF outputs, X1, X2. 2 ICS9148-47 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: Send the address D2(H) . Send two additional dummy bytes, a command code and byte count. Send the desired number of data bytes. See the diagram below: Clock Generator Address (7 bits) A(6:0) & R/W# D2(H) ACK + 8 bits dummy command code ACK + 8 bits dummy Byte count ACK Data Byte 1 ACK Data Byte N ACK Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must be sent. How to Read: Send the address D3(H). Send the byte count in binary coded decimal Read back the desired number of data bytes See the diagram below: Clock Generator Address (7 bits) A(6:0) & R/W# ACK Byte Count ACK Data Byte 1 D3(H) The following specifications should be observed: 1. Operating voltage for I2C pins is 3.3V 2. Maximum data transfer rate (SCLK) is 100K bits/sec. 3 ACK Data Byte N ICS9148-47 Serial Bitmap Byte 3: Functionality & Frequency Select & Spread Slect Register Bit 7 Description (Reserved) Bit 654 000 001 010 011 100 101 110 111 6:4 3 2 10 CPU PCI 68.5 75.0 83.3 66.6 103 112 133.3 100 34.25 37.5 41.6 33.3 34.3 37.3 44.43 33.33 Byte 5: PWD 0 Spread Percentage ±0.5% Center ±0.5% Center ±0.5% Center ±0.5% Center ±0.5% Center ±0.5% Center ±0.5% Center ±0.5% Center 0 - Frequency is selected by hardware select SEL100/66.6# 1 - Frequency is selected by 6:4 above (Reserved) 00 - Normal operation 01 - Test mode 10 - Spread sprectrum ON 11 - Tristate all outputs 0 0 00 Bit Pin# Pin Name PWD 7 4 PCICLK_F 1 6 11 PCICLK5 1 5 10 PCICLK4 1 4 - - 0 3 8 PCICLK3 1 2 7 PCICLK2 1 1 6 PCICLK1 1 0 5 PCICLK0 1 Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 4: Byte 6: Bit Pin# Pin Name PWD 7 6 5 4 3 - - - 2 21 CPUCLK1 1 1 - - 0 0 22 CPUCLK0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Bit Pin# Pin Name PWD 7 6 - - 0 0 5 24 IOAPIC 1 4 3 2 - - 0 0 0 1 27 REF0 1 0 27 REF0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Disabled) Enabled (low) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default For pin 27, there are 2 output stages together for 1 pin. These 2 latches must be both 0 or 1 simultaneously or there will be a short to ground if one is disabled and the other is running. 4 ICS9148-47 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3PD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors -200 CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND Fi VDD = 3.3 V; CIN CINX Logic Inputs X1 & X2 pins Ttrans To 1st crossing of target Freq. TYP 0.1 2.0 -100 60 66 3 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 170 170 650 14.318 27 Settling Time1 Ts From 1st crossing to 1% target Freq. Clk Stabilization 1 Skew1 TSTAB From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; TAGP-PCI1 MIN 2 VSS-0.3 Guaranteed by design, not 100% tested in production. 5 36 3.5 µA MHz 5 45 pF pF 3 ms 3 ms 4 ns 5 1 mA ms ICS9148-47 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew 1 SYMBOL IDD2.5OP66 IDD2.5OP100 IDD2.5PD tCPU-AGP tCPU-PCI2 CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND MIN 0 1 VT = 1.5 V; VTL = 1.25 V TYP 16 23 MAX 72 100 UNITS mA mA 10 100 µA 0.5 2.6 1 4 ns ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B VOL = 0.4 V, VOH = 2.0 V Fall Time t f2B 1 VOH = 2.0 V, VOL = 0.4 V Duty Cycle d t2B1 VT = 1.25 V 1 Skew tsk2B Jitter, Cycle-to-cycle tjcyc-cyc2B1 tj1s2B1 tjabs2B1 Jitter, One Sigma Jitter, Absolute MIN 2 19 1 Rise Time 1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V TYP 2.3 0.2 -41 37 MAX UNITS V 0.4 V -19 mA mA 1.25 1.6 ns 1 1.6 ns 48 55 % VT = 1.25 V 30 175 ps VT = 1.25 V 150 250 ps 45 VT = 1.25 V VT = 1.25 V -250 Guaranteed by design, not 100% tested in production. 6 40 150 ps 140 +250 ps ICS9148-47 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 TYP 3.1 0.1 -62 57 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns d t1 VT = 1.5 V 50 55 % tsk1 VT = 1.5 V 140 500 ps tj1s1 VT = 1.5 V 17 150 ps tjabs1 VT = 1.5 V -500 70 500 ps MIN 2 TYP 2.2 0.33 -41 37 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Skew1 1 1 1 CONDITIONS IOH = -18 mA IOL = 18 mA VOH = 1.7 V VOL = 0.7 V 29 MAX UNITS V 0.4 V -28 mA mA Tr4B VOL = 0.4 V, VOH = 2.0 V 1.3 1.6 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns Dt4B VT = 1.25 V 54 55 % VT = 1.25 V 60 250 ps Tj1s4B VT = 1.25 V 1 3 % Tjabs4B VT = 1.25 V 5 % tsk4B Jitter, One Sigma Jitter, Absolute SYMBOL VOH4B VOL4B IOH4B IOL4B 1 45 -5 Guaranteed by design, not 100% tested in production. 7 ICS9148-47 Electrical Characteristics - 48, 24 MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 TYP 3 0.14 -44 42 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.2 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.2 4 ns d t5 VT = 1.5 V 52 55 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 29 TYP 3.1 0.17 -44 42 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns d t5 VT = 1.5 V 54 57 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % 47 Guaranteed by design, not 100% tested in production. 8 ICS9148-47 SOIC Package LEAD COUNT 28L DIMENSION L 0.704 Ordering Information ICS9148M-47 Example: ICS XXXX M - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.