ICS9158-05 Integrated Circuit Systems, Inc. Advanced Information Buffered Clock Generator for Pentium™ /Triton™ Systems General Description Features The ICS9158-05 is a low cost frequency generator designed specifically to clock Pentium systems using the Triton chip set. Three copies of the CPU clock are available at 50, 60, or 66.7 MHz. Five copies of the synchronous BUS clock run at half the CPU frequency. A 14.318 MHz REFCLK, 12 MHz, KEYBD, and 24 MHz FLOPPY clock are also provided. • • • • • • • • • • Each high drive output is capable of driving a 30pF load with better than 1V/ns typical slew and have a duty cycle of 50±5%. The synchronous outputs are skew controlled to within ±250ps and CPU clocks lead BUS clocks by 2-5ns. Glitch-free start and stop of the CPU and BUS clocks is provided as well as a power-down mode with all clocks forced low and the internal oscillators and PLLs powered-down. Power-up time is less than 10ns. All frequency transitions are gradual and meet the Intel cycle-to-cycle timing specification for 486 and Pentium microprocessors. 3 CPU and 5 synchronous BUS clocks 50/60/66 MHz and glitch-free stop clock selections ±250ps skew between all synchronous outputs Outputs drive up to 30pF load with 1V/ns slew 2-5ns early CPU clocks support Triton chip set Compatible with 486 and Pentium CPUs Consumes less than 10µA in power-down mode On-chip loop filter components 3.0V - 5.5V supply range 24-pin SOIC package Applications • Ideal for RISC or CISC systems such as 486, Pentium, PowerPC,™ etc. requiring multiple CPU and synchronous BUS clocks. Block Diagram Pentium and Triton are trademarks of Intel Corporation. PowerPC is a trademark of Motorola Corporation 9158-05 Rev B 05/08/97 ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9158-05 Advanced Information Functionality Pin Configuration VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated OE PD# FS1 FS0 CPU Ratio 1 1 1 1 0 0 0 1 14/4xX1 14/3xX1 1 1 1 1 1 1 0 1 1 0 X X 0 X X X 42/10xX1 (STOP) (PWR DOWN) - CPU (0:2) (MHz) 50 66.7 BUS (0:4) (MHz) 25 33.3 14.318 14.318 60 Low 30 Low Low *Low *Low Tristate Tristate Tristate PD# forces all outputs low and powers-down the oscillator and PLL circuitry, minimizing power consumption. In order to ensure glitch-free start and stop of the CPU and BUS clocks, PD# should be asserted after the CPU and BUS clocks have stopped, and be deasserted 10ms (maximum PLL lock time) prior to starting the clocks. 24-Pin SOIC OE 1 PD# 1 FLOPPY (MHz) 24 KEYBD (MHz) 12 1 0 0 X Low Tristate Low Tristate Pin Descriptions for ICS9158-05 PIN NUMBER 1 X1,X2, REF (MHz) 14.318 14.318 PIN NAME REFCLK TYPE OUT 2 X2 OUT 3 X1 IN 4 5 6 VDD GND KEYBD PWR PWR OUT Crystal connection, which includes output crystal load capacitance. Crystal connection, which includes crystal load capacitance and feedback bias for a nominal 14.31818 MHz parallel-resonance 12pF crystal. Digital POWER SUPPLY. Digital GROUND. 12 MHz keyboard clock output. 7 8 9 10 11 FLOPPY BUS0 AGND OE BUS1 OUT OUT PWR IN OUT 24 MHz floppy disk clock output. BUS clock output. ANALOG GROUND. OUTPUT ENABLE. Tristates all outputs when low.* BUS clock output. 12 13 14 15 16 GND CPU0 CPU1 PD# AVDD PWR OUT OUT IN PWR Digital GROUND. CPU clock output. CPU clock output. Power-down input shuts off both PLL stages when low.* ANALOG power supply. 17 18 19 20 21 BUS2 BUS3 GND VDD CPU2 OUT OUT PWR PWR OUT CPU clock output. BUS clock output. Digital GROUND. Digital POWER SUPPLY. CPU clock output. OUT IN IN BUS clock output. Clock frequency select #1.* Clock frequency select #0.* 22 BUS4 23 FS1 24 FS0 * Input pin has internal pull-up to VDD. DESCRIPTION 14.318 clock output. 2 ICS9158-05 Advanced Information Absolute Maximum Ratings AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V VDD = +5V±10%, TA =0°C to 70°C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage1 1 SYMBOL VIL VIH IIL IIH VOL VOH Output Low Current Output High Current1 Supply Current Output Frequency Change over Supply and Temperature1 Short circuit current1 IOL IOH IDD Pull-up resistor value1 Input Capacitance1 Load Capacitance1 TEST CONDITIONS VIN=0V (Pull-up) VIN=VDD IOL=20.0mA IOH=-30mA MIN 2.0 -20 -5 2.4 VOL=0.8V VOH=2.0V No load, 66 MHz With respect to typical frequency 45 ISC Each output clock 25 RPU Ci CL Input pin Except X1, X2 Pins X1, X2 FD TYP 0.25 3.5 MAX UNITS 0.8 V V µA µA V V 5 0.4 65 -55 67 -35 100 mA mA mA 0.002 0.01 % 56 mA 680 kΩ pf pf 8 20 Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 ICS9158-05 Advanced Information Electrical Characteristics ( continued) VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Output Rise time, 0.8 to 2.0V (Note 1) tr 30pf load - 1 1.5 ns Rise time, 20% to 80% VDD (Note 1) tr 30pf load - 2.5 3 ns Output Fall time, 2.0 to 0.8V1 tf 30pf load - 0.5 1.5 ns Fall time, 80% to 20% VDD1 tf 30pf load - 1.5 2 ns Duty cycle1 dt 30pf load 45/55 48/52 55/45 % Jitter, one sigma1 tj1s 0.5 2.0 % Jitter, absolute tjab As compared with clock period 2 5 % Jitter, absolute tjab 25-66MHz clocks 250 ps Input Frequency -5 -250 fi 14.318 Clock skew between CPU and 2XCPU outputs Tsk 100 250 ps Frequency Transition Time1 tft 13 20 ms From 4 to 50 MHz Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 MHz ICS9158-05 Advanced Information Electrical Characteristics at 3.3V VDD = +3.3V±10%, TA =0°C to 70°C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage SYMBOL VIL VIH TEST CONDITIONS MIN IIL IIH VOL VOH VIN =0V(Pull-up) VIN =VDD IOL=10mA IOH =-5mA Output Low Current 1 Output High Current 1 Supply Current Output Frequency Change over Supply and Temperature1 IOL IOH IDD VOL=0.2VDD VOH =0.7VDD No load, 66 MHz With respect to typical frequency 20 Short Circuit Current 1 ISC RPU Ci CL Each output clock Input pin Except X1, X2 Pins X1, X2 25 Pull-up Resistor Value 1 Input Capacitance 1 Load Capacitance1 MAX 0.8 2.0 Input Low Current Input High Current Output Low Voltage Output High Voltage1 FD TYP -10 -5 0.1V DD 0.85VDD UNITS V V µA µA V V 30 -15 43 -10 65 mA mA mA 0.002 0.01 % 56 900 8 20 mA kΩ pF pF AC Characteristics PARAMETER Output Rise time, 0.8 to 2.0V1 1 Rise time, 20% to 80% VDD Output Fall time, 2.0 to 0.8V1 Fall time, 80% to 20% VDD1 Duty cycle1 Jitter, one sigma1 1 Jitter, absolute Jitter, absolute1 Input Frequency Clock skew window between CPU and 2XCPU outputs1 Frequency Transition time 1 SYMBOL tr TEST CONDITIONS 30pF load tr tf tf dt tj1s tjab 30pF 30pF 30pF 30pF load load load load tjab fi 25-66 MHz clocks As compared with clock period TYP MAX UNITS - 1 3.0 ns 40/50 2.5 0.5 1.5 44/46 4.0 2.5 4.0 50/40 ns ns ns % 0.5 2 2.0 5 % % 300 ps MHz 100 250 ps 13 20 ms 14.318 Tsk tft MIN From 4 to 50 MHz Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 ICS9158-05 Advanced Information ICS9158-05 CPU Clock DecodingTable Frequency Transitions (using 14.318 MHz input. All frequencies in MHz) A key feature of the ICS9158-05 is its ability to provide smooth, glitch-free frequency transitions on the CPU and BUS clocks when the frequency select pins are changed. The frequency transition rate does not violate the Intel 486 or Pentium specification of less than 0.1% frequency change per clock period. VDD=5V±10% or 3.3V±10%, TEMP=0-70°C X1,X2, REF (MHz) 14.318 14.318 OE PD# FS1 FS0 CPU Ratio 1 1 1 1 0 0 0 1 14/4xX1 14/3xX1 1 1 1 1 1 1 0 1 1 0 X X 0 X X X 42/10xX1 14.318 (STOP) 14.318 (PWR Low DOWN) Tristate CPU (0:2) (MHz) 50 66.7 BUS (0:4) (MHz) 25 33.3 60 Low 30 Low *Low *Low Tristate Tristate Using an Input Clock as a Reference The ICS9158-05 is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is possi-ble to use a crystal oscillator or other clock sources. Please see application note AAN04 for details on driving the ICS9158-05 with a clock. PD# forces all outputs low and powers-down the oscillator and PLL circuitry, minimizing power consumption. In order to ensure glitch-free start and stop of the CPU and BUS clocks, PD# should be asserted after the CPU and BUS clocks have stopped, and be deasserted 10ms (maximum PLL lock time) prior to starting the clocks. OE 1 PD# 1 FLOPPY (MHz) 24 KEYBD (MHz) 12 1 0 0 X Low Tristate Low Tristate 6 ICS9158-05 Advanced Information 24 Lead SOIC LEAD COUNT DIMENSION L 24L 0.604 Ordering Information ICS9158-05M Example: ICS XXXX-PPP M Package Type M=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 7 ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.