Integrated Circuit Systems, Inc. ICS9159-07 Frequency Generator for NexGen™ Nx586 Systems General Description Features The ICS9159-07 is a low-cost frequency generator designed specifically for NexGen Nx586 systems. The integrated buffer minimizes skew and provides the CPU clocks required by the NexGen Nx586 microprocessor. A 14.318 MHz XTAL oscil-lator provides the reference clock to generate standard Nx586 frequencies. The CPU clock makes gradual frequency transi-tions without violating the PLL timing of internal microproc-essor clock multipliers. • Three CPU clocks operate up to 65 MHz at 3.3V, plus smooth transitions • Selection of nine frequencies, tristate • Seven BUS clocks support sync or async bus operation • Integrated buffer outputs drive up to 10pF loads Either synchronous (2XCPU/3) or asynchronous (32 MHz) PCI bus operation can be selected. Green PC systems are supported through doze mode. • 3.13 to 5.25V (3.3±5%, 5.0±5%) supply range • 28-pin SOIC package • Clock duty cycles 45/55 Applications • Ideal for NexGen Nx586 PCI-based motherboard designs Block Diagram NexGen is a trademark of NexGen Corporation. 9159-07 Rev C 060697 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9159-07 Pin Configuration 28-Pin SOIC Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz XTAL. Normally, 14.318 MHz. 1 X1 IN 2 X2 OUT XTAL output which includes XTAL load capacitance. CPU(0:2) OUT Processor clock outputs which are a multiple of the input reference frequency as shown in the table below. 3, 11, 23 GND PWR Device Ground. 4, 5, 14 FS(0:2) 6,7, 9 8, 26 VDD IN PWR Frequency multiplier select pins. See table below. These inputs have internal pullup devices.* Positive power supply. 10 OE IN Output Enable. All outputs tristate when low.** 12 DOZE# IN Reduces CPU clock frequency to 10 MHz when at a logic low level.* 13 BSEL# IN Synchronous and non-synchronous bus clock selector.* ASYNC=0, SYNC=1 15, 16, 18 19, 21, 22, 27 BCLK(0:6) OUT Bus clock outputs are fixed at 2 ¤3 the PCLK frequency. 20 VDDB PWR Power for BUS output buffers. 17 GNDB PWR This ground return path is brought on separately to permit separating the noise impulses from high output buffers from affecting sensitive internal circuitry.*** 24 DISK OUT Fixed 24 MHz clock (with 14.318 MHz input). 25 KEYBD OUT Fixed 12 MHz clock (with 14.318 MHz input). 28 REF OUT REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. * Internally pulled-up. ** External pull-up resistor of 5 to 20 kW recommended due to dynamic coupling of adjacent CPU pins. *** Ground for bus clock buffers. 2 ICS9159-07 Functionality 14.318 MHz Input, all frequencies in MHz. OE FS2 FS1 FS0 DZE CPU (0:2) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X X 1 1 1 1 1 1 1 1 0 X 65 60 55.5 51 46.5 42 37.5 35 10 Tristate Actual CPU Frequencies CPU Frequency (MHz) Actual Frequency (MHz) 65 60 55.5 51 46.5 42 37.5 35 10 Tristate 64.98 60.03 55.50 51.00 46.53 42.00 37.48 35.00 10.00 Tristate 3 BUS 0:6 BSEL=1 43.3 40 37 34 31 28 25 23.3 6.6 Tristate BSEL=0 32 32 32 32 32 32 32 32 32 Tristate ICS9159-07 Absolute Maximum Ratings Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0°C to +70°C Storage Temperature ........................................................................... –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7V DD - - V Input Low Current IIL VIN =0V - 25.0 -5.0 µA Input High Current IIH VIN =VDD -5.0 - 5.0 µA 1 IOL VOL=0.8V; for PCLKS & BCLKS 30.0 47.0 - mA Output High Current1 IOH VOL=2.0V; for PCLKS & BCLKS - -66.0 -42.0 mA 1 IOL VOL=0.8V; for fixed CLKs 25.0 38.0 - mA Output Low Current Output Low Current Output High Current 1 IOH VOL=2.0V; for fixed CLKs - -47.0 -30.0 mA Output Low Voltage 1 VOL IOL=15mA; for PCLKS & BCLKS - 0.3 0.4 V Output High Voltage 1 VOH IOH=-30mA; for PCLKS & BCLKS 2.4 2.8 - V Output Low Voltage 1 VOL IOL=12.5mA; for fixed CLKs - 0.3 0.4 V Output High Voltage 1 VOH IOH=-20mA; for fixed CLKs 2.4 2.8 - V ICC CPU @65.0 MHz; BUS @ 43.3 MHz; all outputs unloaded - 80.0 130.0 mA Supply Current Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9159-07 Electrical Characteristics at 3.3V VDD = 3.1 – 3.7 V, TA = 0 – 70° C AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Rise Time Tr1 20pF load; 0.8 to 2.0V - 0.9 1.5 ns Fall Time1 Tf1 20pF load; 2.0 to 0.8V - 0.8 1.4 ns Tr2 20pF load; 20% to 80% - 1.5 2.5 ns Tf2 20pF load; 80% to 20% - 1.4 2.4 ns Dt 20pF load; VOUT=1.4V 45 50 55 % -150 50 +150 ps 1 1 Rise Time 1 Fall Time Duty Cycle 1 1 Jitter Cycle-to-Cycle CPU(0:2) BUS(0:6) Tjcc1 Load=10pF Slew1 SR1 Load=10pF; 0.8 to 2.0V 1.0 1.6 A V/ns Jitter 1Cycle-to-Cycle Tjcc2 Load=10pF -250 - 250 ps SR2 Load=30pF; 0.8 to 2.0V Fixed CLK; Load=20pF; Comp. to the period Fixed CLK; Load=20pF; Comp. to the period A 0.6 1.0 A V/ns - 1 3 % - 2 5 % 12.0 14.318 16.0 MHz Slew 1 Jitter, One Sigma1 Tjis Jitter, Absolute1 Tjab Input Frequency1 Logic Input Capacitance Fi 1 Crystal Oscillator Capacitance 1 CIN Logic input pins - 5 - pF CINX X1, X2 pins Acquisition from 35 MHz to 65 MHz (first crossing) (and 65 to 35). Acquisition from 10 MHz to 65 MHz (first crossing) (and 65 to 10) From 1 st crossing of acquisition to <1% settling. - 18 - pF - 0.46 1.4 ms - 0.76 2.3 ms - 400 - ms Frequency Transition Time1 Ta1 Frequency Transition Time (to DOZE)1 Ta2 Frequency Settling Time 1 1 Skew ts CPU to CPU TSK1 -250 - +250 CPU to BUS(0:5) TSK2 -600 200 1000 CPU to BUS(6) TSK3S -900 -400 110 BUS(0:5) to BUS(0:5) TSK4 -500 - +500 BUS(0:5) to BUS(6) TSK5 -1050 -550 250 CL=10pF VO=1.5V Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 ps ICS9159-07 Electrical Characteristics at 5.5V VDD = 4.5 – 5.5 V, TA = 0 – 70 ° C DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.8 V Input High Voltage VIH 2.0 - - V Input Low Current IIL VIN=0V -45.0 -15.0 A mA Input High Current IIH VIN=VDD , other logic inputs -5.0 - 5.0 mA VIN=VDD , OE pin -5.0 A 400.0 mA Input High Current Output Enable Pin2 IIH(OE) Output Low Current 1 IOL VOL=0.8V; for PCLKS & BCLKS 36.0 62.0 - mA Output High Current 1 IOH VOL=2.0V; for PCLKS & BCLKS - -152.0 -90.0 mA 1 IOL VOL=0.8V; for fixed CLKs 30.0 50.0 - mA Output High Current 1 IOH VOL=2.0V; for fixed CLKs - -110.0 -65.0 mA Output Low Voltage1 VOL IOL=20mA; for PCLKS & BCLKS - 0.25 0.4 V Output High Voltage1 VOH IOH=-70mA; for PCLKS & BCLKS 2.4 4.0 - V 1 VOL IOL=15mA; for fixed CLKs - 0.2 0.4 V Output High Voltage1 VOH IOH=-50mA; for fixed CLKs 2.4 4.7 - V Supply Current ICC CPU @65.0 MHz; BUS @ 43.3 MHz; all outputs unloaded - 130.0 220.0 mA Output Low Current Output Low Voltage Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 6 ICS9159-07 Electrical Characteristics at 5.5V VDD = 4.5 – 5.5 V, TA = 0 – 70 ° C AC Characteristics PARAMETER SYMBOL 1 TEST CONDITIONS MIN TYP MAX UNITS Tr1 20pF load; 0.8 to 2.0V - 0.55 0.95 ns Fall Time Tf1 20pF load; 2.0 to 0.8V - 0.52 0.90 ns Rise Time1 Tr2 20pF load; 20% to 80% - 1.2 2.1 ns Tf2 20pF load; 80% to 20% - 1.1 2.0 ns Dt 20pF load; VOUT=1.4V 45 50 55 % Rise Time 1 1 Fall Time Duty Cycle 1 CPU(0:2) 1 Tjcc1 Load=10pF -150 50 +150 ps 1 SR1 Load=10pF; 0.8 to 2.0V 1.6 2.6 - V/ns 1 Jitter Cycle-to-Cycle Tjcc2 Load=10pF -250 - 250 ps Slew1 SR2 Load=30pF; 0.8 to 2.0V Fixed CLK; Load=20pF; Comp. to the period Fixed CLK; Load=20pF; Comp. to the period 1.0 1.6 - V/ns - 1 3 % - 2 5 % Jitter Cycle-to-Cycle Slew BUS(0:6) Jitter, One Sigma1 Tjis Jitter, Absolute1 Tjab Input Frequency1 Fi Logic Input Capacitance1 Crystal Oscillator Capacitance 1 12.0 14.318 16.0 MHz CIN Logic input pins - 5 - pF CINX X1, X2 pins Acquisition from 35 MHz to 65 MHz (first crossing) (and 65 to 35). Acquisition from 10 MHz to 65 MHz (first crossing) (and 65 to 10) From 1 st crossing of acquisition to <1% settling. - 18 - pF - 0.50 1.5 ms - 0.78 2.4 ms - 400 - ms Frequency Transition Time1 Ta1 Frequency Transition Time (to DOZE)1 Ta2 Frequency Settling Time 1 1 Skew ts CPU to CPU TSK1 -250 - +250 CPU to BUS(0:5) TSK2 -1600 -800 0 CPU to BUS(6) TSK3S -1750 -1250 -750 BUS(0:5) to BUS(0:5) TSK4 -500 - +500 BUS(0:5) to BUS(6) TSK5 -900 -400 -100 CL=10pF VO=1.5V Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 7 ps ICS9159-07 Typical Timing Diagram of Outputs Showing Skew Relationship Clock Singles Note that the skew is rising edge to rising edge. The CPU is runniing at VCO/2 and the BUS clock is runing at VCO/3 resulting in the output rising edges being coincident every 3rd pulse. 8 ICS9159-07 LEAD COUNT 28L DIMENSIONL 0.704 SOIC Package Ordering Information ICS9159M-07 Example: ICS XXXX M-PPP Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC, SOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.