Integrated Circuit Systems, Inc. ICS9248-150 Frequency Generator for Multi - Processor Servers Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCICLK VDD48 FS0/48MHz FS1/48MHz# GND48 VDDCPU CPUCLKT0 CPUCLKC0 GNDCPU CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT2 CPUCLKC2 GNDCPU CPUCLKT3 CPUCLKC3 VDDCPU REF SPREAD# GNDREF X1 X2 VDDREF ICS9248-150 Recommended Application: ServerWorks Grand Champion Systems. Output Features: • 8 - Differential CPU Clock Pairs @ 3.3V • 1 - 3V 33MHz PCI clocks • 1 - 48MHz clock • 1 - Inverted 48MHz clock • 1 - 14.318 reference output Features: • Up to 200MHz frequency support • Support power management: Power Down Mode • Supports Spread Spectrum modulation: 0 to -0.5% down spread. • Uses external 14.318MHz crystal • Select logic for Differential Swing Control, Test mode, Tristate, Power down, Spread Spectrum. • External resistor for current reference • FS pins for frequency select Key Specifications: • PCI Output jitter <500ps • CPU Output jitter <200ps • 48MHz Output jitter <350ps • REF Output jitter < 1000ps 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL100/133 GNDPCI VDDA GNDA PD# VDDCPU CPUCLKT4 CPUCLKC4 GNDCPU CPUCLKT5 CPUCLKC5 VDDCPU CPUCLKT6 CPUCLKC6 GNDCPU CPUCLKT7 CPUCLKC7 VDDCPU MULTSEL0 MULTSEL1 GND GNDI REF I REF VDDI REF 48-Pin SSOP and TSSOP Functionality Block Diagram SEL133/ 100 FS0 FS1 0 0 0 Active 100MHz 0 0 1 100MHz Test Mode 0 1 0 100MHz Test Mode 0 1 1 Tristate all outputs 1 0 0 Active 133MHz 1 0 1 133MHz Test Mode 1 1 0 Active 200MHz 1 1 1 Reserved Function PLL2 Analog Power Groups VDD48, GND48 = 48MHz, PLL2 VDDA=VDD (core supply voltage 3.3V) GNDA=Ground for core supply 48MHz 48MHz# X1 X2 XTAL OSC PLL1 Spread Spectrum REF CPU DIVDER 8 PCI DIVDER PD# SPREAD# MULTSEL(1:0) SEL100/133 FS(1:0) 8 CPUCLKT (7:0) CPUCLKC (7:0) PCICLK Control Logic Config. Reg. I REF Digital Power Group VDDREF, GNDREF = REF, Xtal 9248-150 Rev B 06/12/01 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is ICS9248-150 General Description The ICS9248-150 is a main clock for ServerWorks Grand Champion Systems. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-150 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Configuration PIN NUMBER PIN NAME TYPE 1 PCICLK OUT PCI clock output 2, 6, 12, 18, 24, 31, 37, 43, VDD PWR 3.3V power supply 3 DESCRIPTION FS0 IN Frequency select pin 48MHz OUT 48MHz clock output FS1 IN 48MHz# OUT Inverted 48MHz clock output 5, 9, 15, 21, 28, 34, 40, 47 GND PWR Ground pins for 3.3V supply 33, 36, 39, 42, 16, 13, 10, 7 CPUCLKT (7:0) OUT "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 32, 35, 38, 41, 17, 14, 11, 8 CPUCLKC (7:0) OUT "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 19 REF OUT 4 20 SPREAD# IN Frequency select pin Reference output 14.318MHz Invokes Spread Spectrum functionality on the Differential host clocks, Active Low 22 X1 X2 Crystal Input 14.318MHz Crystal input 23 X2 X1 Crystal Output 14.318MHz Crystal output 25, 46 VDDI REF VDDA, PWR Analog power supply 3.3V 26 I REF OUT This pin establishes the reference current for the CPUCLK pairs. This pin takes a fixed precision resistor tied to ground in order to establish the required current. 29, 30 MULTSEL(1:0) IN CPU swing select inputs 44 PD# IN Invokes power-down mode. Active Low. 27, 45 GNDI REF GNDA PWR 48 SEL100/133 IN Analog Ground pins for 3.3V supply CPU Frequency Select. Low=100MHz, High=133MHz Third party brands and names are the property of their respective owners. 2 ICS9248-150 Truth Table SEL 133/100 FS0 FS1 CPUCLK MHz PCICLK MHZ 48 MHz 0 0 0 100 33 48 0 0 1 100 33 Disable 0 1 0 100 Disable Disable 0 1 1 Tristate Tristate Tristate 1 0 0 133 33 48 1 0 1 133 33 Disable 1 1 0 200 33 48 1 1 1 TCLK/2 TCLK/8 TCLK/2 CPUCLK Buffer Configuration Conditions Iout Vdd = nominal (3.30V) Iout Vdd = 3.30 ± 5% Configuration All combinations of M0, M1 and Rr shown in table below All combinations of M0, M1 and Rr shown in table below Load Min Max Nominal test load for given configuration -7% I nominal +7% I nominal Nominal test load for given configuration -12% I nominal +12% I nominal Third party brands and names are the property of their respective owners. 3 ICS9248-150 CPUCLK Swing Select Functions MULTSEL0 MULTSEL1 Board Target Trace/Term Z 0 0 60 ohms 0 0 50 ohms 0 1 60 ohms 0 1 50 ohms 1 0 60 ohms 1 0 50 ohms 1 1 60 ohms 1 1 50 ohms 0 0 30 (DC equiv) 0 0 25 (DC equiv) 0 1 30 (DC equiv) 0 1 25 (DC equiv) 1 0 30 (DC equiv) 1 0 25 (DC equiv) 1 1 30 (DC equiv) 1 1 25 (DC equiv) Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Third party brands and names are the property of their respective owners. 4 Output Current Voh @ Z, Iref=2.32mA Ioh = 5*Iref 0.71V @ 60 Ioh = 5*Iref 0.59V @ 50 Ioh = 6*Iref 0.85V /2 60 Ioh = 6*Iref 0.71V @ 50 Ioh = 4*Iref 0.56V @ 60 Ioh = 4*Iref 0.47V @ 50 Ioh = 7*Iref 0.99V @ 60 Ioh = 7*Iref 0.82V @ 50 Ioh = 5*Iref 0.75V @ 30 Ioh = 5*Iref 0.62V @ 20 Ioh = 6*Iref 0.90V @ 30 Ioh = 6*Iref 0.75V @ 20 Ioh = 4*Iref 0.60 @ 20 Ioh = 4*Iref 0.5V @ 20 Ioh = 7*Iref 1.05V @ 30 Ioh = 7*Iref 0.84V @ 20 ICS9248-150 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND –0.5 V to VDD +0.5 V 0°C to +70°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH VIN = 0 V; Inputs with no pull-up resistors IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 Operating Supply IDD3.3OP CL = 0 pF; Select @ 100 MHz Current CL = 0 pF; Input address to VDD or GND Powerdown Current IDD3.3PD Input Frequency Pin Inductance Input Capacitance1 Transition time 1 1 Settling time Clk Stabilization1 Delay1 1 Fi Lpin CIN COUT CINX VDD = 3.3 V Ttrans MIN 2 VSS-0.3 -5 -5 -200 TYP 181 52 MAX VDD+0.3 0.8 5 250 60 14.318 UNITS V V µA µA mA mA 7 5 6 45 MHz nH pF pF pF To 1st crossing of target frequency 3 ms Ts From 1st crossing to 1% target frequency 3 ms TSTAB tPZH,tPZL tPHZ,tPLZ From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 3 10 10 ms ns ns Logic Inputs Output pin capacitance X1 & X2 pins 27 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 5 1 1 ICS9248-150 Electrical Characteristics - CPU T A = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance 1 CONDITIONS M IN TYP M A X UNITS VO = VD D *(0.5) 714 Ω VO = VD D *(0.5) IO H = -1 mA IO L = 1 mA 714 0.4 Ω V V RD SN 2 B VO H 2 B VO L 2 B Output High Current 2 V O H @ MIN = 1.0 V, V O H @ MA X = 2.375 V -27 -27 mA 2 VO L @ MIN = 1.2 V, VO L @ MA X = 0.3 V 27 30 mA VO L = 20%, VO H = 80% 175 324 700 ps VO H = 80%, VO L = 20% VD D = 3.3V 175 45 501 50 700 55 ps % VT = 50% 45 51.2 55 % VT = 50% 83.8 100 ps VT = 50% 78.5 100 ps VT = 50% 86 150 ps Ris e Time Fall Time Diff. Cros s over Voltag Duty Cycle Skew CPUT0:7 Skew CPU C0:7 Jitter 2 RD SP 2 B 1 Output Impedance Output High Voltage Output Low Voltage Output Low Current 1 SYM BOL IO H 2 B IO L 2 B t r2 B 1 1 t f2 B Vx d t2 B 1 t sk 2 B t sk 2 B 1 1 t jcy c-cyc 1 2 Guaranteed by des ign, not 100% tes ted in production. IO W T can be varied and is s electable thru the M ULTSEL pin. Electrical Characteristics - REF TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance 1 TYP VO = VDD*(0.5) 20 48 IOH = -1 mA 2.4 Output High Voltage VOH Output Low Voltage Output High Current IOL = 1 mA Skew VOL1 1 IOH IOL1 tr11 tf11 dt11 tsk11 Jitter tjcyc-cyc1 VT = 1.5 V Output Low Current Rise Time Fall Time Duty Cycle 1 RDSP11 MIN MAX UNITS MHz 60 Ω V V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 0.4 V mA VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA VOL = 0.4 V, VOH = 2.4 V 1 1.6 4 ns VOH = 2.4 V, VOL = 0.4 V 1 2.4 4 VT = 1.5 V 45 53.5 55 ns % N/A ps 1000 ps VT = 1.5 V 305 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 6 ICS9248-150 Electrical Characteristics - PCI TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance 1 TYP VO = VDD*(0.5) 12 33 IOH = -1 mA 2.4 Output High Voltage VOH Output Low Voltage Output High Current IOL = 1 mA Skew VOL1 1 IOH 1 IOL tr11 tf11 dt11 tsk11 Jitter tjcyc-cyc1 VT = 1.5 V Output Low Current Rise Time Fall Time Duty Cycle 1 RDSP11 MIN MAX UNITS MHz 55 Ω V 0.55 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 V mA VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA VOL = 0.4 V, VOH = 2.4 V 0.5 1.2 2 ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.2 2 VT = 1.5 V 45 49.9 55 ns % 500 ps 139.7 500 ps VT = 1.5 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance 1 TYP VO = VDD*(0.5) 20 48 IOH = -1 mA 2.4 Output High Voltage VOH Output Low Voltage Output High Current IOL = 1 mA Skew VOL1 1 IOH 1 IOL tr11 tf11 dt11 tsk11 Jitter tjcyc-cyc1 VT = 1.5 V Output Low Current Rise Time Fall Time Duty Cycle 1 RDSP11 MIN MAX UNITS MHz 60 Ω V 0.4 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 V mA VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA VOL = 0.4 V, VOH = 2.4 V 1 1.3 4 ns VOH = 2.4 V, VOL = 0.4 V 1 1.6 4 VT = 1.5 V 45 52.5 55 ns % VT = 1.5 V 175 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 7 N/A ps 350 ps ICS9248-150 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PD# CPUCLKT CPUCLKC VCO Crystal Notes: 1. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock. Third party brands and names are the property of their respective owners. 8 ICS9248-150 c N SYMBOL L E1 INDEX AREA E 1 2 h x 45° D A A A1 b c D E E1 e h L N α A1 -Ce SEATING PLANE b .10 (.004) C N 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS9248yF-150-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is ICS9248-150 c N L E1 INDEX AREA E 1 2 D A A2 A1 -Ce In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N SEATING PLANE b aaa C 48 D mm. MIN 12.40 D (inch) MAX 12.60 MIN .488 MAX .496 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICS9248yG-150-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is