ICS93732 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps • CYCLE - CYCLE jitter (>200MHz): <75ps • OUTPUT - OUTPUT skew: <100ps • DUTY CYCLE: 49.5% - 50.5% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ICS93732 Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input DDRC0 DDRT0 VDD DDRT1 DDRC1 GND SCLK CLK_INT N/C VDDA GND VDD DDRT2 DDRC2 GND DDRC5 DDRT5 DDRC4 DDRT4 VDD SDATA N/C FB_INT FB_OUT N/C DDRT3 DDRC3 GND 28-Pin 209mil SSOP 28-Pin 173mil TSSOP Block Diagram Functionality INPUTS OUTPUTS AVDD CLK_INT CLKT CLKC FB_OUTT FB_OUTT SCLK SDA SD ATA Control DDRT0 Logic DDRC0 DDRT1 DDRC1 DDRT2 DDRC2 DDRT3 FB_INT DDRC3 PLL CLK_INT DDRT4 DDRC4 DDRT5 DDRC5 0578H—02/19/04 PLL State 2.5V (nom) L L H L on 2.5V (nom) H H L H on ICS93732 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DDRC0 DDRT0 VDD DDRT1 DDRC1 GND SCLK CLK_INT N/C VDDA GND VDD DDRT2 DDRC2 GND DDRC3 DDRT3 N/C FB_OUT OUT OUT PWR OUT OUT PWR IN IN N/C PWR PWR PWR OUT OUT PWR OUT OUT N/C OUT 20 FB_INT IN 21 22 23 24 25 26 27 28 N/C SDATA VDD DDRT4 DDRC4 DDRT5 DDRC5 GND N/C I/O PWR OUT OUT OUT OUT PWR "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. Ground pin. Clock pin of I2C circuitry 5V tolerant "True" reference clock input. No Connection. 2.5V power for the PLL core. Ground pin. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. Ground pin. "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. No Connection. Feedback output, dedicated for external feedback. True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. No Connection. Data pin for I2C circuitry 5V tolerant Power supply, nominal 2.5V "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. Ground pin. 0578H—02/19/04 2 ICS93732 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . 0°C to +85°C Case Temperature . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operation Conditions TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER SYMBOL Analog / Core Supply Volta AVDD Input Voltage Level V IN Output Differential Pair VOC Crossing Voltage CONDITIONS MIN 2.3 2 TYP 2.5 2.5 MAX 2.7 3 UNITS V V 66/100/133/166MHz, VDD=2.50V 1.23 1.25 1.32 V MAX 300 300 100 -29 37 UNITS 10 mA Electrical Characteristics - Input / Supply / Common Output parameters TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER Operating Supply Current Output High Current Output Low Current High Impedance Ouptut Current SYMBOL I DD2.5 I DDPD I OH I OL I OZ High-level Output Voltage VOH Low-level Output Voltage VOL Output Capacitance1 CONDITIONS RT = 120W, CL = 12 pF at 100MHz RT = 120W, CL = 12 pF at 133MHz CL=0 pF VDD = 2.5V, VOUT = 1V VDD = 2.5V, VOUT = 1.2V MIN -48 29 TYP 236 263 -33 33 VDD = 2.7V, VOUT = V DD or GND VDD = min to max, I OH = -1mA VDD = 2.3V, I OH = -12mA VDD = min to max, I OH = 1mA VDD = 2.3V, I OH = 12mA VI = V DD or GND COUT 1. Guaranteed by design, not 100% tested in production. 0578H—02/19/04 3 2 2.25 1.95 0.05 0.3 3 mA mA mA mA V 0.1 0.4 V pF ICS93732 Timing Requirements TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS freqop Operating Clock Frequency Input Voltage level: 0-2.50V 1 d Input Clock Duty Cycle tin Clock Stabilization1 t STAB from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. MIN 22 40 TYP 50 MAX 340 60 100 UNITS MHz % µs Switching Characteristics TA = 0 - 70°C; Supply Voltage AV DD, V DD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER SYMBOL Cycle to cycle Jitter1,2 t c-c Phase Error1 Output to output Skew1 t pe CONDITIONS 66 MHz 100 / 125/ 133/167MHz 200/267MHz MIN -150 Tskew Duty Cycle (Sign Ended)1,3 DC Rise Time, Fall Time4 t R , tf TYP 100 48 47 66 MHz to 100MHz 101MHz to 267 MHz Load=120Ω/14pF 49.5 49 Notes: 1. Refers to transition on noninverting output. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 0578H—02/19/04 4 20 50 49.4 579 MAX 120 65 75 150 100 50.5 51 950 UNITS ps ps ps % % ps ICS93732 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4(H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D4(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D5(H) ACK Dummy Command Code ICS (Slave/Receiver) ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0578H—02/19/04 5 ICS93732 Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock. Affected Pin BYTE 5 Pin # Name Bit 7 2, 1 DDR0(T&C) Bit 6 4, 5 DDR1(T&C) Bit 5 Bit 4 Bit 3 13, 14 DDR2(T&C) Bit 2 17, 16 DDR3(T&C) Bit 1 Bit 0 Note: PWD = Power Up Default BYTE Affected Pin 6 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 24, 25 DDR4(T&C) Bit 2 Bit 1 26, 27 DDR5(T&C) Bit 0 Note: PWD = Power Up Default Control Function Type Output Control Output Control Reserved Reserved Output Control Output Control Reserved Reserved RW RW X X RW RW X X Control Function Type Reserved Reserved Reserved Reserved Output Control Reserved Output Control Reserved X X X X RW X RW X 0578H—02/19/04 6 Bit Control 0 1 DISABLE ENABLE DISABLE ENABLE DISABLE ENABLE DISABLE ENABLE - PWD 1 1 1 1 1 1 1 1 Bit Control 0 1 DISABLE ENABLE DISABLE ENABLE - PWD 0 0 0 1 1 1 1 1 ICS93732 c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS D E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 0.65 BASIC 0.0256 BASIC e L 0.55 0.95 .022 .037 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° L E1 INDEX AREA E 1 2 α D A A2 A1 VARIATIONS -Ce b N SEATING PLANE 28 .10 (.004) C D mm. MIN 9.90 D (inch) MAX 10.50 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP Ordering Information ICS93732yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0578H—02/19/04 7 MIN .390 MAX .413 ICS93732 c N L E1 INDEX AREA E 1 2 α D In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D SEE VARIATIONS E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS α 0° 8° aaa -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 A A2 VARIATIONS A1 N -Ce b SEATING PLANE aaa C 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS93732yG -T Example: ICS XXXX y G - T Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0578H—02/19/04 8 MAX .386