ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<120ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • Slew Rate: 1V/ns - 2V/ns 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS93V850 GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC 2 VDDI C AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 140 MHz 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD SDATA FB_INC FB_INT VDD FB_OUTT FB_OUTC GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND 48-Pin TSSOP Block Diagram Functionality INPUTS FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 SCLK SDATA Control Logic CLKT2 CLKC2 CLKT3 CLKC3 OUTPUTS AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC PLL State GND L H L H L H Bypassed/Off GND H L H L H L Bypassed/Off H L H L H On L H L H L On <20 MHz Hi-Z Hi-Z Hi-Z Hi-Z Off 2.5V L (nom) 2.5V H (nom) 2.5V <20 MHz (nom) CLKT4 CLKC4 FB_INT FB_INC CLK_INC CLK_INT CLKT5 CLKC5 PLL CLKT6 CLKC6 CLKT7 CLKC7 AVDD CLKT8 CLKC8 CLKT9 CLKC9 0423H—07/03/03 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS93V850 Preliminary Product Preview Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 PWR Ground 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 OUT "Complementar y" clocks of differential pair outputs. 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 OUT "Tr ue" Clock of differential pair outputs. Power supply 2.5V 4, 11, 21, 28, 34, 38, 45, VDD PWR 12 SCLK IN Clock input of I2C input, 5V tolerant input 13 CLK_INT IN "True" reference clock input 14 CLK_INC IN "Complementar y" reference clock input 15 V D D I 2C PWR 3.3V power for I2C 16 AVDD PWR Analog power supply, 2.5V 17 AGND PWR A n a l o g gr o u n d . 32 FB_OUTC OUT "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. 33 FB_OUTT OUT "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. 35 FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 36 FB_INC IN "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. 37 SDATA IN Data input for I2C serial input, 5V tolerant input 0423H—07/03/03 2 ICS93V850 Preliminary Product Preview Byte 0: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 3, 2 5, 6 10, 9 20, 19 22, 23 46, 47 44, 43 39, 40 PWD 1 1 1 1 1 1 1 1 Byte 1: Output Control (1= enable, 0 = disable) BIT PIN# PWD Bit 7 29, 30 1 Bit 6 27, 26 1 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 * Note: Do not change DESCRIPTION CLKT0, CLKC0 CLKT1, CLKC1 CLKT2, CLKC2 CLKT3, CLKC3 CLKT4, CLKC4 CLKT5, CLKC5 CLKT6, CLKC6 CLKT7, CLKC7 Byte 2: Reserved (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# - PWD 1 1 1 1 1 1 1 1 Byte 3: Reserved (1= enable, 0 = disable) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 Byte 4: Reserved (1= enable, 0 = disable) BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 DESCRIPTION CLKT8, CLKC8 CLKT9, CLKC9 Reserved Reserved* Reserved* Reserved Reserved Reserved this bit value. DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 5: Reserved (1= enable, 0 = disable) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# - PWD 0 0 0 0 0 1 1 0 DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) Note: Don’t write into this register, writing into this register can cause malfunction 0423H—07/03/03 3 ICS93V850 Preliminary Product Preview Absolute Maximum Ratings Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . -0.5V to 3.6V (VDDI) . . . . . . . . . . . . . . . . . . . Logic Inputs: VI (except SCLK and SDATA) . . . . . . VI (SCLK and SDATA) . . . . . . . . . Logic Outputs: VO (except SDATA) . . . . . . . . . . . . . VO (SDATA) . . . . . . . . . . . . . . . . -0.5V to 4.6V –0.5 V to VDD +0.5 V –0.5 V to VDDI2C +0.5 V –0.5 V to VDD +0.5 V –0.5 V to VDDI2C +0.5 V Input clamp current: IIK (VI < 0 or VI > VDD) . . . . +/- 50mA Output clamp current: IOK (VO < 0 or VO > VDD) +/- 50mA Continuous output current: IO (VO = 0 to VDD) . . +/- 50mA Package thermal impedance, theta JA: DGG package +89°C/W Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current SYMBOL IIH IIL IDD2.5 IDDPD IOH Output Low Current IOL High Impedance Output Current Input Clamp Voltage IOZ VIK High-level output voltage VOH Low-level output voltage VOL Input Capacitance1 Output Capacitance1 CIN COUT CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf CL = 0pf VDD = 2.3V, VOUT = 1V VDD = 2.3V, VOUT = 1.2V MIN TYP -18 UNITS µA µA mA mA mA 26 mA 100 VDD=2.7V, Vout=VDD or GND Iin = -18mA VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = GND or VDD VOUT = GND or VDD 1 Guaranteed by design, not 100% tested in production. 0423H—07/03/03 4 MAX ±10 mA V V V 0.1 0.6 3 V pF pF ICS93V850 Preliminary Product Preview Recommended Operating Condition TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Analog/core supply voltage SYMBOL MIN TYP MAX UNITS VDD, AVDD 2.3 2.5 2.7 V VDDI2C 2.3 3.6 V VIL VIH -0.3 0.4 0.36 0.5 VDD-0.4 VDD+0.3 VDDQ +0.6 VDDQ +0.6 V V V V 0.45x(VIH-VIL) 0.55x(VIH-VIL) V Input voltage level Input differential-pair voltage swing1 Input differential-pair crossing voltage Output differential-pair crossing voltage CONDITIONS DC - CLK_INT, FB_INT AC - CLK_INT, FB_INT VID VIC V VOC 1 Differential inputs signal voltages specifies the differential voltage [VTR - VCP] required for switching, where VT is the true input level and VCP is the complementary input level. Timing Requirements TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Operating clock frequency Input clock duty cycle CLK stabilization UNITS freqop 66 170 MHz dtin 40 60 % 100 µs TSTAB from VDD = 3.3V to 1% target freq. Switching Characteristics PARAMETER SYMBOL Jitter; Absoulte Jitter Tjabs Cycle to Cycle Jitter1 Tcyc -Tcyc Phase error Output to Output Skew Pulse skew t(phase error) Tskew Tskewp Half Period Jitter Typ: Propagation Delay Time Slew Rate Tjitter Hp t SLEW CONDITION 66MHz 100/125/133/167MHz 66MHz 100/125/133/167MHz MIN TYP -150 66/100/133/166MHz Bypass Mode CLK to any output Load = 120Ω/14pF MAX 120 75 110 65 150 100 100 UNITS ps ps ps ps ps ps ps 75 ps -75 4 1 1.8 Notes: 1. Refers to transition on noninverting output. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 0423H—07/03/03 5 ns 2 V/ns ICS93V850 Preliminary Product Preview General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0423H—07/03/03 6 ICS93V850 Preliminary Product Preview Recommended Layout for the ICS93V850 General Layout Precautions: Use copper flooded ground on the top signal layer under the clock buffer The area under U1 on the right is an example. Flood over the ground vias. 1) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 2) Make all power and ground traces are as wide as the via pad for lower inductance. 3) VAA for pin 16 has a low pass RC filter to decouple the digital and analog supplies. The 4.7uF capacitors may be replaced with a single low ESR device with the same total capacitance. VAA is routed on a outside signal layer. Do not cut a power or ground plane and route in it. 4) Notice that ground vias are never shared. 5) When ever possible, VCC (net V2P5 in the schematic) pins have a decoupling capacitor. Power is always routed from the plane connection via to the capacitor pad to the VCC pin on the clock buffer. Moats or plane cuts are not used to isolate power. 6) Differential mode clock output traces are routed: a. With a ground trace between the pairs. Trace is grounded on both ends. b. Without a ground trace, clock pairs are routed with a separation of at least 5 times the thickness of the dielectric. If the dielectric thickness is 4.5 mil, the trace separation is at least 18 mils. 7) Terminate differential CLK_IN and FB_IN traces after routing to buffer pads. Component Values: Ref Desg. Value C1,C4,C5, C7,C11,C12 C2,C3,C8, C9 C10 C6 R9,R12 R9 U1 Description Package .01uF CERAMIC MLC 0603 4.7uF CERAMIC MLC 1206 .22uF 2200pF 120 Ω 4.7 Ω CERAMIC MLC CERAMIC MLC 0603 0603 0603 0603 TSSOP48 ICS93701AG 0423H—07/03/03 7 ICS93V850 Preliminary Product Preview c N L E1 INDEX AREA E 1 2 D A A2 A1 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0° 8° 0° 8° α aaa -0.10 -.004 -Ce SEATING PLANE b VARIATIONS N aaa C 48 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) D mm. MIN MAX 12.40 12.60 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information ICS93V850yGT Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 0423H—07/03/03 8 D (inch) MIN .488 MAX .496