ICS950405 Integrated Circuit Systems, Inc. AMD - K8™ System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Support I2C Index read/write and block read/write operations. Uses external 14.318MHz crystal. Supports Hyper Transport Technology (HTTCLK). • • • Functionality FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 Pin Configuration *FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 VDDPCI GND PCICLK11/HTTCLK3 PCICLK10 PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 VDDPCI GND 2X PCICLK4 2X PCICLK5 2X PCICLK6 2X PCICLK7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS950405 Output Features: • 2 - Differential pair push-pull CPU clocks @ 3.3V • 9 - PCICLK (Including 1 free running) @ 3.3V • 3 - Selectable PCICLK/HTTCLK @ 3.3V • 1 - HTTCLK @ 3.3V • 1 - 48MHz @ 3.3V fixed. • 1 - 24/48MHz @ 3.3V • 3 - REF @ 3.3V, 14.318MHz. Features: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology and RESET# output to reset system if system malfunctions. • Programmable watch dog safe frequency. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS1* GND VDDREF REF2/FS2* Reset# VDDA GND CPUCLK8T0 CPUCLK8C0 GND VDDCPU CPUCLK8T1 CPUCLK8C1 VDDCPU GND GND PD#* 48MHz/FS3** GND AVDD48 24_48MHz/Sel24_48#* GND SDATA SCLK 48-SSOP * Internal Pull-Up Resistor 2X 0802F—04/22/05 This Output has 2X Default Drive and can be programmaed lower via IIC ICS950405 Pin Descriptions PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 *FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 VDDPCI GND PCICLK11/HTTCLK3 PCICLK10 PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 VDDPCI GND 2XPCICLK4 2XPCICLK5 PIN TYPE I/O PWR IN OUT PWR I/O I/O OUT PWR PWR I/O OUT OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT 23 2XPCICLK6 OUT 24 2XPCICLK7 OUT 25 26 27 SCLK SDATA GND IN I/O PWR 28 24_48MHz/Sel24_48#* 29 30 31 AVDD48 GND 48MHz/FS3** I/O PWR PWR I/O 32 PD#* 33 34 35 36 37 38 39 40 41 42 43 GND GND VDDCPU CPUCLK8C1 CPUCLK8T1 VDDCPU GND CPUCLK8C0 CPUCLK8T0 GND VDDA PWR PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR IN 44 Reset# OUT 45 46 47 48 REF2/FS2* VDDREF GND REF1/FS1* I/O PWR PWR I/O DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Supply for HTT clocks, nominal 3.3V. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Mode selection latch input pin / Hyper Transport output. Mode selection latch input pin / PCI clock output / Hyper Transport output. PCI clock output / Hyper Transport output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output / Hyper Transport output. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant Ground pin. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Ground pin. Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. Ground pin. Ground pin. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Ground pin. Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin. 3.3V power for the PLL core. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 14.318 MHz reference clock / Frequency select latch input pin. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength 0802F—04/22/05 2 ICS950405 General Description The ICS950405 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950405 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum REF (2:0) CPU DIVDER CPUCLKC (1:0) CPUCLKT (1:0) PD# SDATA SCLK FS (3:0) MODE (A,B) PCI DIVDER PCICLK (7:0, 10) Control Logic Config. PCICLK(11,9,8)/HTTCLK (3:1) HTT DIVDER Reg. HTTCLK0 SEL24_48# 0802F—04/22/05 3 ICS950405 Power Groups Pin Number VDD Description GND 2 5 Xtal, POR 9 10 PCICLK, HTTCLK O/p 16,19 15,20 PCICLK Outputs 29 27,30,33 48 MHz, Fix Analog 35,38 34,39 CPU Outputs 43 42 Analog, CPU PLL, MCLK 46 47 REF, Digital Core Mode Functionality Tables ModeA ModeB Pin7 Pin8 Pin11 0 0 HTTCLK1 HTTCLK2 PCICLK11 0 1 HTTCLK1 HTTCLK2 HTTCLK3 1 0 PCICLK8 PCICLK9 PCICLK11 1 1 HTTCLK1 PCICLK9 PCICLK11 Table1: Frequency Selection Table 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 0 0 150.00 60.00 30.00 0 1 180.00 60.00 30.00 0 1 0 210.00 70.00 35.00 1 0 1 1 240.00 60.00 30.00 1 1 0 0 270.00 67.50 33.75 1 1 0 1 233.33 66.67 33.33 1 1 1 1 1 1 0 1 266.67 66.67 33.33 300.00 75.00 37.50 Bit3 FS3 0 0 0 0 0 0 0 Bit2 FS2 0 0 0 0 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 Bit0 FS0 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0802F—04/22/05 4 ICS950405 General I2C serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0802F—04/22/05 5 Not acknowledge stoP bit ICS950405 2 I C Table: Frequency Select Register Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD SS_EN SEL24_48MHz Reserved Reserved FS3 FS2 FS1 FS0 Spread Enable Output Select Reserved Reserved Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 RW RW RW RW RW RW RW RW OFF 48MHz Reserved Reserved ON 24MHz Reserved Reserved 1 Latch X X Latch Latch Latch Latch Name Control Function Type 0 1 PWD REF0 HTTCLK0 PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 PCICLK11/HTTCLK3 PCICLK10 PCICLK0 PCICLK1 Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 24_48MHz 48MHz Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD CPUCLK8T/C_1 CPUCLK8T/C_0 REF2 REF1 PCI_Str1 PCI_Str0 PCI_Str1 PCI_Str0 Output Control Output Control Output Control Output Control PCI9,8 Strength Control only PCI11 Strength Control only RW RW RW RW RW RW RW RW Disable Disable Disable Disable 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive Enable Enable Enable Enable 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 1 1 1 1 0 1 0 1 See Table1: Frequency Selection Table 2 I C Table: Output Control Register Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 1 6 7 8 11 12 13 14 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 17 18 21 22 23 24 28 31 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # 37,36 41,40 45 48 - 0802F—04/22/05 6 ICS950405 2 I C Table: Output Control Register Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 All other PCICLK Strength Control PCICLK (7:6) Strength Control PCICLK (5) Strength Control PCICLK (4) Strength Control RW RW RW RW RW RW RW RW 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 0 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved X X X X X X X X Name Control Function Type 0 1 PWD Byte Count Programming b(7:0) RW RW RW RW RW RW RW RW Control Function Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 1 2 I C Table: Reserved Register Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 2 I C Table: Byte Count Register Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. 0 0 0 0 0 1 1 0 2 I C Table: Byte Count and Vendor ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name REV_ID3 REV_ID2 REV_ID1 REV_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Revision ID Vendor ID 0802F—04/22/05 7 ICS950405 2 I C Table: Skew Control Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name PCI/HTTSkw3 PCI/HTTSkw2 PCI/HTTSkw1 PCI/HTTSkw0 PCISkw3 PCISkw2 PCISkw1 PCISkw0 Control Function CPU-PCI/HTT 7 Step Skew Control (ps) CPU-PCI 7 Step Skew Control (ps) Type RW RW RW RW RW RW RW RW 0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 1 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A PWD 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900 1 1 0 0 1 1 0 0 2 I C Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # Name Bit 7 - ASEL Bit 6 - AEN Bit 5 Bit 4 - Reserved Reserved Bit 3 - WDTCtrl Bit 2 Bit 1 Bit 0 - WD2 WD1 WD0 Control Function Async Frequency Select AGP/PCI/ Freq Source Select Reserved Reserved Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type 0 1 PWD RW 66MHz 75.4MHz 0 RW FIX PLL CPU PLL 1 RW RW - - X X RW 290ms Base 1160ms Base 0 RW RW RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 1 1 1 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Bit 7 - M/NEN Bit Bit Bit Bit Bit Bit Bit - WDEN WDStatus WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 6 5 4 3 2 1 0 Control Function M/N Programming Enable Watchdog Enable WD Alarm Status Watch Dog Safe Freq Programming bits Type 0 1 PWD RW Disable Enable 0 RW R RW RW RW RW RW Disable Normal Enable Alarm 0 0 0 0 0 0 0 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 2 I C Table: VCO Frequency Control Register Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 N Divider Prog bit 8 N Divider Prog bit 9 Type 0 1 RW The decimal representation of N Divider in Byte 11 and 12 RW RW The decimal representation of M and N RW Divier in Byte 11 and 12 will configure the M Divider Programming RW VCO frequency. Default at power up = bits (5:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW 0802F—04/22/05 8 PWD X X X X X X X X ICS950405 2 I C Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function Type 0 1 RW RW The decimal representation of M and N RW Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = N Divider Programming RW latch-in or Byte 0 Rom table. bit (7:0) RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Control Function Type Spread Spectrum Programming b(7:0) RW RW RW RW RW RW RW RW Name Control Function Type 0 1 PWD Reserved R RW - - 0 X Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 14 Pin # Bit 7 Bit 6 - Reserved SSP14 Bit Bit Bit Bit Bit Bit - SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 5 4 3 2 1 0 Spread Spectrum Programming b(14:8) 0802F—04/22/05 9 RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X X X ICS950405 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency SYMBOL VIH VIL IIH IIL1 IIL2 IDD(op) IDDPD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors MIN 2 VSS - 0.3 -5 -200 CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Fi C Logic Inputs IN 1 Input Capacitance CINX X1 & X2 pins 1 T To 1st crossing of target Freq. Transition Time trans 1 TSTAB From VDD = 3.3 V to 1% target Freq. Clk Stabilization 1 T VT = 1.5 V Skew CPU-PCI 1 Guaranteed by design, not 100% tested in production. 0802F—04/22/05 10 11 27 1.5 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 mA 40 mA 16 5 45 3 3 4 MHz pF pF ms ms ns ICS950405 Electrical Characteristics - K8 Push Pull Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS Rising Edge Rate Falling Edge Rate Differential Voltage Change in VDIFF_DC Magnitude δV/δt δV/δt VDIFF Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential ∆VDIFF Common Mode Voltage VCM Change in Common Mode Voltage ∆VCM Jitter, Cycle to cycle tjcyc-cyc Measured at the AMD64 processor's test load. (single-ended measurement) Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. MIN TYP MAX UNITS NOTES 2 2 0.4 10 10 2.3 V/ns V/ns V 1 1 1 -150 150 mV 1 1.05 1.45 V 1 -200 200 mV 1 0 200 ps 1 Measured using the JIT2 software package with a Tek 7404 scope. TIE (Time Interval Error) measurement tja -1000 1000 Jitter, Accumulated technique: Sample resolution = 50 ps, Sample Duration = 10 µs Measurement from differential dt3 Duty Cycle 45 53 wavefrom Average value during switching RON 55 Output Impedance transition. Used for determining series 15 termination value. Measurement from differential tsrc-skew Group Skew 250 wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off 0802F—04/22/05 11 1,2,3 % 1 Ω 1 ps 1 ICS950405 Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -18 mA Output High Voltage VOH1 IOL = 9.4 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 dt1 VT = 1.5 V 1 Skew tsk1 VT = 1.5 V tjcyc-cyc1 VT = 1.5 V Jitter VT = 1.5 V tjabs1 1 MIN 2.1 TYP MAX 0.4 -22 57 2 2 55 500 500 500 16 45 UNITS V V mA mA ns ns % ps ps ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - ZCLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL1 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf11 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V Duty Cycle dt1 1 VT = 1.5 V Skew tsk1 VT = 1.5 V 3V66 tjcyc-cyc1 Jitter 0802F—04/22/05 12 MIN 12 2.4 -33 30 0.5 0.5 45 TYP MAX 55 0.55 -33 38 2 2 55 250 250 UNITS MHz Ω V V mA mA ns ns % ps ps ICS950405 Electrical Characteristics - AGPCLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH1 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V Duty Cycle dt1 1 VT = 1.5 V Skew tsk1 VT = 1.5 V 3V66 tjcyc-cyc1 Jitter MIN TYP 12 2.4 MAX 55 0.55 -33 38 2 2 55 250 250 -33 30 0.5 0.5 45 UNITS MHz Ω V V mA mA ns ns % ps ps Electrical Characteristics - REF TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V VOL = 0.8 V Output Low Current IOL5 Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 dt5 VT = 1.5 V t VT = 1.5 V jcyc-cyc5 Jitter1 tjabs5 VT = 1.5 V 0802F—04/22/05 13 MIN 2.6 16 45 TYP MAX UNITS V 0.4 V -22 mA mA 4 ns 4 ns 55 % 1000 ps 800 ps ICS950405 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS950405 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0802F—04/22/05 14 ICS950405 c N L E1 INDEX AREA SYMBOL E A A1 b c D E E1 e h L N α 1 2 a h x 45° D A A1 -Ce SEATING PLANE N .10 (.004) C 48 b In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950405yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0802F—04/22/05 15 MAX .630 ICS950405 Revision History Rev. 0.1 Issue Date Description 4/21/2005 Updated Byte 11/12 M/N programming description 0802F—04/22/05 16 Page # 8-9