ICS950602 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for PII/III™ Recommended Application: VIA Mobile PL133T and PLE133T Chipsets. Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz crystal. GND *FS2/REF1 REF0 Vtt_PWRGD# VDDREF GND X1 X2 VDDPCI *FS4/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 SDRAM_IN *CPU_STOP# *PCI_STOP# *PD# **MULTISEL GND SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS950602 Output Features: • 2 - CPU clocks @ 2.5V • 1 - Pairs of differential CPU clocks @ 3.3V • 7 - PCI including 1 free running @ 3.3V • 7 - SDRAM @ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - 24_48MHz selectable @ 3.3V • 2 - REF @ 3.3V, 14.318MHz Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CPUCLK0 CPUCLK1 VDDCPU_2.5 VDDCPU_3.3 CPUCLKT CPUCLKC GND RESET# I REF SDRAM6 GND SDRAM0 SDRAM1 VDDSDRAM SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDRAM AVDD48 48MHz/FS0* 24_48MHz/FS1* SCLK 48-Pin SSOP & TSSOP * Internal Pull-up resistor of 120K to VDD ** these inputs have 120K internal pull-down to GND Key Specifications: • CPU Output Jitter <200ps • CPU Output Skew <175ps • PCI to PCI Output Skew <500ps Block Diagram Host Swing Select Functions 0469B—12/18/02 MULTISEL0 Board Target Trace/Term Z Reference R, Iref = VDD/(3*Rr) Output Current Voh @ Z 0 50 ohms Rr = 221 1%, Iref = 5.00mA Ioh = 4* I REF 1.0V @ 50 1 50 ohms Rr = 475 1%, Iref = 2.32mA Ioh = 6* I REF 0.7V @ 50 ICS950602 Integrated Circuit Systems, Inc. General Description The ICS950602 is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessary clock signals for such a system. The ICS950602 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple. Pin Description PIN NUMBER 1, 6, 12, 23, 32, 38, 42, 5, 9, 29, 35 2 PIN NAME TYPE GND PWR VDD PWR FS2 IN DESCRIPTION Ground pins for 3.3V supply 3 . 3 V p ow e r s u p p l y L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . REF1 OUT 3.3V, 14.318MHz reference clock output. 3 REF0 OUT 3.3V, 14.318MHz reference clock output. 4 Vtt_PWRGD# IN 7 X1 IN 8 X2 OUT FS4 IN This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0) are valid and are ready to be sampled (active low) Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 10 PCICLK_F 11 17, 16, 15, 14, 13 FS3 OUT IN 3.3V PCI clock output L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . PCICLK0 OUT 3.3V PCI clock output PCICLK (5:1) OUT 3.3V PCI clock outputs 18 SDRAM_IN IN SDRAM buffer input pin. 19 CPU_STOP# IN Stops all CPUCLKs clocks at logic 0 level, when input low 20 PCI_STOP# IN 21 PD# IN 22 MULTSEL IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs. 24 SDATA I/O Data pin for I2C circuitry 5V tolerant 25 SCLK IN Clock pin for I2C circuitry 5V tolerant IN L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . FS1 26 48_24MHz FS0 OUT IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, w h e n i n p u t l ow Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Selectable 48 or 24MHz output L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 27 48MHz OUT 3.3V Fixed 48MHz clock output. AVDD48 PWR 3.3V analog power supply for 48 or 24MHz outputs. SDRAM (5:0, 6) OUT SDRAM clock outputs. 40 I REF OUT 41 RESET# OUT 43 CPUCLKC OUT 44 CPUCLKT OUT VDDCPU_3.3 VDDCPU_2.5 CPUCLK (1:0) PWR PWR OUT 28 30, 31, 33, 34, 36, 37, 39 45 46 47, 48 This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Real time system reset signal for frequency value or watchdog timer timeout. This signal is active low. "Complementary" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 3.3V power for CPU differential clocks. 2.5V power for CPU clocks. CPU clock outputs. 0469B—12/18/02 2 ICS950602 Integrated Circuit Systems, Inc. General I2C serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P *See notes on the following page. 0469B—12/18/02 3 Not acknowledge stoP bit ICS950602 Integrated Circuit Systems, Inc. Byte 0: Functionality and frequency select register (Default=0) Bit PWD Description Bit2 Bit1 Bit6 Bit5 Bit4 CPUCLK PCICLK MHz MHz FS4 FS3 FS2 FS1 FS0 Bit (2:1,6:4) Bit 3 Bit 0 Bit 7 Spread % 0 0 0 0 0 200.00 33.30 +/-0.25% center spread 0 0 0 0 1 190.00 38.00 +/-0.25% center spread 0 0 0 1 0 180.00 36.00 +/-0.25% center spread 0 0 0 1 1 170.00 34.00 +/-0.25% center spread 0 0 1 0 0 166.00 33.20 +/-0.25% center spread 0 0 1 0 1 160.00 32.00 +/-0.25% center spread 0 0 1 1 0 150.00 37.50 +/-0.25% center spread 0 0 1 1 1 145.00 36.30 +/-0.25% center spread 0 1 0 0 0 140.00 35.00 +/-0.25% center spread 0 1 0 0 1 136.00 34.00 +/-0.25% center spread 0 1 0 1 0 130.00 32.50 +/-0.25% center spread 0 1 0 1 1 124.00 31.00 +/-0.25% center spread 0 1 1 0 0 67.20 33.60 +/-0.25% center spread 0 1 1 0 1 100.90 33.63 +/-0.25% center spread 0 1 1 1 0 118.00 39.30 +/-0.25% center spread 0 1 1 1 1 134.40 33.60 +/-0.25% center spread 1 0 0 0 0 67.00 33.50 +/-0.25% center spread 1 0 0 0 1 100.50 33.50 +/-0.25% center spread 1 0 0 1 0 115.00 38.30 +/-0.25% center spread 1 0 0 1 1 133.90 33.47 +/-0.25% center spread 1 0 1 0 0 66.80 33.40 +/-0.25% center spread 1 0 1 0 1 100.20 33.40 +/-0.25% center spread 1 0 1 1 0 110.00 36.70 +/-0.25% center spread 1 0 1 1 1 133.60 33.40 +/-0.25% center spread 1 1 0 0 0 105.00 35.00 +/-0.25% center spread 1 1 0 0 1 90.00 30.00 +/-0.25% center spread 1 1 0 1 0 85.00 28.30 +/-0.25% center spread 1 1 0 1 1 78.00 39.00 +/-0.25% center spread 1 1 1 0 0 66.60 33.30 +/-0.25% center spread 1 1 1 0 1 100.00 33.30 0 to -0.5% down spread 1 1 1 1 0 75.00 37.50 +/-0.25% center spread 1 1 1 1 1 133.30 33.30 0 to -0.5% down spread 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0) Note 1 0 0 0 Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 0469B—12/18/02 4 ICS950602 Integrated Circuit Systems, Inc. Byte 1: Output Control Register (1 = enable, 0 = disable) Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 48 47 44, 43 PWD X X X X X 1 1 1 Description FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back CPUCLK0 CPUCLK1 CPUCLKT, CPUCLKC Byte 2: Output Control Register (1 = enable, 0 = disable) Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 39 10 17 16 15 14 13 11 PWD 1 1 1 1 1 1 1 1 Description SDRAM6 PCICLK_F PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Byte 3: Output Control Register (1 = enable, 0 = disable) Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 27 26 31, 30 34, 33 37, 36 PWD 0 0 1 1 0 1 1 1 Description RESET gear shift detect 1 = Enable, 0 = Disable S E L24_48: 0 = 24, 1 = 48 48MHz 24_48MHz Reserved SDRAM (4:5) SDRAM (2:3) SDRAM (0:1) Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# - PWD X X X X X X X X Description MULTSEL Read back Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0469B—12/18/02 5 ICS950602 Integrated Circuit Systems, Inc. Byte 5: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Pin# - PWD 0 0 0 Bi t 4 - 0 Bi t 3 - 0 Bi t 2 - 0 Bi t 1 Bi t 0 2 3 1 1 Description Reserved Reserved Reserved CPUCLK0 Free running control, 0 = Not free running 1 = Free running CPUCLK1 Free running control, 0 = Not free running 1 = Free running CPUCLKT/C Free running control, 0 = Not free running 1 = Free running REF1 REF0 Byte 6: Reserved Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# - PWD 0 0 0 0 0 0 0 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 7: Byte Count Read Back Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 PWD Description 0 0 0 0 Default Byte count read back is 15 Byte. 1 1 1 1 Byte 8: Vendor ID Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 PWD X X X X 0 0 0 1 Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved) 0469B—12/18/02 6 ICS950602 Integrated Circuit Systems, Inc. Byte 9: Watchdog Timer Count Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X • 1 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 0 16 • 290ms = 4.64 seconds. 0 0 0 Byte 10: Programming Enable bit 8 Watchdog Control Register Bit Name PWD Bi t 7 Program Enable 0 Bi t 6 WD Enable 0 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 WD Alarm S F4 S F3 S F2 S F1 S F0 0 1 1 1 1 1 Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table Byte 11: VCO Frequency M Divider (Reference divider) Control Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0 PWD X X X X X X X X Description N divider bit 8 The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection. Byte 12: VCO Frequency N Divider (VCO divider) Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0 PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X 0469B—12/18/02 7 ICS950602 Integrated Circuit Systems, Inc. Byte 13: Spread Spectrum Control Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0 PWD X X X X X X X X Description The Spread Spectrum will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 14: Spread Spectrum Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8 PWD X X X X X X X X Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8 0469B—12/18/02 8 ICS950602 Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage VIH 2 VDD + 0.3 V Input Low Voltage VIL VSS - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 mA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors Input Low Current Operating Supply Current IDD3.3OP Powerdown Current IDD3.3PD Input Frequency Fi Pin Inductance Lpin Input Capacitance 1 Transition time 1 Settling time 1 Clk Stabilization Delay 1 1 MIN TYP MAX UNITS mA -200 CL = 0 pF; Select @ 67 MHz 100 CL =Full load, SDRAM not running 144 IREF = 2.32 mA 280 20 IREF = 5 mA 22 14.32 VDD = 3.3 V 37 mA mA MHz 7 nH Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 45 pF Ttrans To 1st crossing of target frequency 3 ms Ts From 1st crossing to 1% target frequency 3 ms TSTAB From VDD = 3.3 V to 1% target frequency 3 ms 10 10 ns ns CIN 1 CONDITIONS 27 tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs) Guaranteed by design, not 100% tested in production. 0469B—12/18/02 9 1 1 ICS950602 Integrated Circuit Systems, Inc. Electrical Characteristics - CPUCLK(T,C) TA = 0 - 70°C; VDD=3.3V +/-5%; loads from Intel CK408B spec, Rev 1.1 (unless otherwise specified) PARAMETER SYMBOL Current Source ZO2A 1 Output Impedance Output High Voltage VOH2A Output High Current IOH32A VO = Vx TYP MAX Ω 3000 0.71 VR = 475Ω +1%; IREF = 2.32 mA; IOH = 6*IREF UNITS 1.2 -13.92 V mA tr2A VOL = -0.35V, VOH = 0.35V 175 220 467 ps 1 tf2A VOH = 0.35V, VOL = -0.35V 175 230 467 ps V2A Rs = 33.2Ω, Rp = 63.4Ω to gnd, RT-C = 475Ω 510 700 900 mV dt2A VT = crossing point 45 49 55 % 250 300 170 200 3.2 4 ns 50 200 ps TYP MAX 45 45 UNITS Differential Crossover 1 Voltage 1 Duty Cycle 1 Skew, CPUT,C to CPU tsk2A 1 tsk2A1 Skew, CPUT,C to PCI Jitter, Cycle to cycle 1 MIN 1 Rise Time Fall Time CONDITIONS 1 tjcyc-cyc2A VT (CPU) = crossing point, VT (PCI) = 1.25 V 100 MHz 133 MHz VT (CPU) = crossing point, VT (PCI) = 1.5 V VT = crossing point 2 CPU,SD = 100MHz ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLK(1:0) TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance1 Output High Voltage SYMBOL RDSP2B RDSN2B VOH2B Output Low Voltage VOL2B IOL = 1 mA Output High Current IOH2B VOH@MIN = 1.0 V, VOH@MAX = 2.375 V -27 27 Output Low Current IOL2B VOL@MIN = 1.2 V, VOL@MIN = 0.3 V 27 30 Rise Time 1 CONDITIONS 0.4 tr2B VOL = 0.4V, VOH = 2.0V tf2B VOH = 2.0V VOL = 0.4V 0.7 V V ns 55 % 60 175 ps 3.2 4 ns CPU,SD = 100MHz 140 250 CPU,SD = 133 MHz 100 250 CPU = 100, SD = 133 MHz Guaranteed by design, not 100% tested in production. 220 275 Fall Time 1 dt2B Duty Cycle Skew, CPU to CPU 1 1 Skew, CPU to PCI VT = 50% Jitter, Cycle to cycle 100MHz 133 MHz tsk2B VT = 1.25 V tsk2B1 VT (CPU) = 1.25 V, VT (PCI) = 1.5 V VT = 1.25V 1 0.4 Ω 1.6 1 1 MIN 13.5 13.5 2 VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA tjcyc-cyc2B 0469B—12/18/02 10 45 2 0.8 50 54 ps ICS950602 Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew CONDITIONS MIN RDSP11 VO = VDD*(0.5) 12 VOH11 VOL11 I OH11 I OL11 tr11 tf11 dt11 tsk11 2.4 Jitter,cycle to cycle tjcyc-cyc IOH = -1 mA 1 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V -33 30 VOL = 0.4 V, V OH = 2.4 V 0.5 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V TYP 33.33 MAX UNITS MHz 55 Ω V 0.55 -33 38 V mA mA 2.4 2.5 ns 0.5 2.25 2.5 ns 45 53 55 % 220 500 ps 300 450 ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz, 24_48MHz TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN 1 Output Frequency FO3 1 Output Impedance RDSP3 VO = VDD*(0.5) 12 1 IOH = -1 mA 2.4 Output High Voltage VOH3 1 Output Low Voltage VOL3 IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 Output High Current IOH3 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 Output Low Current IOL3 1 Rise Time tr3A VOL = 0.4 V, VOH = 2.4 V 1 1 Fall Time tf3B VOH = 2.4 V, VOL = 0.4 V 1 1 VT = 1.5 V 45 Duty Cycle dt3A 1 tjcyc-cyc3 VT = 1.5 V Jitter, cycle-to-cycle 1 Guaranteed by design, not 100% tested in production. 0469B—12/18/02 11 TYP 48 MAX 1.1 1.25 52 0.55 -23 27 2 2 55 UNITS MHz Ω V V mA mA ns ns % 200 350 ps 55 ICS950602 Integrated Circuit Systems, Inc. Electrical Characteristics - SDRAM TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL 1 CONDITIONS MIN TYP MAX UNITS RDSP5 Vo=VDD*(0.5) 10 24 Ω Output Impedance RDSN5 Vo=VDD*(0.5) 10 24 Ω Output High Voltage VOH5 IOH = -1 mA 2.4 Output Low Voltage VOL5 IOL = 1 mA 0.4 Output High Current IOH5 VOH@MIN = 2 V -46 Output Low Current IOL5 Rise Time tr5 Output Impedance 1 Fall Time Duty Cycle Skew Propagation delay SDRAM_IN to SDRAM tf5 VOH@MAX = 3.135V -54 VOL@MIN = 1 V 54 V V mA mA VOL@MAX =0.4V VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 1.6 ns 1 VOH = 2.4 V, VOL = 0.4 V 0.4 0.75 1.6 ns 1 VT = 1.5 V 45 50 55 % 1 VT = 1.5 V 30 250 ps VT = 1.5 V 2.95 4 ns 1 dt5 tsk5 1 tpdel5 53 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Frequency FO4 VO = VDD*(0.5) Output Impedance RDSP41 1 IOH = -1 mA Output High Voltage VOH4 1 IOL = 1 mA Output Low Voltage VOL4 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH41 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL4 VOL = 0.4 V, VOH = 2.4 V Rise Time tr41 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf4 1 Duty Cycle VT = 1.5 V dt1 tjcyc-cyc41 VT = 1.5 V Jitter, cycle-to-cycle 1 Guaranteed by design, not 100% tested in production. 0469B—12/18/02 12 MIN TYP 14.318 20 2.4 -29 29 1 1 45 MAX 60 1.85 1.95 0.4 -23 27 4 4 55.7 365 56 550 UNITS MHz Ω V V mA mA ns ns % ps ICS950602 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 0469B—12/18/02 13 ICS950602 Integrated Circuit Systems, Inc. Power Down Waveform 0ns 25ns 1 50ns 2 VCO Internal CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 16.7MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 0469B—12/18/02 14 ICS950602 Integrated Circuit Systems, Inc. c N SYMBOL L E1 INDEX AREA E 1 2 α h x 45° D A A A1 b c D E E1 e h L N α A1 -Ce b SEATING PLANE .10 (.004) C N 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950602yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 0469B—12/18/02 15 MAX .630 ICS950602 Integrated Circuit Systems, Inc. c N SYMBOL L E1 INDEX AREA A A1 A2 b c D E E1 e L N α aaa E 1 2 D VARIATIONS A A2 N A1 48 -Ce In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.10 -.004 D (inch) MAX 12.60 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 SEATING PLANE b D mm. MIN 12.40 aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) Ordering Information ICS950602yGT Example: ICS XXXX y G - T Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 0469B—12/18/02 16 MIN .488 MAX .496