ICS ICS952606

ICS952606
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 48-pin part
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
1 - 0.7V current-mode differential CPU pairs for ITP
•
1 - 0.7V current-mode differential SRC pair
•
9 - PCI (33MHz)
•
1 - USB, 48MHz
•
1 - DOT, 48MHz
•
2 - REF, 14.318MHz
•
3 - 3V66, 66.66MHz
•
Supports CPU clks up to 400MHz in test mode
•
Uses external 14.318MHz crystal
•
Supports undriven differential CPU, SRC pair in PD#
for power management.
1 - 3V66/VCH, selectable 48MHz or 66MHz
Key Specifications:
•
CPU/SRC outputs cycle-cycle jitter < 125ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
PCI outputs cycle-cycle jitter < 250ps
•
CPU outputs skew: < 100ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
USB/
FS2
CPU
SRC
3V66
PCI
REF
DOT
MHz
B6b5 FS_A FS_B MHz
MHz
MHz MHz
MHz
0
0
100.00 100/200 66.66 33.33 14.318 48.00
0
1
200.00 100/200 66.66 33.33 14.318 48.00
0
1
0
133.33 100/200 66.66 33.33 14.318 48.00
1
1
166.66 100/200 66.66 33.33 14.318 48.00
0
0
200.00 100/200 66.66 33.33 14.318 48.00
0
1
400.00 100/200 66.66 33.33 14.318 48.00
1
1
0
266.66 100/200 66.66 33.33 14.318 48.00
1
1
333.33 100/200 66.66 33.33 14.318 48.00
Pin Configuration
*FSA/REF0
*FSB/REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PD#
48MHz_DOT
48MHz_USB
GND
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS952606
•
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GND
IREF
CPUCLKT_ITP
CPUCLKC_ITP
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
SRCCLKT
SRCCLKC
VDD
Vtt_Pwrgd#
SDATA
SCLK
3V66_0
3V66_1
GND
VDD3V66
3V66_2
3V66_3/VCH
**120KW pull-down
48-pin SSOP
0717F—06/10/05
Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description
PIN #
PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
*FSA/REF0
*FSB/REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
20
PD#
21
22
23
24
48MHz_DOT
48MHz_USB
GND
VDD48
PIN TYPE
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up
resistor, used to power down the device. The internal clocks are
disabled and the VCO and the crystal are stopped.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
0717F—06/10/05
2
Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
30
25
26
27
28
29
30
31
32
3V66_0
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
SDATA
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
33
Vtt_Pwrgd#
34
VDD
PWR
35
SRCCLKC
OUT
36
SRCCLKT
OUT
37
GND
PWR
38
CPUCLKC0
OUT
39
CPUCLKT0
OUT
40
VDDCPU
PWR
41
CPUCLKC1
OUT
42
CPUCLKT1
OUT
43
GND
PWR
44
CPUCLKC_ITP
OUT
45
CPUCLKT_ITP
OUT
46
IREF
OUT
47
48
GND
VDDA
PWR
PWR
IN
DESCRIPTION
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
3.3V power for the PLL core.
0717F—06/10/05
3
Integrated
Circuit
Systems, Inc.
ICS952606
General Description
ICS952606 is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets. ICS952606 is driven with a 14.318MHz crystal. It
generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
PLL2
X1
X2
Frequency
Dividers
48MHz, USB, DOT, VCH
XTAL
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT0
Programmable
Spread
PLL1
SCLK
Programmable
Frequency
Dividers
SDATA
VTTPWRGD#
PD#
STOP
Logic
SRCCLKC0
3V66(3:0)
PCICLK_F (2:0)
Control
Logic
PCICLK (5:0)
CPUCLKT_ITP
FS_A
CPUCLKC_ITP
FS_B
I REF
Power Groups
Pin Number
VDD
GND
3
6
27
28
10,16
11,17
34
37
48
47
24
23
-47
40
43
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, Fix Digital, Fix Analog
IREF
CPUCLK clocks
0717F—06/10/05
4
Integrated
Circuit
Systems, Inc.
ICS952606
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
Max
VDD + 0.5V
VDD + 0.5V
150
70
115
-0.5
-65
0
Units
V
V
°C
°C
°C
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
VIH
3.3V +/-5%
Input Low Voltage
VIL
3.3V +/-5%
Input High Current
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
2
VSS 0.3
-5
IIL1
Input Low Current
IIL2
Operating Supply Current
IDD3.3OP
Powerdown Current
IDD3.3PD
Input Frequency3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
TYP
MAX
VDD + 0.3
V
0.8
V
5
uA
-5
uA
-200
uA
Full Active, CL = Full load;
260.000
350
mA
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
31.000
0.300
14.31818
35
12
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
ms
1,2
kHz
1
us
1
ns
ns
1
2
7
5
6
5
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de1,2
TSTAB
1.8
Clk Stabilization
assertion of PD# to 1st clock.
Triangular Modulation
30
33
Modulation Frequency
CPU output enable after
Tdrive_PD#
300
PD# de-assertion
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Capacitance1
UNITS NOTES
0717F—06/10/05
5
Integrated
Circuit
Systems, Inc.
ICS952606
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
1
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
749
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
3
150
756
-7
350
1150
-300
250
550
mV
1
1
1
12
140
mV
1
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
-300
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
300
5.0015
5.0266
6.000 6.0018
6.0320
7.500 7.5023
5.4000
10.000 10.0030
10.0533
5.000
279
280
30
30
700
700
125
125
1
mV
Measurement from differential
45
50.9
55
%
wavefrom
tsk3
VT = 50%
Skew
8
100
ps
Measurement from differential
tjcyc-cyc
40
125
ps
Jitter, Cycle to cycle
wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
Duty Cycle
dt3
0717F—06/10/05
6
1
1
1
Integrated
Circuit
Systems, Inc.
ICS952606
Electrical Characteristics - 3V66 Mode: 3V66 [3:0]
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Long Accuracy
ppm
see Tperiod min-max values
66.66MHz output nominal
Tperiod
Clock period
66.66MHz output spread
IOH = -1 mA
VOH
Output High Voltage
VOL
IOL = 1 mA
Output Low Voltage
V OH@MIN = 1.0 V
IOH
Output High Current
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V
IOL
Output Low Current
VOL@MAX = 0.4 V
Edge Rate
Rising edge rate
Edge Rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
tr1
Rise Time
tf1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
d
VT = 1.5 V
Duty Cycle
t1
VT = 1.5 V
tsk1
Skew
Jitter
tjcyc-cyc
MIN
-300
14.9955
14.9955
2.4
TYP
Notes
1,2
2
2
1.79
1.69
49.9
38
4
4
2
2
55
UNITS
ppm
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
80
250
ps
1
172
250
ps
1
15
MAX
300
15.0045
15.0799
0.55
-33
-33
30
1
1
0.5
0.5
45
VT = 1.5 V 3V66
1
1
1
1
1
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
2
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
IOL = 1 mA
V OH@MIN = 1.0 V
VOH@MAX = 3.135 V
VOL@MIN = 1.95 V
VOL@MAX = 0.4 V
-300
29.9910
29.9910
2.4
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V 3V66
1
1
0.5
0.5
45
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
IOH
IOL
tr1
tf1
dt1
tsk1
tjcyc-cyc
1
TYP
MAX
300
30 30.0090
30.1598
0.55
-33
-33
30
1.79
1.69
51.2
59
140
38
4
4
2
2
55
500
250
UNITS
Notes
ppm
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
ps
1,2
2
2
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
2
0717F—06/10/05
7
1
1
1
1
1
1
1
Integrated
Circuit
Systems, Inc.
ICS952606
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70°C; V DD = 3.3V +/-5%; CL = 5-10 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
Long Accuracy
ppm
see Tperiod min-max values
-200
200
48.008 MHz output nominal
20.8257
20.8340
Clock period
T period
Output High Voltage
V OH
I OH = -1 mA
2.4
I OL = 1 mA
0.55
Output Low Voltage
V OL
V OH@MIN = 1.0 V
-33
Output High Current
I OH
-33
V OH@MAX = 3.135 V
30
V OL @MIN = 1.95 V
Output Low Current
I OL
V OL@MAX = 0.4 V
38
Edge Rate
Rising edge rate
2
4
Edge Rate
Falling edge rate
2
4
UNITS
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
Notes
1,2
2
1
1
Rise Time
t r1
V OL = 0.4 V, V OH = 2.4 V
0.5
0.87
1
ns
1
Fall Time
Duty Cycle
t f1
dt1
V OH = 2.4 V, V OL = 0.4 V
V T = 1.5 V
125us period jitter
(8kHz frequency modulation
amplitude)
0.5
45
0.89
52.3
1
55
ns
%
1
1
0.64
2
ns
1
Long Term Jitter
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
2
0717F—06/10/05
8
Integrated
Circuit
Systems, Inc.
ICS952606
Electrical Characteristics - VCH, 48MHz, 48MHz, USB
TA = 0 - 70°C; V DD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
T period
V OH
V OL
-200
20.8257
2.4
Output High Current
I OH
Output Low Current
I OL
see Tperiod min-max values
48.008 MHz output nominal
I OH = -1 mA
I OL = 1 mA
V OH@MIN = 1.0 V
V OH@MAX = 3.135 V
V OL @MIN = 1.95 V
V OL@MAX = 0.4 V
Rising edge rate
Falling edge rate
Edge Rate
Edge Rate
TYP
MAX
UNITS Notes
200
20.8340
1,2
2
38
2
2
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
0.55
-33
-33
30
1
1
1
1
Rise Time
t r1
V OL = 0.4 V, V OH = 2.4 V
1
1.45
2
ns
1
Fall Time
Duty Cycle
t f1
dt1
V OH = 2.4 V, V OL = 0.4 V
V T = 1.5 V
125us period jitter
(8kHz frequency modulation
amplitude)
1
45
1.37
52.5
2
55
ns
%
1
1
0.63
6
ns
1
Long Term Jitter
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
2
0717F—06/10/05
9
Integrated
Circuit
Systems, Inc.
ICS952606
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
Output High Current
IOH1
Output Low Current
IOL1
Rise Time
Fall Time
Skew
Duty Cycle
tr11
tf11
tsk11
dt11
Jitter
tjcyc-cyc1
VOH1
VOL1
CONDITIONS
MIN
TYP
MAX
see Tperiod min-max values
-300
300
14.31818 MHz output nominal 69.8270
69.8550
IOH = -1 mA
2.4
IOL = 1 mA
0.4
V OH@MIN = 1.0 V, V OH@MAX =
-29
-23
3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4
29
27
V
VOL = 0.4 V, VOH = 2.4 V
1
1.93
2
VOH = 2.4 V, VOL = 0.4 V
1
1.92
2
VT = 1.5 V
14
500
VT = 1.5 V
45
53.8
55
VT = 1.5 V
400 1000
UNITS
Notes
ppm
ns
V
V
1
mA
mA
ns
ns
ps
%
1
1
1
1
ps
1
1
Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
3V66 to PCI
DOT-USB
DOT-VCH
SYMBOL
S3V66-PCI
SDOT_USB
SDOT_VCH
CONDITIONS
3V66 (3:0) leads 33MHz PCI
180 degrees out of phase
in phase
0717F—06/10/05
10
MIN
1.50
0.00
0.00
TYP
2
MAX
3.50
1.00
1.00
UNITS
ns
ns
ns
Integrated
Circuit
Systems, Inc.
ICS952606
General I2C serial interface information for the ICS952606
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0717F—06/10/05
11
Not acknowledge
stoP bit
Integrated
Circuit
Systems, Inc.
ICS952606
I2C Table: Read-Back Register
Byte 0
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
Bit 0
-
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Freq Select 1 Read
FSB
Back
Freq Select 0 Read
FSA
Back
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
SRC Free-Running
Bit 7
SRC/SRC#
Control
Bit 6
SRC
Output Control
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
Bit 1
CPUT1/CPUC1
Output Control
Bit 0
CPUT0/CPUC0
Output Control
I2C Table: Output Control Register
Byte 2
Pin #
Type
R
R
R
R
R
Type
RW
RW
R
R
R
R
RW
RW
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
READBACK of
CPU(2:0) Frequency
1
STOPPAB
LE
Disable
Enable
RESERVED
RESERVED
RESERVED
RESERVED
Disable
Enable
Disable
Enable
PWD
X
X
X
X
X
X
X
X
0
PWD
FREE-RUN
0
1
X
X
X
X
1
1
Name
SRC_PD#
Drive Mode
Control Function
Type
0
1
PWD
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in PCI_Stop#
(byte3bit7)
RW
Driven
Hi-Z
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
CPUT1_PD# Drive Mode
CPUT0_PD# Drive Mode
RESERVED
RESERVED
RESERVED
RESERVED
0:driven in PD#
1: Tri-stated
RESERVED
RESERVED
RESERVED
RW
RW
-
RESERVED
Driven
Hi-Z
Driven
Hi-Z
RESERVED
RESERVED
RESERVED
X
0
0
X
X
X
Control Function
PCI_Stop# Control
0:all stoppable PCI are
stopped
RESERVED
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD
RW
Enable
Disable
1
RW
RW
RW
RW
RW
RW
RESERVED
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
X
1
1
1
1
1
1
Bit 7
I2C Table: Output Control Register
Byte 3
Pin #
Name
Bit 7
PCI_Stop#
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
0717F—06/10/05
12
Integrated
Circuit
Systems, Inc.
ICS952606
I2C Table: Output Control Register
Byte 4
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
48MHz_USB
2x output drive
48MHz_USB
RESERVED
RESERVED
RESERVED
PCICLKF2
PCICLKF1
PCICLKF0
I2C Table: Output Control Register
Byte 5
Pin #
Name
Bit 7
DOT_48MHZ
Bit 6
CPU_T/C_ITP
3V66_3/VHC
Bit 5
Select
Control Function
Type
0
1
PWD
0=2x drive
RW
2x drive
normal
1
Output Control
RESERVED
RESERVED
RESERVED
Output Control
Output Control
Output Control
RW
RW
RW
RW
Control Function
Output Control
Output Control
Type
RW
RW
0
Disable
Disable
1
Enable
Enable
PWD
1
1
Output Select
RW
3V66
VCH
0
Disable
Enable
RESERVED
RESERVED
RESERVED
Stoppable Free-run
Stoppable Free-run
Stoppable Free-run
1
X
X
X
1
1
1
Bit 4
3V66_3/VHC
Output Control
RW
Disable
Enable
1
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
3V66_2
3V66_1
3V66_0
RESERVED
Output Control
Output Control
Output Control
RW
RW
RW
RESERVED
Disable
Enable
Disable
Enable
Disable
Enable
X
1
1
1
Control Function
Test Clock Mode
FS_A and FS_B
Operation
SRC Frequency
Select
Down/Center
Spread Spectrum
Enable
Output Control
Output Control
Type
-
0
Disable
-
1
Enable
-
PWD
0
0
-
Normal
Test Mode
0
-
100MHz
200MHz
0
-
Center
Spread
ON
Enable
Enable
0
RW
RW
Down
Spread
OFF
Disable
Disable
1
1
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
0
0
0
0
1
I2C Table: Output Control and Fix Frequecy Register
Byte 6
Pin #
Name
Bit 7
Test Clock Mode
Bit 6
RESERVED
Bit 5
CPU *2 Test Clock
Bit 4
SRC Frequency Select
Bit 3
Spread Spectrum Type
Bit 2
Spread Spectrum Mode
Bit 1
Bit 0
REF1
REF0
I2C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Bit 7
RID3
Bit 6
RID2
Bit 5
RID1
Bit 4
RID0
Bit 3
VID3
Bit 2
VID2
Bit 1
VID1
Bit 0
VID0
REVISION ID
VENDOR ID
0717F—06/10/05
13
0
Integrated
Circuit
Systems, Inc.
ICS952606
I2C Table: Byte Count Register
Byte 8
Control Function
Type
0
1
PWD
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Writing to this register
will configure how
many bytes will be read
back, default is 08 = 8
bytes.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
1
0
0
0
I2C Table: Reserved
Byte 9
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
-
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWD
X
X
X
X
X
X
X
X
I2C Table: Reserved
Byte 10
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
M/N prog Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
M/N prog Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
-
0
1
Disable
Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWD
0
X
X
X
X
X
X
X
Control Function
N Divider Bit 8
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Type
RW
0
-
1
-
PWD
X
RW
-
-
X
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Bit 7
N Div8
Bit 6
-
M Div6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
0717F—06/10/05
14
Integrated
Circuit
Systems, Inc.
I2C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
Bit 7
N Div7
Bit 6
N Div6
Bit 5
N Div5
Bit 4
N Div4
Bit 3
N Div3
Bit 2
N Div2
Bit 1
N Div1
Bit 0
N Div0
I2C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Bit 7
SSP7
Bit 6
SSP6
Bit 5
SSP5
Bit 4
SSP4
Bit 3
SSP3
Bit 2
SSP2
Bit 1
SSP1
Bit 0
SSP0
I2C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Bit 7
Reserved
Bit 6
Reserved
Bit 5
SSP13
Bit 4
SSP12
Bit 3
SSP11
Bit 2
SSP10
Bit 1
SSP9
Bit 0
SSP8
ICS952606
Control Function
The decimal
representation of N Div
(8:0) is equal to VCO
divider value. Default
at power up = latch-in
or Byte 0 Rom table.
Control Function
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
Control Function
Reserved
Reserved
It is recommended to
use ICS Spread %
table for spread
programming.
0717F—06/10/05
15
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
X
X
X
X
X
X
Integrated
Circuit
Systems, Inc.
ICS952606
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PWRDWN#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI
USB/DOT
REF
1
Normal
Normal
Normal
Normal
66MHz
33MHz
48MHz
14.318MHz
0
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Low
Low
Low
Low
Note
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the
tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
0717F—06/10/05
16
Integrated
Circuit
Systems, Inc.
ICS952606
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
3V66_3/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0717F—06/10/05
17
Integrated
Circuit
Systems, Inc.
ICS952606
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0717F—06/10/05
18
Integrated
Circuit
Systems, Inc.
ICS952606
c
N
SYMBOL
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
A1
-Ce
b
SEATING
PLANE
.10 (.004) C
VARIATIONS
N
48
D mm.
MIN
15.75
D (inch)
MAX
16.00
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952606yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0717F—06/10/05
19
MAX
.630
Integrated
Circuit
Systems, Inc.
ICS952606
Revision History
Rev.
E
F
Issue Date Description
1. Updated pinout and pin description.
6/9/2005 2. Updated LF Ordering Information to RoHS Compliant.
6/10/2005 Updated Block Diagram
0717F—06/10/05
20
Page #
1-3, 19
4