ICS97U877 Integrated Circuit Systems, Inc. 1.8V Wide Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864 Pin Configuration 1 2 3 4 5 6 A B C Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_18) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Auto PD when input signal is at a certain logic state D E F G H J K Switching Characteristics: • Period jitter: 40ps • Half-period jitter: 60ps • CYCLE - CYCLE jitter 40ps • OUTPUT - OUTPUT skew: 40ps 52-Ball BGA Top View A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 Block Diagram CLKT0 Powerdown Control and Test Logic OS AVDD LD* LD* or OE CLKC0 LD*, OS or OE CLKT1 CLKT2 CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ OE CLKC2 40 CLKC1 PLL bypass CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLK_INT CLKT6 CLK_INC CLKC6 PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. CLKT7 ICS97U877 10 21 CLKC7 CLKT8 11 CLKC8 CLKT9 20 CLKC9 FB_OUTT FB_OUTC 0792A—04/15/04 30 1 CLKT3 CLKC3 CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ 10K-100k VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND 31 40-Pin MLF CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS ICS97U877 Pin Descriptions Te r m i n a l Name Electrical Characteristics Description AGND Analog Ground Ground AVDD A n a l o g p ow e r 1.8 V nominal CLK_INT C l o ck i n p u t w i t h a ( 1 0 K - 1 0 0 K O h m ) p u l l d o w n r e s i s t o r Differential input CLK_INC Complentar y clock input with a (10K-100K Ohm) pulldown resistor Differential input FB_INT Feedback clock input Differential input FB_INC Complementary feedback clock input Differential input FB_OUTT Feedback clock output Differential output FB_OUTC Complementary feedback clock output Differential output OE Output Enable (Asynchronous) LVCMOS input OS Output Select (tied to GND or VDDQ) LVCMOS input GND Ground Ground VDDQ Logic and output power 1.8V nominal CLKT[0:9] Clock outputs Differential outputs CLKC[0:9] Complementary clock outputs Differential outputs NB No ball The PLL clock buffer, ICS97U877, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97U877 is characterized for operation from 0°C to 70°C. 0792A—04/15/04 2 ICS97U877 Function Table Inputs Outputs PLL AVDD OE OS CLK_INT CLK_INT CLKT CLKC FB_OUTT FB_OUTC GND H X L H L H L H Bypassed/Off GND H X H L H L H L Bypassed/Off GND L H L H *L(Z) *L(Z) L H Bypassed/Off GND L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L Bypassed/Off 1.8V(nom) L H L H *L(Z) *L(Z) L H On 1.8V(nom) L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L On 1.8V(nom) H X L H L H L H On 1.8V(nom) H X H L H L H L On 1.8V(nom) X X L L *L(Z) *L(Z) *L(Z) *L(Z) Off 1.8V(nom) X X H H Reser ved *L(Z) means the outputs are disabled to a low stated meeting the IODL limit. 0792A—04/15/04 3 ICS97U877 Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0°C to +70°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS Input High Current IIH VI = VDDQ or GND (CLK_INT, CLK_INC) Input Low Current (OE, IIL VI = VDDQ or GND OS, FB_INT, FB_INC) Output Disabled Low OE = L, VODL = 100mV IODL 100 Current CL = 0pf @ 270MHz IDD1.8 Operating Supply Current CL = 0pf IDDLD VDDQ = 1.7V Iin = -18mA VIK Input Clamp Voltage VDDQ - 0.2 IOH = -100 µA VOH High-level output voltage IOH = -9 mA 1.1 1.45 IOL=100 µA 0.25 VOL Low-level output voltage IOL=9 mA VI = GND or VDDQ CIN 2 Input Capacitance1 1 COUT 2 VOUT = GND or VDDQ Output Capacitance 1 Guaranteed by design, not 100% tested in production. 0792A—04/15/04 4 MAX UNITS ±250 µA ±10 µA µA 300 500 -1.2 0.10 0.6 3 3 mA µA V V V V V pF pF ICS97U877 Recommended Operating Condition (see note1) TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) SYMBOL MIN PARAMETER CONDITIONS V , A Supply Voltage 1.7 DDQ VDD CLK_INT, CLK_INC, FB_INC, VIL Low level input voltage FB_INT OE, OS CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ VIH High level input voltage FB_INT 0.65 x VDDQ OE, OS DC input signal voltage (note VIN -0.3 2) DC - CLK_INT, CLK_INC, 0.3 Differential input signal FB_INC, FB_INT VID AC - CLK_INT, CLK_INC, voltage (note 3) 0.6 FB_INC, FB_INT Output differential crossVOX VDDQ/2 - 0.10 voltage (note 4) Input differential crossVIX VDDQ/2 - 0.15 voltage (note 4) IOH High level output current IOL Low level output current Operating free-air TA 0 temperature Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing. 0792A—04/15/04 5 TYP 1.8 MAX 1.9 UNITS V 0.35 x VDDQ V 0.35 x VDDQ V V V VDD/2 VDDQ + 0.3 V VDDQ + 0.4 V VDDQ + 0.4 V VDDQ/2 + 0.10 V VDDQ2 + 0.15 V -9 9 mA mA 70 °C ICS97U877 Timing Requirements TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS MIN MAX PARAMETER SYMBOL Max clock frequency freqop 1.8V+0.1V @ 25°C 95 370 UNITS MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 350 MHz 40 60 % 15 µs Input clock duty cycle CLK stabilization dtin TSTAB Switching Characteristics1 TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION SYMBOL MIN ten Output enable time OE to any output tdis OE to any output Output disable time tjit (per) -30 Period jitter tjit(hper) -60 Half-period jitter 1 Input Clock Input slew rate SLr1(i) 0.5 Output Enable (OE), (OS) 1.5 Output clock slew rate SLr1(o) tjit(cc+) 0 Cycle-to-cycle period jitter tjit(cc-) 0 t( )dyn -20 Dynamic Phase Offset -50 Static Phase Offset tSPO2 tskew Output to Output Skew 30.00 SSC modulation frequency SSC clock input frequency 0.00 deviation PLL Loop bandwidth (-3 dB 2.0 from unity gain) Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. 0792A—04/15/04 6 TYP 4.73 5.82 2.5 2.5 0 MAX 8 8 30 60 4 3 40 -40 20 50 40 33 UNITS ns ns ps ps v/ns v/ns v/ns ps ps ps ps ps kHz -0.50 % MHz ICS97U877 Parameter Measurement Information VDD V(CLKC) V(CLKC) ICS97U877 GND Figure 1. IBIS Model Output Load VDD/2 C = 10 pF - GND ICS97U877 R = 10Ω Z = 60Ω SCOPE Z = 50Ω Z = 2.97" R = 1MΩ V(TT) C = 1 pF Z = 120Ω R = 10Ω Z = 60Ω Z = 50Ω Z = 2.97" R = 1MΩ V(TT) C = 1 pF C = 10 pF Note: VTT = GND GND -VDD/2 Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 0792A—04/15/04 7 ICS97U877 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT tC(n) YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter 0792A—04/15/04 8 t ( ) n+1 ICS97U877 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t jit(hper_n+1) t jit(hper_n) 1 fo tjit(hper) = t jit(hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslr tslf Figure 8. Input and Output Slew Rates 0792A—04/15/04 9 ICS97U877 CK CK FBIN FBIN t( t( ) SSC OFF SSC ON t( ) SSC OFF SSC ON t( )dyn t( )dyn t( )dyn Figure 9. Dynamic Phase Offset 50% VDDQ OE t en Y 50% VDDQ Y Y/ Y OE 50% VDDQ t dis Y 50 % VDDQ Y Figure 10. Time delay between OE and Clock Output (Y, Y) 0792A—04/15/04 10 )dyn ICS97U877 Figure 11. AVDD Filtering - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz). 0792A—04/15/04 11 ICS97U877 C Seating Plane A1 Numeric Designations for Horizontal Grid b REF T 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) D d TYP D1 - e - TYP TOP VIEW E c REF h TYP - e - TYP E1 0.12 C ALL DIMENSIONS IN MILLIMETERS D E 7.00 Bsc 4.50 Bsc T Min/Max 0.86/1.00 ----- BALL GRID ----HORIZ VERT e 0.65 Bsc 6 10 Max. TOTAL 60 d Min/Max 0.35/0.45 h Min/Max 0.15/0.21 D1 E1 5.85 Bsc 3.25 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, MO-205*, MO-225** 10-0055 Ordering Information ICS97U877yHLF-T Example: ICS XXXX y H LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0792A—04/15/04 12 REF. DIMENSIONS b c 0.575 0.625 ** ICS97U877 (Ref.) Seating Plane (N D -1)x e (Ref.) A1 Index Area ND & NE Even A3 N L N 2 2 E2 or E Top View (NE -1)x e (Ref.) E2 2 Sawn Singulation b (Ref.) A D are Even 1 Anvil Singulation 1 (Typ.) e 2 If N & N D E e ND & NE Odd D2 2 Thermal Base D2 0.08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE ALL DIMENSIONS IN MILLIMETERS N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 40 10 10 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 0.30 / 0.50 SYMBOL A A1 A3 b e MIN. MAX. 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC D2 MIN. / MAX. E2 MIN. / MAX. SPECIAL NON-JEDEC ALL DIM. SAME EXCEPT AS BELOW: 4.35 / 4.65 5.05 / 5.35 Source Reference: MLF2™SER 10-0053 Ordering Information ICS97U877yKLF-T Example: ICS XXXX y K LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type 0792A—04/15/04 Prefix ICS = Standard Device 13